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An Introduction to High-Level Synthesis

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An Introduction to High-Level Synthesis [3B2-8] mdt2009040008.3d 17/7/09 13:24 Page 8 High-Level Synthesis An Introduction to High-Level Synthesis Philippe Coussy Michael Meredith Universite´ de Bretagne-Sud, Lab-STICC Forte Design Systems Daniel D. Gajski Andres Takach University of California, Irvine Mentor Graphics today would even think of program- Editor’s note: ming a complex software application High-level synthesis raises the design abstraction level and allows rapid gener- solely by using an assembly language. ation of optimized RTL hardware for performance, area, and power require- In the hardware domain, specification ments. This article gives an overview of state-of-the-art HLS techniques and languages and design methodologies tools. 1,2 Tim Cheng, Editor in Chief have evolved similarly. For this reason, ÀÀ until the late 1960s, ICs were designed, optimized, and laid out by hand. Simula- THE GROWING CAPABILITIES of silicon technology tion at the gate level appeared in the early 1970s, and and the increasing complexity of applications in re- cycle-based simulation became available by 1979. Tech- cent decades have forced design methodologies niques introducedduring the 1980s included place-and- and tools to move to higher abstraction levels. Raising route, schematic circuit capture, formal verification, the abstraction levels and accelerating automation of and static timing analysis. Hardware description lan- both the synthesis and the verification processes have guages (HDLs), such as Verilog (1986) and VHDL for this reason always been key factors in the evolu- (1987), have enabled wide adoption of simulation tion of the design process, which in turn has allowed tools. These HDLs have also served as inputs to logic designers to explore the design space efficiently and synthesis tools leading to the definition of their synthe- rapidly. sizable subsets. During the 1990s, the first generation of In the software domain, for example, machine commercial high-level synthesis (HLS) tools was avail- code (binary sequence) was once the only language able commercially.3,4 Around the same time, research that could be used to program a computer. In the interest on hardware-software codesign including ÀÀ 1950s, the concept of assembly language (and assem- estimation, exploration, partitioning, interfacing, com- bler) was introduced. Finally, high-level languages munication, synthesis, and cosimulation gained mo- ÀÀ (HLLs) and associated compilation techniques were mentum.5 The concept of IP core and platform-based developed to improve software productivity. HLLs, design started to emerge.6-8 In the 2000s, there has which are platform independent, follow the rules of been a shift to an electronic system-level (ESL) para- human language with a grammar, a syntax, and a se- digm that facilitates exploration, synthesis, and verifica- mantics. They thus provide flexibility and portability tion of complex SoCs.9 This includes the introduction by hiding details of the computer architecture. As- of languages with system-level abstractions, such as sembly language is today used only in limited scenar- SystemC (http://www.systemc.org), SpecC (http:// ios, primarily to optimize the critical parts of a www.cecs.uci.edu/~specc), or SystemVerilog (IEEE program when there is an absolute need for speed 1800-2005; http://standards.ieee.org), and the intro- and code compactness, or both. However, with the duction of transaction-level modeling (TLM). The growing complexity of both modern system architec- ESL paradigm shift caused by the rise of system com- tures and software applications, using HLLs and com- plexities, a multitude of components in a product pilers clearly generates better overall results. No one (hundreds of processors in a car, for instance), 0740-7475/09/$26.00 c 2009 IEEE Copublished by the IEEE CS and the IEEE CASS IEEE Design & Test of Computers 8 Authorized licensed use limited to: Columbia University. Downloaded on January 7, 2010 at 18:37 from IEEE Xplore. Restrictions apply. [3B2-8] mdt2009040008.3d 17/7/09 13:24 Page 9 a multitude of versions of a chip (for better product dif- ferentiation), and an interdependency of component Specification suppliers forced the market to focus on hardware and software productivity, dependability, interoperabil- Compilation ity, and reusability. In this context, processor custom- ization and HLS have become necessary paths to Formal model efficient ESL design.10 The new HLS flows, in addition to reducing the time for creating the hardware, also Allocation Scheduling help reduce the time to verify it as well as facilitate Library Binding other flows such as power analysis. Raising the hardware design’s abstraction level is Generation essential to evaluating system-level exploration for ar- chitectural decisions such as hardware and software RTL architecture design, synthesis and verification, memory organiza- tion, and power management. HLS also enables Logic synthesis reuse of the same high-level specification, targeted to accommodate a wide range of design constraints ... and ASIC or FPGA technologies. Typically, a designer begins the specification of an Figure 1. High-level synthesis (HLS) design steps. application that is to be implemented as a custom processor, dedicated coprocessor or any other cus- tom hardware unit such as interrupt controller, Key concepts bridge, arbiter, interface unit, or a special function Starting from the high-level description of an appli- unit with a high-level description capture of the cation, an RTL component library, and specific design desired functionality, using an HLL. This first step constraints, an HLS tool executes the following tasks thus involves writing a functional specification (an (see Figure 1): untimed description) in which a function consumes 1. compiles the specification, all its input data simultaneously, performs all compu- 2. allocates hardware resources (functional units, tations without any delay, and provides all its output storage components, buses, and so on), data simultaneously. At this abstraction level, varia- 3. schedules the operations to clock cycles, bles (structure and array) and data types (typically 4. binds the operations to functional units, floating point and integer) are related neither to the 5. binds variables to storage elements, hardware design domain (bits, bit vectors) nor to 6. binds transfers to buses, and the embedded software. Realistic hardware imple- 7. generates the RTL architecture. mentation thus requires conversion of floating-point and integer data types into bit-accurate data types Tasks 2 through 6 are interdependent, and for a de- of specific length (not a standard byte or word size, signer to achieve the optimal solution, they would ide- as in software) with acceptable computation accu- ally be optimized in conjunction. To handle real-world racy, while generating an optimized hardware archi- designs, however, the tasks are commonly executed in tecture starting from this bit-accurate specification. sequence to manage the computational complexity of HLS tools transform an untimed (or partially timed) synthesis. The particular order of some of the synthesis high-level specification into a fully timed implementa- tasks, as well as a measure of how well the interdepen- tion.10-13 They automatically or semiautomatically gen- dencies are estimated and accounted for, significantly erate a custom architecture to efficiently implement impacts the generated design’s quality. More details the specification. In addition to the memory banks are available elsewhere.10-13 and the communication interfaces, the generated ar- chitecture is described at the RTL and contains a Compilation and modeling data path (registers, multiplexers, functional units, HLS always begins with the compilation of the and buses) and a controller, as required by the given functional specification. This first step transforms specification and the design constraints. the input description into a formal representation. July/August 2009 9 Authorized licensed use limited to: Columbia University. Downloaded on January 7, 2010 at 18:37 from IEEE Xplore. Restrictions apply. [3B2-8] mdt2009040008.3d 17/7/09 13:24 Page 10 High-Level Synthesis This first step traditionally includes several code opti- control dependencies, data dependencies between mizations such as dead-code elimination, false data basic blocks can be added to the CDFG model as dependency elimination, and constant folding and shown in the hierarchical task graph representation loop transformations. used in the SPARK tool.14,16 The formal model produced by the compilation classically exhibits the data and control dependen- Allocation cies between the operations. Data dependencies Allocation defines the type and the number of can be easily represented with a data flow graph hardware resources (for instance, functional units, (DFG) in which every node represents an operation storage, or connectivity components) needed to sat- and the arcs between the nodes represent the input, isfy the design constraints. Depending on the HLS 12 output, and temporary variables. A pure DFG mod- tool, some components may be added during sched- els data dependencies only. In some cases, it is pos- uling and binding tasks. For example, the connectiv- sible to get this model by removing the control ity components (such as buses or point-to-point dependencies of the initial specification from the connections among components) can be added be- model at compile time. To do so, loops are com- fore or after binding and scheduling tasks.
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