The Challenges of Hardware Synthesis from C-Like Languages
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An Introduction to High-Level Synthesis
High-Level Synthesis An Introduction to High-Level Synthesis Philippe Coussy Michael Meredith Universite´ de Bretagne-Sud, Lab-STICC Forte Design Systems Daniel D. Gajski Andres Takach University of California, Irvine Mentor Graphics today would even think of program- Editor’s note: ming a complex software application High-level synthesis raises the design abstraction level and allows rapid gener- solely by using an assembly language. ation of optimized RTL hardware for performance, area, and power require- In the hardware domain, specification ments. This article gives an overview of state-of-the-art HLS techniques and languages and design methodologies tools. 1,2 ÀÀTim Cheng, Editor in Chief have evolved similarly. For this reason, until the late 1960s, ICs were designed, optimized, and laid out by hand. Simula- THE GROWING CAPABILITIES of silicon technology tion at the gate level appeared in the early 1970s, and and the increasing complexity of applications in re- cycle-based simulation became available by 1979. Tech- cent decades have forced design methodologies niques introduced during the 1980s included place-and- and tools to move to higher abstraction levels. Raising route, schematic circuit capture, formal verification, the abstraction levels and accelerating automation of and static timing analysis. Hardware description lan- both the synthesis and the verification processes have guages (HDLs), such as Verilog (1986) and VHDL for this reason always been key factors in the evolu- (1987), have enabled wide adoption of simulation tion of the design process, which in turn has allowed tools. These HDLs have also served as inputs to logic designers to explore the design space efficiently and synthesis tools leading to the definition of their synthe- rapidly. -
A Compiler Infrastructure for Static and Hybrid Analysis of Discrete Event System Models
UNIVERSITY OF CALIFORNIA, IRVINE A Compiler Infrastructure for Static and Hybrid Analysis of Discrete Event System Models DISSERTATION submitted in partial satisfaction of the requirements for the degree of DOCTOR OF PHILOSOPHY in Computer Engineering by Tim Schmidt Dissertation Committee: Professor Rainer D¨omer,Chair Professor Kwei-Jay Lin Professor Fadi Kurdahi 2018 c 2018 Tim Schmidt TABLE OF CONTENTS Page LIST OF FIGURES v LIST OF TABLES vii LIST OF ALGORITHMS viii LIST OF ACRONYMS ix ACKNOWLEDGMENTS x CURRICULUM VITAE xii ABSTRACT OF THE DISSERTATION xvi 1 Introduction 1 1.1 System Level Design . .1 1.2 SystemC . .3 1.3 Recoding Infrastructure for SystemC (RISC) . .7 1.3.1 Software Stack . .7 1.3.2 Tool Flow . .8 1.4 Segment Graph . 11 1.5 Goals . 19 1.6 Related Work . 22 1.6.1 LECS Group . 22 1.6.2 Other Related Work . 25 2 Static Communication Graph Generation 28 2.1 Introduction . 28 2.1.1 Related work . 31 2.2 Thread Communication Graph . 32 2.3 Static Compiler Analysis . 34 2.3.1 Thread Communication Graph . 34 2.3.2 Module Hierarchy . 37 2.3.3 Optimization and Designer Interaction . 38 2.3.4 Visualization . 38 2.3.5 Accuracy and Limitations . 39 ii 2.4 Experiments . 39 2.4.1 Mandelbrot Renderer . 39 2.4.2 AMBA Bus Model . 41 2.4.3 S2C Testbench . 42 2.5 Summary . 43 3 Static Analysis for Reduced Conflicts 45 3.1 Channel Analysis . 45 3.1.1 Introduction . 46 3.1.2 Conflict Analysis . 49 3.1.3 Port Call Path Sensitive Segment Graphs . -
Synchronously Waiting on Asynchronous Operations
Document No. P1171R0 Date 2018-10-07 Reply To Lewis Baker <[email protected]> Audience SG1, LEWG Synchronously waiting on asynchronous operations Overview The paper P1056R0 introduces a new std::experimental::task<T> type. This type represents an asynchronous operation that requires applying operator co_await to the task retrieve the result. The task<T> type is an instance of the more general concept of Awaitable types. The limitation of Awaitable types is that they can only be co_awaited from within a coroutine. For example, from the body of another task<T> coroutine. However, then you still end up with another Awaitable type that must be co_awaited within another coroutine. This presents a problem of how to start executing the first task and wait for it to complete. task<int> f(); task<int> g() { // Call to f() returns a not-yet-started task. // Applying operator co_await() to the task starts its execution // and suspends the current coroutine until it completes. int a = co_await f(); co_return a + 1; } int main() { task<int> t = g(); // But how do we start executing g() and waiting for it to complete // when outside of a coroutine context, such as in main()? int x = ???; return x; } This paper proposes a new function, sync_wait(), that will allow a caller to pass an arbitrary Awaitable type into the function. The function will co_await the passed Awaitable object on the current thread and then block waiting for that co_await operation to complete; either synchronously on the current thread, or asynchronously on another thread. When the operation completes, the result is captured on whichever thread the operation completed on. -
Lock-Free Programming
Lock-Free Programming Geoff Langdale L31_Lockfree 1 Desynchronization ● This is an interesting topic ● This will (may?) become even more relevant with near ubiquitous multi-processing ● Still: please don’t rewrite any Project 3s! L31_Lockfree 2 Synchronization ● We received notification via the web form that one group has passed the P3/P4 test suite. Congratulations! ● We will be releasing a version of the fork-wait bomb which doesn't make as many assumptions about task id's. – Please look for it today and let us know right away if it causes any trouble for you. ● Personal and group disk quotas have been grown in order to reduce the number of people running out over the weekend – if you try hard enough you'll still be able to do it. L31_Lockfree 3 Outline ● Problems with locking ● Definition of Lock-free programming ● Examples of Lock-free programming ● Linux OS uses of Lock-free data structures ● Miscellanea (higher-level constructs, ‘wait-freedom’) ● Conclusion L31_Lockfree 4 Problems with Locking ● This list is more or less contentious, not equally relevant to all locking situations: – Deadlock – Priority Inversion – Convoying – “Async-signal-safety” – Kill-tolerant availability – Pre-emption tolerance – Overall performance L31_Lockfree 5 Problems with Locking 2 ● Deadlock – Processes that cannot proceed because they are waiting for resources that are held by processes that are waiting for… ● Priority inversion – Low-priority processes hold a lock required by a higher- priority process – Priority inheritance a possible solution L31_Lockfree -
CMS Application Multitasking
z/VM Version 7 Release 1 CMS Application Multitasking IBM SC24-6258-00 Note: Before you use this information and the product it supports, read the information in “Notices” on page 337. This edition applies to version 7, release 1, modification 0 of IBM® z/VM® (product number 5741-A09) and to all subsequent releases and modifications until otherwise indicated in new editions. Last updated: 2018-09-12 © Copyright International Business Machines Corporation 1992, 2018. US Government Users Restricted Rights – Use, duplication or disclosure restricted by GSA ADP Schedule Contract with IBM Corp. Contents List of Figures....................................................................................................... ix List of Tables........................................................................................................ xi About This Document..........................................................................................xiii Intended Audience.................................................................................................................................... xiii Where to Find More Information...............................................................................................................xiii Links to Other Documents and Websites............................................................................................ xiii How to Send Your Comments to IBM.....................................................................xv Summary of Changes for z/VM CMS Application Multitasking.............................. -
Automating Non-Blocking Synchronization in Concurrent Data Abstractions
Automating Non-Blocking Synchronization In Concurrent Data Abstractions Jiange Zhang Qing Yi Damian Dechev University of Colorado at University of Colorado at University of Central Florida Colorado Springs, CO, USA Colorado Springs, CO, USA Orlando, FL, USA [email protected] [email protected] [email protected] Abstract—This paper investigates using compiler tion needs. We show that by automatically weaving syn- technology to automatically convert sequential C++ chronization schemes with sequential implementations of data abstractions, e.g., queues, stacks, maps, and trees, data structures, many efficient lock-free data structures to concurrent lock-free implementations. By auto- matically tailoring a number of state-of-the-practice can be made readily available, with performance compet- synchronization methods to the underlying sequen- itive to that of the manually crafted ones by experts. tial implementations of different data structures, our The key technical difference between our work and exist- automatically synchronized code can attain perfor- ing STM research is that we support multiple synchroniza- mance competitive to that of concurrent data struc- tion strategies and automatically select the best strategy tures manually-written by experts and much better performance than heavier-weight support by software for each piece of code at compile time. No existing compiler transactional memory (STM). for STM supports automatic tailoring of synchronizations to what is needed by different pieces of code. The compiler I. Introduction algorithms we present are the first to do this. While we The advent of the multi-core era has brought multi- mostly rely on standard compiler techniques (e.g., pointer threaded programming to the mainstream and with it the and data-flow analysis), the problem formulations and challenges of managing shared data among the threads. -
Mutual Exclusion: Classical Algorithms for Locks
Mutual Exclusion: Classical Algorithms for Locks Bill Scherer Department of Computer Science Rice University [email protected] COMP 422 Lecture 20 March 2008 Motivation Ensure that a block of code manipulating a data structure is executed by only one thread at a time • Why? avoid conflicting accesses to shared data (data races) —read/write conflicts —write/write conflicts • Approach: critical section • Mechanism: lock —methods – acquire – release • Usage —acquire lock to enter the critical section —release lock to leave the critical section 2 Problems with Locks • Conceptual —coarse-grained: poor scalability —fine-grained: hard to write • Semantic —deadlock —priority inversion • Performance —convoying —intolerance of page faults and preemption 3 Lock Alternatives • Transactional memory (TM) + Easy to use, well-understood metaphor – High overhead (so far) ± Subject of much active research • Ad hoc nonblocking synchronization (NBS) + Thread failure/delay cannot prevent progress + Can be faster than locks (stacks, queues) – Notoriously difficult to write – every new algorithm is a publishable result + Can be “canned” in libraries (e.g. java.util) 4 Synchronization Landscape Ad Hoc NBS Fine Locks Software HW TM (STM) TM Programmer Effort Coarse Canned Locks NBS System Performance 5 Properties of Good Lock Algorithms • Mutual exclusion (safety property) —critical sections of different threads do not overlap – cannot guarantee integrity of computation without this property • No deadlock —if some thread attempts to acquire the lock, then some -
Synchronization Key Concepts: Critical Sections, Mutual Exclusion, Test-And-Set, Spinlocks, Blocking and Blocking Locks, Semaphores, Condition Variables, Deadlocks
Synchronization key concepts: critical sections, mutual exclusion, test-and-set, spinlocks, blocking and blocking locks, semaphores, condition variables, deadlocks Ali Mashtizadeh and Lesley Istead David R. Cheriton School of Computer Science University of Waterloo Fall 2019 1 / 56 Thread Synchronization All threads in a concurrent program share access to the program's global variables and the heap. The part of a concurrent program in which a shared object is accessed is called a critical section. What happens if several threads try to access the same global variable or heap object at the same time? 2 / 56 Critical Section Example /* Note the use of volatile; revisit later */ int ________volatiletotal = 0; void add() f void sub() f int i; int i; for (i=0; i<N; i++) f for (i=0; i<N; i++) f total++; total--; g g g g If one thread executes add and another executes sub what is the value of total when they have finished? 3 / 56 Critical Section Example (assembly detail) /* Note the use of volatile */ int ________volatiletotal = 0; void add() f void sub() f loadaddr R8 total loadaddr R10 total for (i=0; i<N; i++) f for (i=0; i<N; i++) f lw R9 0(R8) lw R11 0(R10) add R9 1 sub R11 1 sw R9 0(R8) sw R11 0(R10) g g g g 4 / 56 Critical Section Example (Trace 1) Thread 1 Thread 2 loadaddr R8 total lw R9 0(R8) R9=0 add R9 1 R9=1 sw R9 0(R8) total=1 <INTERRUPT> loadaddr R10 total lw R11 0(R10) R11=1 sub R11 1 R11=0 sw R11 0(R10) total=0 One possible order of execution. -
Concurrent Programming Without Locks
Concurrent Programming Without Locks KEIR FRASER University of Cambridge Computer Laboratory and TIM HARRIS Microsoft Research Cambridge Mutual exclusion locks remain the de facto mechanism for concurrency control on shared-memory data structures. However, their apparent simplicity is deceptive: it is hard to design scalable locking strategies because locks can harbour problems such as priority inversion, deadlock and convoying. Furthermore, scalable lock-based systems are not readily composable when building compound operations. In looking for solutions to these problems, interest has developed in non- blocking systems which have promised scalability and robustness by eschewing mutual exclusion while still ensuring safety. However, existing techniques for building non-blocking systems are rarely suitable for practical use, imposing substantial storage overheads, serialising non-conflicting operations, or requiring instructions not readily available on today’s CPUs. In this paper we present three APIs which make it easier to develop non-blocking implemen- tations of arbitrary data structures. The first API is a multi-word compare-and-swap operation (MCAS) which atomically updates a set of memory locations. This can be used to advance a data structure from one consistent state to another. The second API is a word-based software transactional memory (WSTM) which can allow sequential code to be re-used more directly than with MCAS and which provides better scalability when locations are being read rather than being updated. The third API is an object-based software transactional memory (OSTM). OSTM allows a more streamlined implementation than WSTM, but at the cost of re-engineering the code to use OSTM objects. We present practical implementations of all three of these APIs, built from operations available across all of today’s major CPU families. -
Enabling Task Level Parallelism in Handelc Thamer S
Enabling Task Level Parallelism in HandelC Thamer S. AbuYasin Submitted to the Department of Electrical Engineering & Computer Science and the Faculty of the Graduate School of the University of Kansas in partial fulfillment of the requirements for the degree of Master’s of Science Thesis Committee: Dr. David Andrews: Chairperson Dr. Arvin Agah Dr. Perry Alexander Date Defended 2007/12/14 The Thesis Committee for Thamer S. AbuYasin certifies That this is the approved version of the following thesis: Enabling Task Level Parallelism in HandelC Committee: Chairperson Date Approved i Chapter 1 Abstract HandelC is a programming language used to target hardware and is similar in syntax to ANSI-C. HandelC offers constructs that allow programmers to express instruction level parallelism. Also, HandelC offers primitives that allow task level parallelism. However, HandelC does not offer any runtime support that enables programmers to express task level parallelism efficiently. This thesis discusses this issue and suggests a support library called HCthreads as a solution. HCthreads offers a subset of Pthreads functionality and interface relevant to the HandelC environment. This study offers means to identify the best configuration of HC- threads to achieve the highest speedups in real systems. This thesis investigates the issue of integrating HandelC within platforms not supported by Celoxica. A support library is implemented to solve this issue by utilizing the high level abstractions offered by Hthreads. This support library abstracts away any HWTI specific synchronization making the coding experience quite close to software. HCthreads is proven effective and generic for various algorithms with different threading behaviors. HCthreads is an adequate method to implement recursive algorithms even if no task level parallelism is warranted. -
Parallel Systemc/TLM Simulation of Hardware Components Described for High-Level Synthesis Denis Becker
Parallel SystemC/TLM Simulation of Hardware Components described for High-Level Synthesis Denis Becker To cite this version: Denis Becker. Parallel SystemC/TLM Simulation of Hardware Components described for High- Level Synthesis. Artificial Intelligence [cs.AI]. Université Grenoble Alpes, 2017. English. NNT: 2017GREAM082. tel-01709813v3 HAL Id: tel-01709813 https://hal.archives-ouvertes.fr/tel-01709813v3 Submitted on 18 Sep 2018 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. THÈSE Pour obtenir le grade de DOCTEUR DE LA COMMUNAUTÉ UNIVERSITÉ GRENOBLE ALPES Spécialité : Informatique Arrêté ministériel : 25 mai 2016 Présentée par Denis Becker Thèse dirigée par Matthieu Moy et co-encadrée par Jérôme Cornet préparée au sein du Laboratoire Verimag, de STMicroelectronics et de l’École Doctorale de Mathématiques, Sciences et Technologies de l’Information, Informatique Simulation Parallèle en SystemC/TLM de Composants Matériels décrits pour la Synthèse de Haut-Niveau Parallel SystemC/TLM Simulation of Hardware Components described for High-Level Synthesis Thèse soutenue publiquement le 11 décembre 2017, devant le jury composé de : M. Frédéric Pétrot Professeur, Université Grenoble Alpes, France, Président M. Rainer Dömer Professeur, University of California, Irvine, CA, États-Unis, Rapporteur M. -
INTEGRATING ALGORITHM-LEVEL DESIGN and SYSTEM-LEVEL DESIGN THROUGH SPECIFICATION Synthesisintegrating Algorithm-Level Design
INTEGRATING ALGORITHM-LEVEL DESIGN AND SYSTEM-LEVEL DESIGN THROUGH SPECIFICATION SYNTHESIS A Dissertation Presented by Jiaxing Zhang to The Department of Electrical and Computer Engineering in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Computer Engineering Northeastern University Boston, Massachusetts August 2014 To my family. i Contents List of Figures v List of Tables vii List of Acronyms viii Acknowledgments x Abstract xi 1 Introduction 1 1.1 Specification Gap . 2 1.2 Flexibility and Overhead Trade-off . 3 1.3 Problem Definition and Goals . 5 1.4 Contributions . 5 1.5 Overview . 8 2 Background 9 2.1 EDA Designs . 9 2.2 Algorithm Level Design . 12 2.2.1 MATLAB/Simulink Modeling Environments . 14 2.3 System-Level Design . 15 2.3.1 Design Abstractions . 17 2.3.2 System Level Design Languages . 18 2.4 Related Work . 20 2.4.1 Bridging Design Gaps . 20 2.4.2 Flexibility Overhead: Granularity Challenges . 24 2.4.3 Flexibility Overhead: SW Synthesis . 24 2.5 Summary . 25 3 Specification Synthesis 27 3.1 Specification Synthesis Foundations . 27 3.1.1 Structural Semantics . 29 3.1.2 Execution Semantics . 31 ii 3.2 Algo2Spec Design . 31 3.2.1 Leaf Synthesizer . 33 3.2.2 Hierarchy Synthesizer . 37 3.2.3 Granularity Discussions . 43 3.3 Algorithm-Architecture Co-Design Flow . 43 3.4 Experimental Results . 45 3.4.1 MJPEG Encoder Synthesis Example . 46 3.4.2 Productivity Gain . 51 3.5 Summary . 53 4 Specification Granularity 54 4.1 Introduction . 54 4.2 Background: Specification Performance Analysis .