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(System)Verilog to Chisel Translation for Faster Hardware Design Jean Bruant, Pierre-Henri Horrein, Olivier Muller, Tristan Groleat, Frédéric Pétrot

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(System)Verilog to Chisel Translation for Faster Hardware Design Jean Bruant, Pierre-Henri Horrein, Olivier Muller, Tristan Groleat, Frédéric Pétrot (System)Verilog to Chisel Translation for Faster Hardware Design Jean Bruant, Pierre-Henri Horrein, Olivier Muller, Tristan Groleat, Frédéric Pétrot To cite this version: Jean Bruant, Pierre-Henri Horrein, Olivier Muller, Tristan Groleat, Frédéric Pétrot. (System)Verilog to Chisel Translation for Faster Hardware Design. 2020 31th International Symposium on Rapid System Prototyping (RSP), Sep 2020, VIrtual Conference, France. hal-02949112 HAL Id: hal-02949112 https://hal.archives-ouvertes.fr/hal-02949112 Submitted on 25 Sep 2020 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. (System)Verilog to Chisel Translation for Faster Hardware Design Jean Bruant∗;y, Pierre-Henri Horreinz, Olivier Mullery, Tristan Groleat´ x and Fred´ eric´ Petrot´ y OVHcloud, ∗Paris, zLyon, xBrest, France yUniv. Grenoble Alpes, CNRS, Grenoble INP1, TIMA, Grenoble, France Abstract—Bringing agility to hardware developments has been target, we also successfully use it into our production FPGA- a long-running goal for hardware communities struggling with based network functions at OVHcloud. limitations of current hardware description languages such as (System)Verilog or VHDL. The numerous recent Hardware Chisel introduces many features and concepts intended Construction Languages such as Chisel are providing enhanced to improve hardware design efficiency which are especially ways to design complex hardware architectures with notable useful for the design of complex IPs and in large projects. academic and industrial successes. While the latter environments However most existing large projects are made of thousands are now mature and perfectly suited for brand new projects, of lines of (System)Verilog or VHDL code. Similarly, complex migrating partially or entirely existing Verilog code-base proves to be a challenging and very time-consuming process. Successful pieces of hardware are often reused in larger projects along migrations need to be able to leverage finely tuned existing with many dependencies. In order to leverage the power of hardware descriptions as a basis to build complex systems Chisel on such legacy code-bases, the first step is to translate through simple iterations. This article introduces sv2chisel, an the existing HDL into Chisel. When performed manually, this open-source automated (System)Verilog to Chisel translator as process is long, tedious and error-prone. entry point for this iterative migration processes. Our tool achieved the proper translation, with on-par resource usage of a To address this issue, we propose in this paper to translate real-world production FPGA design at OVHcloud as well as two legacy (System)Verilog projects into Chisel ones, ready to independent open-source Verilog projects: a MIPS core and the be inserted within a larger Chisel hierarchy, to undergo deep size-optimized 32-bit RISC-V core PicoRV32. refactoring or to be integrated with existing Chisel generators. Index Terms—Hardware description languages, Agile develop- ment, EDA tool, Source code translation Note that we limit ourselves to the synthesizable subset of SystemVerilog that is in practice a limited extension of Verilog [7]. We believe this will be beneficial to the hardware I. INTRODUCTION designers by giving them higher level constructs to refactor the VHDL and Verilog have reigned unchallenged for two entire code after translation, and limits the burden of creating decades as reference hardware description languages. A first signal level interfaces for instantiation, which takes a lot of breach was opened by the introduction of SystemVerilog in time but adds nothing to the design. The source code of our the early 2000’s, rapidly followed by higher abstraction level translator sv2chisel is available on GitHub [8]. proposals allowing more efficient hardware developments [1] These languages aim at specifying the same hardware [2]. Despite embedding many useful modern programming concepts but are based on different programming paradigms: paradigms, SystemVerilog advanced concepts such as object- (System)Verilog relies on an event-based semantic to depict oriented programming are indeed partially supported in simu- underlying hardware while Chisel is based on explicit hard- lation context but have not been integrated into main synthesis ware objects assembled through object-oriented and functional tools. generators. In addition Chisel is strongly typed while (Sys- With the end of Dennard scaling leading to an increas- tem)Verilog provides very few different types. Performing the ing demand for specialized hardware, the adoption of these translation from (System)Verilog to Chisel thus requires a languages has risen, although mainly in niche areas. These sequence of analysis to perform the appropriate abstraction. Hardware Construction Languages (HCL) can be seen as This includes type analysis, to infer the proper high-level types domain specific languages that leverage the power of high- from possibly less structured information, and data-flow and level languages like Python, Scala, etc, to build efficient control-flow analysis to abstract the expressions, functions and hardware generators that produce, in the end, synthesizable their parameters, loops and conditionals, etc. VHDL or Verilog code. Our work does not intend to abstract the original code In this work, we focus on the Chisel [3] HCL, which is quite into a high-level refactored functional object-oriented code. mature and has been proven successful in the development The process is thus more straightforward than, for example, of complex circuits, notably rocket-chip, the original RISC-V decompilation of optimized assembly into C [9], because both core generator [4] and Google Edge TPU (Tensor Processing languages have control structures and share many constructs Unit) [5]. Chisel was initially designed to gain agility in RISC- such as function and module hierarchy. It is however not V microprocessors tape-out process [6]. Despite this initial trivial, as we shall explain in the following sections. II. RELATED WORK on the work done in the FIRRTL compiler [13]. It has been a very valuable starting point – most notably for expression Translating algorithms or structured data from one repre- representation, above which we introduced all the generative sentation to another is a recurrent task in most computer- subset of Verilog. aided fields. Simplest cases can be solved through stateless processing with tools such as awk or perl. However when (System)Verilog control flow, data flow or semantic issues become more complex, advanced analysis and transformations on an inter- mediate representation (IR) are required. Due to the substantial Lexing / Parsing differences between (System)Verilog and Chisel, our translator Transforms Transforms follows this second scheme. Transforms FIRRTL A first work exhibiting similarities, as (System)Verilog is of + quite lower abstraction than Chisel, is related to decompila- Extensions tion [9]. The principle here is to abstract assembly code into structured C, to target other architectures, but mainly to build a reusable, understandable code, to ease maintenance or reverse Emission engineer algorithms. The authors develop data and control flow analyses to build C statements from abstract sequential (non-vliw) optimized assembly. The former recovers high- Chisel (scala) level language expressions while the latter captures control Fig. 1. Main processing steps of sv2chisel statements (loops, conditionals). They traverse dependency graphs and either use generic patterns to recognize the control structures, or study the registers assignments to build the III. TRANSLATION higher-level expressions. They also perform simple data type recovery. In our case, control statement and assignments are A. sv2chisel Translator Structure in general sufficiently similar for not being an issue. However, Figure 1 presents the structure of our translator with the registers identification and types recovery is at the core of our classical stages of any translator or compiler. We parse a work. synthesizable (System)Verilog file using ANTLR 4 [14], which An other work that relates to ours is [10] that focuses on the builds an abstract syntax tree that we eventually map on our discovery of memorizing elements in VHDL. This issue was custom IR. It is based on FIRRTL which has been extended very important before the standardization of the descriptions most notably to support Verilog generative statements and for the hardware synthesis tools (IEEE Std 1076.6-1999), as syntactic-sugars requiring a few transformations to be mapped the simulation semantic of the language made this discovery to Chisel constructs. Four kinds of analysis and transforma- particularly tricky. The authors build a Petri Net that represents tions, main contributions of this work, are then performed the behavior of the circuit. Using semantic preserving reduc- on this IR: 1) clock inference, 2) reset inference, 3) types tion techniques, they achieve a minimal form from which they inference, 4) (System)Verilog syntactic-sugar translation. extract
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