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FPGA Designs with Verilog and Systemverilog

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FPGA Designs with Verilog and Systemverilog FPGA designs with Verilog and SystemVerilog Meher Krishna Patel Created on : Octorber, 2017 Last updated : May, 2020 More documents are freely available at PythonDSP Table of contents Table of contents i 1 First project 1 1.1 Introduction.................................................1 1.2 Creating the project............................................1 1.3 Digital design using ‘block schematics’..................................1 1.4 Manual pin assignment and compilation.................................8 1.5 Load the design on FPGA.........................................8 1.6 Digital design using ‘Verilog codes’.................................... 10 1.7 Pin assignments using ‘.csv’ file...................................... 11 1.8 Converting the Verilog design to symbol................................. 11 1.9 Convert Block schematic to ‘Verilog code’ and ‘Symbol’........................ 14 1.10 Conclusion................................................. 17 2 Overview 18 2.1 Introduction................................................. 18 2.2 Modeling styles............................................... 18 2.2.1 Continuous assignment statements................................ 18 2.2.2 Comparators using Continuous assignment statements..................... 19 2.2.3 Structural modeling........................................ 22 2.2.4 Procedural assignment statements................................ 24 2.2.5 Mixed modeling.......................................... 25 2.3 Conclusion................................................. 26 3 Data types 27 3.1 Introduction................................................. 27 3.2 Lexical rules................................................. 27 3.3 Data types................................................. 27 3.4 Logic values................................................. 27 3.5 Number representation........................................... 28 3.6 Signed numbers............................................... 28 3.7 Operators.................................................. 29 3.8 Arithmetic operator............................................ 29 3.8.1 Bitwise operators.......................................... 29 3.8.2 Relational operators........................................ 30 3.8.3 Logical operators.......................................... 30 3.8.4 Shift operators........................................... 30 3.8.5 Concatenation and replication operators............................. 30 3.8.6 Conditional operator........................................ 30 3.8.7 Parameter and localparam..................................... 31 3.8.8 localparam............................................. 32 3.8.9 Parameter and defparam..................................... 32 3.9 Conclusion................................................. 34 i 4 Procedural assignments 35 4.1 Introduction................................................. 35 4.2 Combinational circuit and sequential circuit............................... 35 4.3 Concurrent statements and sequential statements............................ 36 4.4 ‘always’ block................................................ 36 4.5 Blocking and Non-blocking assignment.................................. 36 4.6 Guidelines for using ‘always’ block.................................... 38 4.6.1 ‘always’ block for ‘combinational designs’............................ 38 4.6.2 ‘always’ block for ‘latched designs’................................ 38 4.6.3 ‘always’ block for ‘sequential designs’............................... 38 4.7 If-else statement.............................................. 39 4.8 Case statement............................................... 40 4.9 Problem with Loops............................................ 41 4.10 Loop using ‘if’ statement......................................... 41 4.11 Conclusion................................................. 43 5 VHDL designs in Verilog 44 5.1 Introduction................................................. 44 5.2 VHDL designs in Verilog.......................................... 44 5.3 Conclusion................................................. 45 6 Visual verifications of designs 46 6.1 Introduction................................................. 46 6.2 Flip flops.................................................. 46 6.2.1 D flip flop.............................................. 46 6.2.2 D flip flop with Enable port.................................... 47 6.3 Counters................................................... 47 6.3.1 Binary counter........................................... 48 6.3.2 Mod-m counter........................................... 49 6.4 Clock ticks................................................. 51 6.5 Seven segment display........................................... 51 6.5.1 Implementation........................................... 52 6.5.2 Test design for 7 segment display................................. 53 6.6 Visual verification of Mod-m counter................................... 55 6.7 Conclusion................................................. 56 7 Finite state machine 57 7.1 Introduction................................................. 57 7.2 Comparison: Mealy and Moore designs.................................. 57 7.3 Example: Rising edge detector...................................... 57 7.3.1 State diagrams: Mealy and Moore design............................ 58 7.3.2 Implementation........................................... 58 7.3.3 Outputs comparison........................................ 60 7.3.4 Visual verification......................................... 60 7.4 Glitches................................................... 61 7.4.1 Combinational design in asynchronous circuit.......................... 61 7.4.2 Unfixable Glitch.......................................... 62 7.4.3 Combinational design in synchronous circuit........................... 62 7.5 Moore architecture and Verilog templates................................ 63 7.5.1 Regular machine.......................................... 63 7.5.2 Timed machine........................................... 67 7.5.3 Recursive machine......................................... 70 7.6 Mealy architecture and Verilog templates................................ 73 7.6.1 Regular machine.......................................... 74 7.6.2 Timed machine........................................... 75 7.6.3 Recursive machine......................................... 77 7.7 Examples.................................................. 79 7.7.1 Regular Machine : Glitch-free Mealy and Moore design.................... 79 7.7.2 Timed machine: programmable square wave........................... 84 7.7.3 Recursive Machine : Mod-m counter............................... 85 7.8 When to use FSM design......................................... 86 7.9 Conclusion................................................. 87 8 Design Examples 88 8.1 Introduction................................................. 88 8.2 Random number generator........................................ 88 8.2.1 Linear feedback shift register (LFSR).............................. 88 8.2.2 Visual test............................................. 91 8.3 Shift register................................................ 91 8.3.1 Bidirectional shift register..................................... 92 8.3.2 Parallel to serial converter..................................... 94 8.3.3 Serial to parallel converter..................................... 95 8.3.4 Test for Parallel/Serial converters................................. 96 8.4 Random access memory (RAM)...................................... 98 8.4.1 Single port RAM.......................................... 98 8.4.2 Visual test : single port RAM................................... 100 8.4.3 Dual port RAM.......................................... 101 8.4.4 Visual test : dual port RAM................................... 102 8.5 Read only memory (ROM)........................................ 103 8.5.1 ROM implementation using RAM (block ROM)........................ 103 8.5.2 Visual test............................................. 104 8.6 Queue with first-in first-out functionality................................ 105 8.6.1 Queue design............................................ 105 8.6.2 Visual test............................................. 106 9 Testbenches 109 9.1 Introduction................................................. 109 9.2 Testbench for combinational circuits................................... 109 9.2.1 Half adder.............................................. 109 9.3 Testbench with ‘initial block’....................................... 110 9.3.1 Read data from file......................................... 113 9.3.2 Write data to file.......................................... 114 9.4 Testbench for sequential designs...................................... 115 9.5 Conclusion................................................. 120 10 SystemVerilog for synthesis 121 10.1 Introduction................................................. 121 10.2 Verilog, VHDL and SystemVerilog.................................... 121 10.3 ‘logic’ data type............................................... 122 10.4 Specialized ‘always’ blocks......................................... 123 10.4.1 ‘always_comb’........................................... 123 10.4.2 ‘always_latch’........................................... 124 10.4.3 ‘always_ff’............................................. 125 10.5 User define types.............................................. 126 10.5.1 ‘typedef’..............................................
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