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An Electronic System Level Modeling Approach for the Design and Verification of Low-Power Systems-On Chip Ons Mbarek

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An Electronic System Level Modeling Approach for the Design and Verification of Low-Power Systems-On Chip Ons Mbarek An electronic system level modeling approach for the design and verification of low-power systems-on chip Ons Mbarek To cite this version: Ons Mbarek. An electronic system level modeling approach for the design and verification of low- power systems-on chip. Other [cs.OH]. Université Nice Sophia Antipolis, 2013. English. NNT : 2013NICE4023. tel-00837662v2 HAL Id: tel-00837662 https://tel.archives-ouvertes.fr/tel-00837662v2 Submitted on 18 Nov 2013 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. UNIVERSITE DE NICE-SOPHIA ANTIPOLIS ECOLE DOCTORALE STIC SCIENCES ET TECHNOLOGIES DE L’INFORMATION ET DE LA COMMUNICATION T H E S E pour l’obtention du grade de Docteur en Sciences de l’Université de Nice-Sophia Antipolis Mention Informatique présentée et soutenue publiquement par Ons MBAREK Une Approche de Modélisation au Niveau Système pour la Conception et la Vérification de Systèmes sur Puce à Faible Consommation An Electronic System Level Modeling Approach for the Design and Verification of Low-Power Systems-on-Chip Thèse dirigée par Michel AUGUIN Laboratoire LEAT, Université de Nice-Sophia Antipolis –CNRS, Sophia Antipolis soutenue le 29/05/2013 Jury : M. Robert DE SIMONE D.R. Président M. Frédéric ROUSSEAU Pr. Rapporteur M. Jean-Didier LEGAT Pr. Rapporteur M. Michel AUGUIN D.R. Directeur de Thèse Mme. Florence MARANINCHI Pr. Examinatrice M. Alain PEGATOQUET M.C. Examinateur Abstract : a SoC power management solution can be defined by a low-power architecture composed of multiple power domains and a power management strategy for power domains states control. If these two elements are energy-efficient, an energy-efficient solution can be obtained. This approach requires inferring power structural elements and their related behavior in the chip internal logic. A strategy adjusting the power domains states must respect structural and functional dependencies due to the physical power domains composition. This strong relationship between power architecture and its management strategy must be explored at early design stages to find the most energy-efficient solution. Low-power design standards have recently enabled low-power architecture exploration starting from the Register Transfer Level (RTL) by defining semantics to specify power architecture, simulate and check its behavior along with the initial functional one. But, these standards miss semantics for reusable power domain control interface making power management strategies exploration tedious. The RTL-based semantics defined by these standards constrain also their use at Transaction-Level of Modeling (TLM) for fast and easy exploration. This dissertation proposes extensions to low-power standards to fill these gaps. It provides a complete study of power optimization opportunities based on composition and management of power domains in Transaction-Level (TL) functional models within a common USLPAF framework. USLPAF includes a methodology that combines design and verification of TL low-power models. To apply this methodology, USLPAF incorporates a library of modeling techniques and built-in features. Keywords: Systems-on-Chip, TLM, Low-Power Design and Verification, Low-Power Design Standards, Power Domains, Energy-Efficient Power Management Solution, Semantics. Résumé : une solution de gestion de puissance d’un système sur puce peut être définie par une architecture de faible puissance composée de multiples domaines d'alimentation et de leur stratégie de gestion. Si ces deux éléments sont économes en énergie, une solution efficace en énergie peut être obtenue. Cette approche nécessite l’ajout d’éléments structurels de puissance et de leurs comportements. Une stratégie de gestion doit respecter les dépendances structurelles et fonctionnelles dues au placement physique des domaines d'alimentation. Cette relation forte entre l'architecture et sa stratégie de gestion doit être analysée tôt dans le flot de conception pour trouver la solution de gestion de puissance la plus efficace. De récentes normes de conception basse consommation définissent des sémantiques pour la spécification, simulation et vérification d’architecture de faible puissance au niveau transfert de registres (RTL). Mais elles manquent une sémantique d’interface de gestion des domaines d'alimentation réutilisable ce qui alourdit l’exploration. Leurs sémantiques RTL ne sont pas aussi utilisables au niveau transactionnel pour une exploration plus rapide et facile. Pour combler ces lacunes, cette thèse étend ces normes et fournit une étude complète des possibilités d'optimisation de puissance basées sur la composition et la gestion des domaines d'alimentation pour des modèles fonctionnels transactionnels utilisant un environnement commun USLPAF. USLPAF comprend une méthodologie alliant conception et vérification des modèles transactionnels de faible consommation, ainsi qu’une bibliothèque de techniques de modélisation et fonctions prédéfinies pour appliquer cette méthodologie. Mots Clés: Systèmes sur Puce, Niveau Transactionnel, Conception et Vérification de Faible Consommation, Normes de Conception Basse Consommation, Domaines d’Alimentation, Solution de Gestion d’Energie Efficace en Energie, Sémantique. Contents Table of Contents viii Acknowledgments ix List of Figures xvi List of Tables xvii Acronyms & Abbreviations xviii 1’ Introduction (In French)1 1’.1 Problématique..................................1 1’.1.1 L’optimisation de la consommation d’énergie dans un système sur puce...................................1 1’.1.2 L’abstraction faible consommation..................5 1’.2 Thèse......................................8 1’.3 Aperçu de la thèse............................... 10 1’.3.1 Contributions.............................. 10 1’.3.2 Sommaire................................ 13 1 Introduction 15 1.1 Problem Statement............................... 15 CONTENTS 1.1.1 Power Optimization in Systems-on-Chip............... 15 1.1.2 Low Power Abstraction......................... 18 1.2 Thesis...................................... 21 1.3 Overview of Thesis............................... 23 1.3.1 Contributions.............................. 23 1.3.2 Outline................................. 26 2 High Level Modeling of Low Power Systems-on-Chip Design: Back- ground & State of Art 28 2.1 Background................................... 29 2.1.1 System-on-Chip Design Flow...................... 29 2.1.1.1 Algorithmic Level (AL)................... 29 2.1.1.2 Transaction Level of Modeling (TLM)........... 30 2.1.1.3 Cycle Accurate Level (CAL)................. 33 2.1.1.4 Register Transfer Level (RTL)................ 33 2.1.1.5 Gate Level (GL)....................... 33 2.1.1.6 Layout............................. 34 2.1.2 Model Driven Engineering (MDE): Basic Concepts......... 34 2.1.3 Transaction-Level of Modeling Key Concepts............. 36 2.1.3.1 TLM Common Concepts................... 36 2.1.3.2 TLM With SystemC..................... 38 2.1.4 The TLM 2.0 OSCI Standard..................... 41 2.1.4.1 The TLM 2.0 Modeling Features and Mechanisms..... 41 2.1.4.2 The TLM 2.0 Coding Styles................. 45 2.1.4.3 The TLM 2.0 Extension Mechanisms............ 47 2.1.5 Power reduction in Systems-on-Chip................. 49 ii/311 Ons MBAREK CONTENTS 2.1.5.1 Dynamic and Static Power.................. 50 2.1.5.2 Low Power Design Techniques................ 51 2.1.5.3 Power Management Levels.................. 57 2.1.6 Low Power Design Standards..................... 67 2.1.6.1 The Unified Power Format.................. 69 2.1.6.2 UPF Versus CPF: Similarities, Differences and Common Gaps.............................. 72 2.2 State of Art................................... 74 2.2.1 State-of-The-Art on High Level Power Modeling, Reduction and Analysis................................. 74 2.2.1.1 Functional/Algorithmic Level................ 75 2.2.1.2 Cycle-Accurate Level..................... 78 2.2.1.3 Transaction-Level....................... 79 2.2.1.4 Using Model Driven Engineering Approaches....... 83 2.2.2 State-of-The-Art on Low Power Design Standards Use....... 85 3 Overview of the USLPAF Framework 88 3.1 The Need for the USLPAF Framework.................... 88 3.1.1 Capturing Power Intent at Transaction-Level............. 88 3.1.1.1 What if the low power flow is extended to TLM?..... 88 3.1.1.2 What if a power domain-based reasoning is applied?... 93 3.1.2 Power-Aware Modeling Issues at Transaction-Level......... 99 3.1.2.1 The accuracy problem.................... 99 3.1.2.2 The power/latency trade-off problem............ 102 3.1.2.3 The synchronization problem................ 106 3.2 The USLPAF Structure and Features..................... 113 Ons MBAREK iii/311 CONTENTS 4 USLPAM: A Unified Methodology for System-Level Power-Aware Mod- eling and Verification 116 4.1 An Overview of the USLPAM Flow...................... 118 4.1.1 The Software Flow Analysis Stage................... 118 4.1.2 The Power Management Points (PMPs) Identification Stage.... 119 4.1.3 The Power Intent Specification Stage................. 122 4.1.3.1 The Main Abstracted UPF Concepts
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