IEEE Standard for Design and Verification of Low-Power, Energy- Aware Electronic Systems
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An Effective and Efficient Methodology for Soc Power Management Through UPF
An effective and efficient methodology for SoC power management through UPF By Renduchinthala Anusha Under the Supervision of Dr. Sujay Deb Mr. Akhilesh Chandra Mishra Mr. Rangarajan Ramanujam Indraprastha Institute of Information Technology Delhi June, 2016 ©Indraprastha Institute of Information Technology (IIITD), New Delhi 2016 An effective and efficient methodology for SoC power management through UPF By Renduchinthala Anusha Submitted in partial fulfilment of the requirements for the degree of Master of Technology in Electronics & Communication Engineering with specialization in VLSI & Embedded Systems To Indraprastha Institute of Information Technology Delhi June, 2016 Abstract With technology scaling and increase of chip complexity, power consumption of chip has been rising and its power architecture is getting complicated. Many power management techniques like power gating, multi-voltage, multi-threshold are applied to reduce power dissipation of devices. UPF is an IEEE 1801 standard format to describe the power architecture, also called as power intent, including power network connectivity and power reduction methods. It enables verification of power intent at early phases of the design cycle. The UPF developed should be consistent with the design at all stages of the design cycle and it should be updated according to the modifications made in the design. In conventional UPF flow through design cycle, few practical challenges are faced. Many bugs are not detected at earlier phases which might lead to the wrong implementation of power intent. In addition, parallel development of power intent for complex designs, limitations of UPF standard to describe few power intent components effectively and time- consuming conventional UPF flow hinder efficient UPF development and management. -
A Practical Guide to Low-Power Design
1 Foreword Energy consumption is a major, if not the major, concern today. The world is facing phenomenal growth of demand for energy from the Far East coupled with the unabated and substantial appetite for energy in the US and Europe. At the same time, population growth, economic expansion and urban development will create greater demand for more personal-mobility items, appliances, devices and services. Recognizing these worrisome trends, the U.S. Department Of Energy (DOE) has identified the reduction of energy consumption in commercial and residential buildings as a strategic goal. The Energy Information Administration at DOE attributed 33% of the primary energy consumption in the United States to building space heating and cooling—an amount equivalent to 2.1 billion barrels of oil. At these levels, even a modest aggregate increase in heating ventilation and air conditioning (HVAC) efficiency of 1% will provide direct economic benefits to people, enabling reduction and better management of electric utility grid demand, and reducing dependence on fossil fuels. In addition to the global relevance of efficient energy usage, there are the micro-economic and convenience concerns of families, where energy consumption is putting pressure on domestic budgets and where battery life of home mobile appliances is becoming a major selection factor for consumers. What can electronics makers do to help? Energy usage can be optimized at the chip, board, box, system, and network level. At each of these levels there are major gains that can be achieved. Low-power design has been a substantial research theme for years in IC design. Several important results have been used to limit energy consumption by fast components such as microprocessors and digital signal processors. -
An Electronic System Level Modeling Approach for the Design and Verification of Low-Power Systems-On Chip Ons Mbarek
An electronic system level modeling approach for the design and verification of low-power systems-on chip Ons Mbarek To cite this version: Ons Mbarek. An electronic system level modeling approach for the design and verification of low- power systems-on chip. Other [cs.OH]. Université Nice Sophia Antipolis, 2013. English. NNT : 2013NICE4023. tel-00837662v2 HAL Id: tel-00837662 https://tel.archives-ouvertes.fr/tel-00837662v2 Submitted on 18 Nov 2013 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. UNIVERSITE DE NICE-SOPHIA ANTIPOLIS ECOLE DOCTORALE STIC SCIENCES ET TECHNOLOGIES DE L’INFORMATION ET DE LA COMMUNICATION T H E S E pour l’obtention du grade de Docteur en Sciences de l’Université de Nice-Sophia Antipolis Mention Informatique présentée et soutenue publiquement par Ons MBAREK Une Approche de Modélisation au Niveau Système pour la Conception et la Vérification de Systèmes sur Puce à Faible Consommation An Electronic System Level Modeling Approach for the Design and Verification of Low-Power Systems-on-Chip Thèse dirigée par Michel AUGUIN Laboratoire LEAT, Université de Nice-Sophia Antipolis –CNRS, Sophia Antipolis soutenue le 29/05/2013 Jury : M. -
Low Power Digital Design Fundamental – an EDA Perspective
Confidential Low Power Digital Design Fundamental – An EDA Perspective Richard Chou ([email protected]) Director of SW Engineering Cadence Design System, Inc. March, 2018 About this presentation • Focus on electronic design automation(EDA), not circuit design • Focus on low-power digital IC design, NOT analog – ASIC designs based on standard-cell methodology, not FPGA • Focus on physical implementation, NOT device physics • Focus on industrial experience, NOT theoretical ideas • Prepare you to be an engineer, NOT a professor 2 © 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only. Agenda Introduction Low Power Physical Implementation Advanced Low Power Techniques Devices – Now & Future Summary 3 © 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only. Low Power Design Issues Impact Profitability Different drivers in different verticals Mobile/Hand-held Consumer/Digital Home Network/Data Center Battery Life Unit Cost (chip package) Power Efficiency Unit Cost (chip package) Unit Cost (fans etc.) Total Cost of Ownership Reliability Reliability Green Low power requirements drive different design decisions: • Product design architecture and integration decisions • IP make versus reuse versus buy decisions • Manufacturing process decisions 4 © 2017 Cadence Design Systems, Inc. All rights reserved. Device Current Components • Dynamic Switching Power – Due to charge/discharge of load cap Vdd 2 – Isw ~ CL Vdd Ile • Dynamic Short-circuit Power V in Vout – Due to direct current path from Vdd to I sc ground during output switching – I ~ input_slew / C Isw sc L CL Ile • Static Leakage Power – Due to subthreshold & gate leakage qVgs/kT -qVds/KT GND – Ile ~ K*e (1-e ) 2 Ptotal = CL.VDD .fclk .a01 + VDD . -
RTL Guidelines for Static Power Reduction
FACULDADE DE ENGENHARIA DA UNIVERSIDADE DO PORTO RTL Guidelines for Static Power Reduction Ciro de Moura Monteiro Mestrado Integrado em Engenharia Eletrotécnica e de Computadores Synopsys Supervisor: Hélder Silva FEUP Supervisor: José Carlos Alves July 27, 2016 c Ciro de Moura Monteiro, 2015 Resumo Nos dias que correm, com o crescimento de aparelhos portáteis, operados por baterias de capacidade limitada, é importante uma boa gestão de energia para garantir o maior período de operação possível. O consumo dinâmico de energia foi em tempos uma das maiores considerações a ter no design de circuitos para baixo consumo de energia, mas hoje em dia, algumas técnicas de redução de consumo dinâmico são aplicadas automaticamente pelas ferramentas. Cada vez se conseguem produzir circuitos integrados com mais transístores e até mesmo com transístores mais pequenos. No entanto, daí advém também o problema do aumento nas correntes de fuga. Uma abordagem possível para tentar reduzir o efeito da potência estática consumida pelas correntes de fuga destes circuitos é apelidada de power gating. Power gating consiste no uso de transístores como interruptores para ligar e desligar a alimen- tação de partes de um circuito integrado. Para tal, podem ser usados transístores de cabeçalho ou transístores de rodapé, cada um com as suas vantagens e desvantagens. i ii Abstract In today’s world, we are witnessing a growth in battery operated portable devices, that require smart power choices due to their limited battery life. Dynamic power consumption has been a major consideration when designing power aware devices, but some dynamic power savings are already automatically introduced by the designing tools.