DOCSLIB.ORG

RTL Guidelines for Static Power Reduction

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
RTL Guidelines for Static Power Reduction FACULDADE DE ENGENHARIA DA UNIVERSIDADE DO PORTO RTL Guidelines for Static Power Reduction Ciro de Moura Monteiro Mestrado Integrado em Engenharia Eletrotécnica e de Computadores Synopsys Supervisor: Hélder Silva FEUP Supervisor: José Carlos Alves July 27, 2016 c Ciro de Moura Monteiro, 2015 Resumo Nos dias que correm, com o crescimento de aparelhos portáteis, operados por baterias de capacidade limitada, é importante uma boa gestão de energia para garantir o maior período de operação possível. O consumo dinâmico de energia foi em tempos uma das maiores considerações a ter no design de circuitos para baixo consumo de energia, mas hoje em dia, algumas técnicas de redução de consumo dinâmico são aplicadas automaticamente pelas ferramentas. Cada vez se conseguem produzir circuitos integrados com mais transístores e até mesmo com transístores mais pequenos. No entanto, daí advém também o problema do aumento nas correntes de fuga. Uma abordagem possível para tentar reduzir o efeito da potência estática consumida pelas correntes de fuga destes circuitos é apelidada de power gating. Power gating consiste no uso de transístores como interruptores para ligar e desligar a alimen- tação de partes de um circuito integrado. Para tal, podem ser usados transístores de cabeçalho ou transístores de rodapé, cada um com as suas vantagens e desvantagens. i ii Abstract In today’s world, we are witnessing a growth in battery operated portable devices, that require smart power choices due to their limited battery life. Dynamic power consumption has been a major consideration when designing power aware devices, but some dynamic power savings are already automatically introduced by the designing tools. Current technology has evolved into having smaller transistors and that enables building chips with bigger transistor density. With this technology, new problems arise, as the existence of higher leakage currents. These may or may not be resolved by power reduction techniques, as not all of them are leakage oriented. One possible solution for this problem would be the power gating technique. Power Gating consists in using switching transistors to control the power supply of certain areas of the circuit. This power reduction technique allows the use of header or footer transistor, each one with its benefits and disadvantages. iii iv Agradecimentos Gostava de deixar um agradecimento... Em especial ao Hélder Silva e Athul Stripad por me acompanharem todas as semanas e aju- darem em algumas decisões importantes. Ao professor José Carlos Alves por me orientar neste trabalho, e me ajudar a tomar decisões. Ao Nelson Eira pela paciência para me explicar o funcionamento dos scripts utilizados pelo ambiente de implementação. À empresa Synopsys pela possibilidade que me foi dada em fazer este projecto de dissertação em ambiente empresarial. À minha família por me ajudar a crescer. À Susana Carvalho por me ajudar a escolher a minha especialização, da qual fiquei a gostar. À Inês Teixeira e Gabriel Ribeiro por me ajudarem com o meu inglês. A todos os meus outros amigos pela paciência para me aturarem. E por fim à FEUP e aos seus professores por me ajudarem na minha formação. Ciro de Moura Monteiro v vi “Laugh and the world laughs with you. Snore and you sleep alone” Anthony Burgess vii viii Contents 1 Introduction1 1.1 Context . .2 1.2 Motivation . .2 1.3 Objectives . .3 1.4 Power Gating . .3 1.5 EDA Team Organisation . .4 1.6 Structure . .5 2 Related Work7 2.1 Power Consumption . .7 2.1.1 Power and Energy . .8 2.1.2 Dynamic Power . 10 2.1.3 Static Power . 11 2.2 Power Gating . 14 2.2.1 Consideration . 15 2.2.2 Header vs Footer Switching . 15 2.2.3 Fine Grain vs Coarse Grain . 17 2.2.4 Power Intent Languages . 20 2.2.5 UPF . 20 3 Design Flow 33 3.1 Flow Without Power . 34 3.1.1 Synthesis . 35 3.2 UPF flow . 36 3.2.1 Voltage Aware Synthesis . 37 3.3 Power Analysis . 37 4 Implementation 41 4.1 Steps taken . 41 4.2 Obstacles . 43 4.3 Power Management Unit . 44 4.4 Final Result . 45 4.4.1 Power Architecture . 46 4.5 Verification . 46 5 Results 49 5.1 Power Reduction Outcome . 49 5.2 Guidelines . 51 ix x CONTENTS 5.3 Alternatives . 52 6 Conclusion 55 6.1 Future Work . 55 References 57 List of Figures 2.1 High power consumption . .9 2.2 Low power consumption . .9 2.3 Power consumption on a CMOS inverter. Source: [1]............... 10 2.4 Inverter . 10 2.5 Clock Gating Cell . 11 2.6 Summary of leakage currents of deep-submicrometer transistors. Source: [2].. 12 2.7 Sub-threshold leakage path in a CMOS inverter . 12 2.8 Header switching . 16 2.9 Footer switching . 16 2.10 Fine grain and cell . 17 2.11 Fine grain and cell with isolation clamp transistor . 18 2.12 Fine grain header switching and cell with isolation clamp transistor . 19 2.13 Companies involved in IEEE P1801 working group. Source [3]. 21 2.14 Example of power domains. 22 2.15 Isolation cell between power domains . 23 2.16 State Retention Isolation. Source: [4]....................... 24 2.17 Power domain with heterogeneous fan-out . 25 2.18 Retention register. Source: [4]........................... 26 2.19 Enable Level Shifter Example . 27 2.20 Header switch cell . 28 2.21 Isolation on input of heterogeneous fan-out . 29 2.22 Redundant isolation . 30 2.23 Output isolation . 30 3.1 UPF tool flow. Source: [5]............................. 33 3.2 Design flow for multi-voltage, power gated designs. Source: [4]......... 34 4.1 Basic representation of the module used. 42 4.2 Function State Machine. 45 4.3 Block representation of the power domains . 47 xi xii LIST OF FIGURES List of Tables 2.1 Main parameter for the seven-metal-layer 90-nm CMOS technology node. Source: [6].......................................... 13 2.2 Example of PST . 31 4.1 EDMA power state table . 43 4.2 Edma power state table . 46 5.1 Power during activity. 50 5.2 Power consumption related to current implementation, during activity. 50 5.3 Power consumption during full simulation. 51 5.4 Power consumption for a full simulation, write traffic. 51 5.5 Power consumption for a full simulation, read traffic. 51 5.6 Relative power consumption for a full write simulation. 51 xiii xiv LIST OF TABLES Symbols and Abbreviations CAD Computer-Aided Design CPF Common Power Format CTS Clock Tree Synthesis DC Design Compiler DFT Compiler Design-for-test Compiler DMA Direct Memory Access DRC Design Rule Check DVE Debugging and Visualisation Environment DVFS Dynamic Voltage and Frequency Scaling DVS Dynamic Voltage Scaling EDA Electronic Design Automation eDMA Embedded DMA FET Field Effect transistor GIDL Gate Induced Drain Leakage HDL Hardware Description Language IC Integrated Circuit IEEE Institute of Electrical and Electronics Engineers IoE Internet of Everything IoT Internet of Things IP Intellectual Property IP Intellectual Property IR drop Voltage drop due to energy losses in a resistive path MOS Metal–Oxide–Semiconductor MTCMOS Multi-Threshold CMOS MVSIM Multi-Voltage Simulation NLP Native Low Power NMOS N channel MOSFET PG Power and Ground PMU Power Management Unit PST Power State Table PVT Process, Voltage, Temperature QoR Quality of Results RCE Regression Control Environment RTL Register Transfer Level SAIF Switching Activity Interchange format SDC Synopsys Design Constraints SI International System of Units (Système international d’unités) SI2 Silicon Integration Initiative xv xvi SYMBOLS AND ABBREVIATIONS SoC System on a Chip SPEF Standard Parasitic Exchange Format TCL Tool Command Language UPF Unified Power Format UVM Universal Verification Methodology VC LP Verification Compiler Low Power VCD IEEE Standard 1364-1995, Value Change Dump VCS Verilog Compiled code Simulator VHDL VHSIC Hardware Description Language VHSIC Very High Speed Integrated Circuit VIP Verification IP/Verification Link Partner VLSI Very-Large-Scale Integration VPD VCD Plus VTB Verilog Test Bench WWW World Wide Web Concepts Clock Gating Technique to reduce clock activity Power Density Power consumed by area Power Gating Cutting power using a switch Power Island Island that kept ON inside power domain that is OFF Shadow Registers Register used to store data in sleep mode VDD Positive voltage rail VSS Negative voltage rail/Reference voltage xvii Chapter 1 Introduction Energy efficiency is a very important aspect of electronic circuit design nowadays. Just a few decades ago, designers used to focus only in having a working chip, and power consumption was not a primary design concern. The requirements for portability, mobility or battery dependency were very infrequent and the early CMOS technologies for digital electronics were sufficiently constrained in terms of power consumption. Then, as technology evolved, transistors size de- creased, making it possible to fit more of them in one die, and so, power consumption gained importance. Nonetheless, only dynamic power seemed to matter, due to the fact that for CMOS technology above 130nm leakage is negligible [4]. Nowadays, power is more important than ever, especially for battery operated and mobile devices. Power hungry chips tend to have high power density, which generates a lot of heat for a small dissipation area. This raises power dissipation issues, requires expensive cooling systems and may cause chip lifetime reduction. Due to environmental concerns, there is an interest on reducing power consumption from devices in an effort of reducing pollution and power wasted without activity. Systems may have most of their modules idling, consuming power without executing any operation. Chips should idle efficiently, to reduce the energy consumed on their operation. In the last years, portability and mobility have gained a still growing importance, and in that field, power consumption is of paramount importance. For example, there is a significant inconve- nience for users if portable equipments have to be constantly charged.
Load more

Recommended publications
  • Prostep Ivip CPO Statement Template
    CPO Statement of Mentor Graphics For Questa SIM Date: 17 June, 2015 CPO Statement of Mentor Graphics Following the prerequisites of ProSTEP iViP’s Code of PLM Openness (CPO) IT vendors shall determine and provide a list of their relevant products and the degree of fulfillment as a “CPO Statement” (cf. CPO Chapter 2.8). This CPO Statement refers to: Product Name Questa SIM Product Version Version 10 Contact Ellie Burns [email protected] This CPO Statement was created and published by Mentor Graphics in form of a self-assessment with regard to the CPO. Publication Date of this CPO Statement: 17 June 2015 Content 1 Executive Summary ______________________________________________________________________________ 2 2 Details of Self-Assessment ________________________________________________________________________ 3 2.1 CPO Chapter 2.1: Interoperability ________________________________________________________________ 3 2.2 CPO Chapter 2.2: Infrastructure _________________________________________________________________ 4 2.3 CPO Chapter 2.5: Standards ____________________________________________________________________ 4 2.4 CPO Chapter 2.6: Architecture __________________________________________________________________ 5 2.5 CPO Chapter 2.7: Partnership ___________________________________________________________________ 6 2.5.1 Data Generated by Users ___________________________________________________________________ 6 2.5.2 Partnership Models _______________________________________________________________________ 6 2.5.3 Support of
    [Show full text]
  • Power Reduction of a CMOS High-Speed Interface Using Power Gating
    FACULDADE DE ENGENHARIA DA UNIVERSIDADE DO PORTO Power reduction of a CMOS high-speed interface using power gating Luís Miguel Granja Gomes FOR JURY EVALUATION Mestrado Integrado em Engenharia Eletrotécnica e de Computadores FEUP Supervisor: Prof. João Canas Ferreira Synopsys Supervisor: Engineer Hélder Araújo June 25, 2013 c Luís Gomes, 2013 Resumo A indústria de circuitos VLSI sofreu uma série de revoluções na forma como os chips eletrónicos são projetados. Começou com o uso de linguagens de descrição de hardware e de avançadas ferramentas de trabalho, com o objetivo de diminuir os tempos de projeto e de produção, ao mesmo tempo que circuitos mais rápidos e pequenos eram construídos. A produção de dispos- itivos eletrónicos aumentou significativamente, de tal modo que, hoje, são usados biliões todos os dias. Atualmente, o maior desafio não é só projetar circuitos integrados mais pequenos e rápidos, mas manter esses acréscimos de velocidade e diminuição de tamanho, reduzindo simultaneamente o consumo de potência. Com a diminuição do tamanho da tecnologia e o uso de transístores com tensões de threshold cada vez mais reduzidas, o consumo de potência dinâmica e estática atingiu níveis insuportáveis. Chegou-se a um ponto em que, tanto económica como ambientalmente fa- lando, é obrigatório projetar para reduzir a potência. Synopsys, uma das maiores empresas desta indústria, apresentou um projeto com o objetivo de implementar Power Gating numa das suas interfaces de alta velocidade, como técnica mais eficaz na redução da potência estática. Esta dissertação apresenta as adaptações necessárias para a implementação de Power Gating us- ando ferramentas Synopsys, aplicando-as a um caso de estudo complexo.
    [Show full text]
  • Powerpoint Template
    Accellera Overview February 27, 2017 Lu Dai | Accellera Chairman Welcome Agenda . About Accellera . Current news . Technical activities . IEEE collaboration 2 © 2017 Accellera Systems Initiative, Inc. February 2017 Accellera Systems Initiative Our Mission To provide a platform in which the electronics industry can collaborate to innovate and deliver global standards that improve design and verification productivity for electronics products. 3 © 2017 Accellera Systems Initiative, Inc. February 2017 Broad Industry Support Corporate Members 4 © 2017 Accellera Systems Initiative, Inc. February 2017 Broad Industry Support Associate Members 5 © 2017 Accellera Systems Initiative, Inc. February 2017 Global Presence SystemC Evolution Day DVCon Europe DVCon U.S. SystemC Japan Design Automation Conference DVCon China Verification & ESL Forum DVCon India 6 © 2017 Accellera Systems Initiative, Inc. February 2017 Agenda . About Accellera . Current news . Technical activities . IEEE collaboration 7 © 2017 Accellera Systems Initiative, Inc. February 2017 Accellera News . Standards - IEEE Approves UVM 1.2 as IEEE 1800.2-2017 - Accellera relicenses SystemC reference implementation under Apache 2.0 . Outreach - First DVCon China to be held April 19, 2017 - Get IEEE free standards program extended 10 years/10 standards . Awards - Thomas Alsop receives 2017 Technical Excellence Award for his leadership of the UVM Working Group - Shrenik Mehta receives 2016 Accellera Leadership Award for his role as Accellera chair from 2005-2010 8 © 2017 Accellera Systems Initiative, Inc. February 2017 DVCon – Global Presence 29th Annual DVCon U.S. 4th Annual DVCon Europe www.dvcon-us.org 4th Annual DVCon India www.dvcon-europe.org 1st DVCon China www.dvcon-india.org www.dvcon-china.org 9 © 2017 Accellera Systems Initiative, Inc.
    [Show full text]
  • Powerplay Power Analysis 8 2013.11.04
    PowerPlay Power Analysis 8 2013.11.04 QII53013 Subscribe Send Feedback The PowerPlay Power Analysis tools allow you to estimate device power consumption accurately. As designs grow larger and process technology continues to shrink, power becomes an increasingly important design consideration. When designing a PCB, you must estimate the power consumption of a device accurately to develop an appropriate power budget, and to design the power supplies, voltage regulators, heat sink, and cooling system. The following figure shows the PowerPlay Power Analysis tools ability to estimate power consumption from early design concept through design implementation. Figure 8-1: PowerPlay Power Analysis From Design Concept Through Design Implementation PowerPlay Early Power Estimator Quartus II PowerPlay Power Analyzer Higher Placement and Simulation Routing Results Results Accuracy Quartus II Design Profile User Input Estimation Design Concept Design Implementation Lower PowerPlay Power Analysis Input For the majority of the designs, the PowerPlay Power Analyzer and the PowerPlay EPE spreadsheet have the following accuracy after the power models are final: • PowerPlay Power Analyzer—±20% from silicon, assuming that the PowerPlay Power Analyzer uses the Value Change Dump File (.vcd) generated toggle rates. • PowerPlay EPE spreadsheet— ±20% from the PowerPlay Power Analyzer results using .vcd generated toggle rates. 90% of EPE designs (using .vcd generated toggle rates exported from PPPA) are within ±30% silicon. The toggle rates are derived using the PowerPlay Power Analyzer with a .vcd file generated from a gate level simulation representative of the system operation. © 2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S.
    [Show full text]
  • IEEE-SA and How Standardization Can Enhance Your Business and Career Case Study in Electronic Design Automation
    IEEE-SA and How Standardization Can Enhance Your Business and Career Case Study in Electronic Design Automation Yatin Trivedi Member, Board of Governors, IEEE-SA Member, Standards Board, IEEE-SA Member, Education Activities Board, IEEE Director of Standards and Interoperability, Synopsys Vienna, March 2015 Contents Standards and EDA Impact of EDA standards Case Study: Successful Standards Standards as Innovation Platform Standards, Business and Career © 2015 IEEE Standards Association Vienna, March 2015 2 1 IEEE Technical Societies/Councils Top-class technical expert base . Aerospace & Electronic Systems . Instrumentation & Measurement . Antennas & Propagation . Lasers & Electro-Optics . Broadcast Technology . Magnetics . Circuits & Systems . Microwave Theory & Techniques . Communications . Nanotechnology Council . Components, Packaging, & Manufacturing . Nuclear & Plasma Sciences Technology . Oceanic Engineering Computer . Power Electronics Computational Intelligence . Power & Energy Consumer Electronics . Product Safety Engineering Control Systems . Professional Communication Council on Electronic Design Automation . Reliability Council on Superconductivity . Robotics & Automation Dielectrics & Electrical Insulation . Sensors Council Education . Signal Processing Electromagnetic Compatibility . Social Implications of Technology Electron Devices . Solid-State Circuits . Engineering in Medicine & Biology . Systems Council . Geosciences & Remote Sensing . Systems, Man, & Cybernetics . Industrial Electronics . Technology Management Council
    [Show full text]
  • Volume 10, Issue 1 — March 2014
    A PUBLICATION OF MENTOR GRAPHICS — VOLUME 10, ISSUE 1 — MARCH 2014 WHAT’S ON Whether It’s Fixing a Boiler, or Getting THE HORIZON? to Tapeout, It’s Productivity that Matters. By Tom Fitzpatrick, Editor and Verification Technologist The Little Things that Can Make Verification Easier Make verification more As I write this, we’re experiencing yet another winter storm here in New England. It started this productive by keeping your focus on verifying your design’s functionality...page 4 morning, and the timing was fortuitous since my wife had scheduled a maintenance visit by the oil company to fix a minor problem with the pipes before it really started snowing heavily. While the kids were sleeping in due to school being cancelled, the plumber worked in our basement to make The advantages of using the Unified Power Format (UPF) sure everything was working well. It turned out that he had to replace the water feeder valve on the standard with Questa See how Questa was able to model the behaviors boiler, which was preventing enough water from circulating in the heating pipes. Aside from being from their UPF specification...page 8 inefficient, this also caused the pipes to make a gurgling sound, which was the key symptom that led to the service call in the first place. As I see the snow piling Pre-silicon validation of IEEE 1149.1-2013 based Silicon up outside my window (6-8 inches and counting), it’s easy to Instruments Verify the functionality picture the disaster that this could have become had we not of the actual chip through what Intellitech calls “silicon instruments.”...page 13 identified the problem early and gotten it fixed.
    [Show full text]
  • Validation of Low Power Format Using Standard Cell Library Santosh K
    Validation of Low Power Format using Standard Cell Library Santosh K. Anchatgeri1, Padmanaban K.2, Sachin Bapat3 1- M.Sc. [Engg.] Student, 2-Assistant Professor, Department of Electronics and Electrical Engineering, M. S. Ramaiah School of Advanced Studies, Bangalore- 560 058 3- Staff Manager, VLSI System Design Centre, QUALCOMM, Bangalore. Abstract Increased system complexity has led to the substitution of the traditional bottom-up design flow by systematic hierarchical design flow. With decreasing channel lengths, few key problems such as timing closure, design sign-off, routing complexity, and power dissipation arise in the design flows. Specifically, minimizing power dissipation is critical in several high-end processors. This research aims at optimizing the design flow for power using the unified power format (UPF). The low power reduction techniques enforced in this research are multivoltage, multi-threshold voltage (Vth), and power gating with state retention. A top-down digital design flow for a flash based mixed signal microcontroller has been implemented with and without UPF synthesis flow for 45nm technology. The UPF synthesis is implemented with two voltages, 1.2V and 0.9V (Multi- VDD). Area, power and timing metrics are analyzed for the flows developed. Power savings of about 20 % are achieved in the design flow with 'multi-threshold' power technique compared to that of the design flow with no low power techniques employed. Similarly, 31 % power savings are achieved in the design flow with the UPF implemented when compared to that of the design flow with 'multi-threshold' power technique employed. Thus, a cumulative power savings of 51% has been achieved in a complete power efficient design flow (UPF) compared to that of the generic top-down standard flow with no power saving techniques employed.
    [Show full text]
  • IEEE Standard for Design and Verification of Low-Power, Energy- Aware Electronic Systems
    IEEE Standard for Design and Verification of Low-Power, Energy- Aware Electronic Systems IEEE Computer Society Sponsored by the Design Automation Standards Committee IEEE 3 Park Avenue IEEE Std 1801™-2015 New York, NY 10016-5997 (Revision of USA IEEE Std 1801-2013) Authorized licensed use limited to: Universidad Nacional Autonoma De Mexico (UNAM). Downloaded on January 16,2018 at 01:18:13 UTC from IEEE Xplore. Restrictions apply. IEEE Std 1801™-2015 (Revision of IEEE Std 1801-2013) IEEE Standard for Design and Verification of Low-Power, Energy- Aware Electronic Systems Sponsor Design Automation Standards Committee of the IEEE Computer Society Approved 5 December 2015 IEEE-SA Standards Board Authorized licensed use limited to: Universidad Nacional Autonoma De Mexico (UNAM). Downloaded on January 16,2018 at 01:18:13 UTC from IEEE Xplore. Restrictions apply. Grateful acknowledgment is made to the following for permission to use source material: Accellera Systems Initiative Unified Power Format (UPF) Standard, Version 1.0 Cadence Design Systems, Inc. Library Cell Modeling Guide Using CPF Hierarchical Power Intent Modeling Guide Using CPF Silicon Integration Initiative, Inc. Si2 Common Power Format Specification, Version 2.1 Abstract: A method is provided for specifying power intent for an electronic design, for use in verification of the structure and behavior of the design in the context of a given power- management architecture, and for driving implementation of that power-management architecture. The method supports incremental refinement of power-intent specifications required for IP-based design flows. Keywords: bottom-up implementation, buffers, energy-aware design, IEEE 1801™, interface specification, IP reuse, isolation, level-shifting, power domains, power intent, power modeling, power states, successive refinement, supply states, repeaters, retention, Unified Power Format (UPF) • The Institute of Electrical and Electronics Engineers, Inc.
    [Show full text]
  • An Effective and Efficient Methodology for Soc Power Management Through UPF
    An effective and efficient methodology for SoC power management through UPF By Renduchinthala Anusha Under the Supervision of Dr. Sujay Deb Mr. Akhilesh Chandra Mishra Mr. Rangarajan Ramanujam Indraprastha Institute of Information Technology Delhi June, 2016 ©Indraprastha Institute of Information Technology (IIITD), New Delhi 2016 An effective and efficient methodology for SoC power management through UPF By Renduchinthala Anusha Submitted in partial fulfilment of the requirements for the degree of Master of Technology in Electronics & Communication Engineering with specialization in VLSI & Embedded Systems To Indraprastha Institute of Information Technology Delhi June, 2016 Abstract With technology scaling and increase of chip complexity, power consumption of chip has been rising and its power architecture is getting complicated. Many power management techniques like power gating, multi-voltage, multi-threshold are applied to reduce power dissipation of devices. UPF is an IEEE 1801 standard format to describe the power architecture, also called as power intent, including power network connectivity and power reduction methods. It enables verification of power intent at early phases of the design cycle. The UPF developed should be consistent with the design at all stages of the design cycle and it should be updated according to the modifications made in the design. In conventional UPF flow through design cycle, few practical challenges are faced. Many bugs are not detected at earlier phases which might lead to the wrong implementation of power intent. In addition, parallel development of power intent for complex designs, limitations of UPF standard to describe few power intent components effectively and time- consuming conventional UPF flow hinder efficient UPF development and management.
    [Show full text]
  • Phd and Mphil Thesis Classes
    A novel approach to Reusable Time-economized STIL based pattern development by Rahul Malhotra Under the Supervision of Dr. Sujay Deb Fabio Carlucci Indraprastha Institute of Information Technology Delhi June, 2015 ©Indraprastha Institute of Information Technology (IIITD), New Delhi 2015 A novel approach to Reusable Time-economized STIL based pattern development by Rahul Malhotra Submitted in partial fulfillment of the requirements for the degree of Master of Technology in Electronics & Communication Engineering with specialization in VLSI & Embedded Systems to Indraprastha Institute of Information Technology Delhi June, 2015 Certificate This is to certify that the thesis titled A novel approach to Reusable Time- economized STIL based pattern development being submitted by Rahul Malho- tra to the Indraprastha Institute of Information Technology Delhi, for the award of the Master of Technology, is an original research work carried out by him under my super- vision. In my opinion, the thesis has reached the standards fulfilling the requirements of the regulations relating to the degree. The results contained in this thesis have not been submitted in part or full to any other university or institute for the award of any degree/diploma. June, 2015 Dr. Sujay Deb Department of Indraprastha Institute of Information Technology Delhi New Delhi 110 020 Abstract State of the art automotive micro-controllers (MCUs) implementing com- plex system-on-chip (SoC) architectures requires often additional functional patterns to achieve high degree of reliability. Functional pattern family in- cludes test patterns checking internal device functionality under nominal condition. The development of these patterns is required to augment struc- tural tests to achieve high test coverage.
    [Show full text]
  • AN 307: Intel® FPGA Design Flow for Xilinx* Users
    AN 307: Intel® FPGA Design Flow for Xilinx* Users Updated for Intel® Quartus® Prime Design Suite: 17.1 Subscribe AN-307 | 2020.08.24 Send Feedback Latest document on the web: PDF | HTML Contents Contents 1. Introduction to Intel® FPGA Design Flow for Xilinx* Users............................................. 4 2. Technology Comparison.................................................................................................. 5 2.1. Intel FPGAs ..........................................................................................................5 2.2. Xilinx FPGAs......................................................................................................... 6 2.3. Comparison Table.................................................................................................. 6 2.4. Intel FPGA Device Features..................................................................................... 7 3. FPGA Tools Comparison.................................................................................................. 9 3.1. Hardware and Software Tools for FPGA Design...........................................................9 3.2. FPGA Design Flow Using Command Line Scripting.....................................................10 3.2.1. Command-Line Executable Equivalents....................................................... 12 3.2.2. Programming and Configuration File Support in the Intel Quartus Prime Pro Edition Software.................................................................................17 3.3. FPGA Design
    [Show full text]
  • Non-Synthesizable Verilog Constructs
    Appendix I Synthesizable and Non-Synthesizable Verilog Constructs The list of synthesizable and non-synthesizable Verilog constructs is tabu-lated in the following Table Verilog Used for Synthesizable Non-Synthesizable Constructs construct Construct module The code inside the module and Yes No the endmodule consists of the declarations and functionality of the design Instantiation If the module is synthesizable Yes No then the instantiation is also synthesizable initial Used in the test benches No Yes always Procedural block with the reg Yes No type assignment on LHS side. The block is sensitive to the events assign Continuous assignment with Yes No wire data type for modeling the combinational logic primitives UDP’s are non-synthesizable Yes No whereas other Verilog primitives are synthesizable force and These are used in test benches No Yes release and non-synthesizable delays Used in the test benches and No Yes synthesis tool ignores the delays fork and join Used during simulation No Yes ports Used to indicate the direction, Yes No input, output and inout. The input is used at the top module parameter Used to make the design more Yes No generic time Not supported for the synthesis No Yes (continued) © Springer India 2016 399 V. Taraate, Digital Logic Design Using Verilog, DOI 10.1007/978-81-322-2791-5 400 Appendix I: Synthesizable and Non-Synthesizable Verilog Constructs (continued) real Not supported for synthesis No Yes functions and Both are synthesizable. Provided Yes No task that the task does not have the timing constructs loop The for loop is synthesizable and Yes No used for the multiple iterations.
    [Show full text]