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Systemverilog in Simulation SystemVerilog in Simulation Product Version 9.2 July 2010 Copyright 1995-2010 Cadence Design Systems, Inc. All rights reserved. Printed in the United States of America. Cadence Design Systems, Inc., 555 River Oaks Parkway, San Jose, CA 95134, USA Trademarks: Trademarks and service marks of Cadence Design Systems, Inc. (Cadence) contained in this document are attributed to Cadence with the appropriate symbol. For queries regarding Cadence’s trademarks, contact the corporate legal department at the address shown above or call 800.862.4522. Open SystemC, Open SystemC Initiative, OSCI, SystemC, and SystemC Initiative are trademarks or registered trademarks of Open SystemC Initiative, Inc. in the United States and other countries and are used with permission. All other trademarks are the property of their respective holders. Restricted Print Permission: This publication is protected by copyright and any unauthorized use of this publication may violate copyright, trademark, and other laws. Except as specified in this permission statement, this publication may not be copied, reproduced, modified, published, uploaded, posted, transmitted, or distributed in any way, without prior written permission from Cadence. This statement grants you permission to print one (1) hard copy of this publication subject to the following conditions: 1. The publication may be used solely for personal, informational, and noncommercial purposes; 2. The publication may not be modified in any way; 3. Any copy of the publication or portion thereof must include all original copyright, trademark, and other proprietary notices and this permission statement; and 4. Cadence reserves the right to revoke this authorization at any time, and any such use shall be discontinued immediately upon written notice from Cadence. Disclaimer: Information in this publication is subject to change without notice and does not represent a commitment on the part of Cadence. The information contained herein is the proprietary and confidential information of Cadence or its licensors, and is supplied subject to, and may be used only by Cadence’s customer in accordance with, a written agreement between Cadence and its customer. Except as may be explicitly set forth in such agreement, Cadence does not make, and expressly disclaims, any representations or warranties as to the completeness, accuracy or usefulness of the information contained in this document. Cadence does not warrant that use of such information will not infringe any third party rights, nor does Cadence assume any liability for damages or costs of any kind that may result from use of such information. Patents: Cadence products described in this document are protected by U.S. Patents 5,095,454, 5,418,931, 5,606,698, 6,487,704, 7,039,887, 7,055,116, 5,838,949, 6,263,301, 6,163,763, 6,301,578 Restricted Rights: Use, duplication, or disclosure by the Government is subject to restrictions as set forth in FAR52.227-14 and DFAR252.227-7013 et seq. or its successor. Licensed Copyrights: This software includes, in binary form, a software package called CUDD V.2.4.1 1995–2004, Regents of the University of Colorado. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. Neither the name of the University of Colorado nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. SystemVerilog in Simulation Contents 1 Introduction to SystemVerilog in Simulation . 7 Additional Documentation . 7 Additional Examples . 8 2 Preparing SystemVerilog Designs for Simulation. 9 Using Options for Compiling, Elaborating, and Simulating SystemVerilog . 9 Compilation Options (ncvlog and irun) . 9 Elaboration Options (ncelab and irun) . 9 Simulation Options (ncsim and irun) . 10 Using the Multi-Step Invocation Method . 15 Using the irun Utility . 16 Compiling a Design with Packages . 16 Compiling Packages with irun . 17 Compiling Packages with ncvlog . 20 Compiling Source Files into Compilation Units . 20 3 Accessing SystemVerilog Design Objects with SimVision . 23 Accessing SystemVerilog Objects in the Design Browser . 23 Selecting SystemVerilog Objects with the Design Browser and Design Search Sidebars 24 Viewing Compilation Units in the Design Browser . 25 Viewing Parameterized Classes and Class Specializations in the Design Browser . 26 Expanding and Collapsing SystemVerilog Aggregate Signals in the Design Browser 26 Sorting the Elements of a Queue, or Dynamic or Associative Array . 27 Viewing SystemVerilog Objects in the Schematic Tracer . 29 Accessing Classes in the SystemVerilog Class Browser . 29 Opening the Class Browser . 30 July 2010 3 Product Version 9.2 SystemVerilog in Simulation Using the Class Browser with the Design Browser . 32 Using the Class Browser with the Source Browser . 34 Viewing SystemVerilog Objects in the Waveform Window . 35 Adjusting the Minimum Height of an Array . 36 Viewing Associative Arrays in the Waveform Window . 37 Following SystemVerilog Signals in the Source Browser . 39 Preparing Your Design for the Constraints Debugger . 40 Opening the Constraints Debugger . 41 Constraint Debugger Overview . 42 Displaying Variable Values as Inputs to Constraints . 45 Displaying Constraints and Variables . 45 Enabling and Disabling Random Variables . 45 Enabling and Disabling Constraints . 45 Creating a Constraint . 46 Running the Current Randomize Call Again . 47 Handling Overconstraints . 47 Viewing Dynamic Objects with the SimVision Data Browser . 47 Setting Up the Data Browser . 47 Preparing Your Design for the Data Browser . 48 Opening Data Browser Windows . 49 Expanding and Collapsing a Dynamic Object . 51 Refreshing the Data Browser Contents . 51 Setting Breakpoints on Dynamic Objects . 52 Displaying Dynamic Objects for the Full Design . 52 Sending Dynamic Objects to the Design Browser . 52 Viewing Dynamic Objects in the Source Browser . 53 Sending Dynamic Objects to a New Data Browser Window . 53 Setting the Debug Scope in the Data Browser . 53 Copying a Dynamic Object . 53 4 Accessing SystemVerilog Design Objects with Tcl . 55 Debugging Compilation Units with Tcl . 55 Accessing Compilation Units with Tcl . 55 Examples . 56 July 2010 4 Product Version 9.2 SystemVerilog in Simulation Debugging Classes with Tcl . 58 Limitations on Tcl Commands for Parameterized Classes . 59 Tcl Syntax for Class Object Names . 59 Tcl Syntax for Parameterized Class Names . 60 Accessing Class Objects with Tcl . 61 Determining the Class Instance Handle from Tcl . 64 Listing Class Instance Handles with Tcl . 65 Determining the Value of a Class Member with Tcl . 66 Traversing the Class Hierarchy with Tcl . 68 Setting Object Breakpoints within Classes with Tcl . 74 Setting Line Breakpoints within Classes with Tcl . 76 Using the heap Command with Classes . 79 Generating Heap Usage Reports . 83 Debugging Constraints with Tcl . 86 Stopping on Calls to randomize() with Tcl . 86 Enabling Random Variables and Constraints with Tcl . 87 Adding a New Constraint from Tcl . 88 Executing randomize() Calls with Tcl . 88 Debugging Semaphores with Tcl . ..
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