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Xilinx Synthesis and Simulation Design Guide (UG626) Synthesis and Simulation Design Guide UG626 (v 14.4) December 18, 2012 This document applies to the following software versions: ISE Design Suite 14.4 through 14.7 Notice of Disclaimer The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of the Limited Warranties which can be viewed at http://www.xilinx.com/warranty.htm; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in Critical Applications: http://www.xilinx.com/warranty.htm#critapps. © Copyright 2002-2012 Xilinx Inc. All rights reserved. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. The PowerPC name and logo are registered trademarks of IBM Corp., and used under license. All other trademarks are the property of their respective owners. Revision History Date Version 03/01/2011 13.1 Enhancements, CR, and Version Updates. 07/06/2011 13.2 Enhancements, CR, and Version Updates. 10/19/2011 13.3 Enhancements, CR, and Version Updates. 01/19/2012 13.4 Enhancements, CR, and Version Updates. Made changes to the Simulating SecureIP with NC-Verilog topic. Made changes to the Test Bench Recommendations topic. 4/24/2012 14.1 Enhancements, CR, and Version Updates. 5/8/2012 14.1 Update to supported architectures. 12/18/2012 14.4 Updated link to design examples. Synthesis and Simulation Design Guide 2 www.xilinx.com UG626 (v 14.4) December 18, 2012 Table of Contents Revision History ....................................................................................................2 Chapter 1 Synthesis and Simulation Overview .........................................................7 Synthesis and Simulation Overview ....................................................................7 Synthesis and Simulation Design Examples........................................................7 Chapter 2 Hardware Description Language (HDL) ....................................................9 Advantages of Using a Hardware Description Language (HDL) to Design FPGA Devices ................................................................................................9 Designing FPGA Devices With Hardware Description Language (HDL) ............................................................................................................ 10 Chapter 3 FPGA Design Flow....................................................................................13 Design Flow Diagram.......................................................................................... 13 Design Entry Recommendations......................................................................... 13 Architecture Wizard ............................................................................................. 14 CORE Generator Software .................................................................................. 16 Functional Simulation Early in the Design Flow............................................... 17 Synthesizing and Optimizing ............................................................................. 18 Setting Constraints............................................................................................... 20 Evaluating Design Size and Performance .......................................................... 21 Evaluating Coding Style and System Features................................................... 23 Placing and Routing............................................................................................. 24 Timing Simulation............................................................................................... 24 Chapter 4 General Recommendations for Coding Practices .................................27 Designing With Hardware Description Language (HDL)................................. 27 Naming, Labeling, and General Coding Styles.................................................. 28 Specifying Constants ........................................................................................... 33 Using Generics and Parameters to Specify Dynamic Bus and Array Widths........................................................................................................... 34 TRANSLATE_OFF and TRANSLATE_ON......................................................... 35 Chapter 5 Coding for FPGA Device Flow .................................................................37 VHDL and Verilog Limitations ........................................................................... 37 Design Challenges in Using an Asynchronous First-In-First-Out (FIFO) Buffer ............................................................................................................ 37 Advantages and Disadvantages of Hierarchical Designs.................................. 38 Using Synthesis Tools with Hierarchical Designs ............................................. 39 Synthesis and Simulation Design Guide Send Feedback UG626 (v 14.4) December 18, 2012 www.xilinx.com 3 Choosing Data Type............................................................................................. 40 Using `timescale ................................................................................................... 43 Mixed Language Designs .................................................................................... 43 If Statements and Case Statements ..................................................................... 44 Sensitivity List in Process and Always Statements............................................ 47 Delays in Synthesis Code.................................................................................... 48 Registers in FPGA Design................................................................................... 48 Input Output Block (IOB) Registers ................................................................... 50 Latches in FPGA Design...................................................................................... 52 Implementing Shift Registers ............................................................................. 53 Describing Shift Registers................................................................................... 54 Control Signals..................................................................................................... 56 Initial State of the Registers and Latches ........................................................... 62 Initial State of the Shift Registers....................................................................... 63 Initial State of the RAMs..................................................................................... 63 Multiplexers ......................................................................................................... 64 Finite State Machine (FSM) Components........................................................... 66 Implementing Memory........................................................................................ 71 Block RAM Inference .......................................................................................... 72 Distributed RAM Inference ................................................................................ 80 Arithmetic Support .............................................................................................. 83 Synthesis Tool Naming Conventions ................................................................. 94 Instantiating FPGA Primitives............................................................................ 94 Instantiating CORE Generator Software Modules ............................................ 96 Attributes and Constraints .................................................................................. 96 Pipelining ........................................................................................................... 100 Retiming ............................................................................................................. 101 Verilog Language Support................................................................................
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