Synthesis and Simulation Design Guide UG626 (v 14.4) December 18, 2012 This document applies to the following software versions: ISE Design Suite 14.4 through 14.7 Notice of Disclaimer The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. 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Synthesis and Simulation Design Guide 2 www.xilinx.com UG626 (v 14.4) December 18, 2012 Table of Contents Revision History ....................................................................................................2 Chapter 1 Synthesis and Simulation Overview .........................................................7 Synthesis and Simulation Overview ....................................................................7 Synthesis and Simulation Design Examples........................................................7 Chapter 2 Hardware Description Language (HDL) ....................................................9 Advantages of Using a Hardware Description Language (HDL) to Design FPGA Devices ................................................................................................9 Designing FPGA Devices With Hardware Description Language (HDL) ............................................................................................................ 10 Chapter 3 FPGA Design Flow....................................................................................13 Design Flow Diagram.......................................................................................... 13 Design Entry Recommendations......................................................................... 13 Architecture Wizard ............................................................................................. 14 CORE Generator Software .................................................................................. 16 Functional Simulation Early in the Design Flow............................................... 17 Synthesizing and Optimizing ............................................................................. 18 Setting Constraints............................................................................................... 20 Evaluating Design Size and Performance .......................................................... 21 Evaluating Coding Style and System Features................................................... 23 Placing and Routing............................................................................................. 24 Timing Simulation............................................................................................... 24 Chapter 4 General Recommendations for Coding Practices .................................27 Designing With Hardware Description Language (HDL)................................. 27 Naming, Labeling, and General Coding Styles.................................................. 28 Specifying Constants ........................................................................................... 33 Using Generics and Parameters to Specify Dynamic Bus and Array Widths........................................................................................................... 34 TRANSLATE_OFF and TRANSLATE_ON......................................................... 35 Chapter 5 Coding for FPGA Device Flow .................................................................37 VHDL and Verilog Limitations ........................................................................... 37 Design Challenges in Using an Asynchronous First-In-First-Out (FIFO) Buffer ............................................................................................................ 37 Advantages and Disadvantages of Hierarchical Designs.................................. 38 Using Synthesis Tools with Hierarchical Designs ............................................. 39 Synthesis and Simulation Design Guide Send Feedback UG626 (v 14.4) December 18, 2012 www.xilinx.com 3 Choosing Data Type............................................................................................. 40 Using `timescale ................................................................................................... 43 Mixed Language Designs .................................................................................... 43 If Statements and Case Statements ..................................................................... 44 Sensitivity List in Process and Always Statements............................................ 47 Delays in Synthesis Code.................................................................................... 48 Registers in FPGA Design................................................................................... 48 Input Output Block (IOB) Registers ................................................................... 50 Latches in FPGA Design...................................................................................... 52 Implementing Shift Registers ............................................................................. 53 Describing Shift Registers................................................................................... 54 Control Signals..................................................................................................... 56 Initial State of the Registers and Latches ........................................................... 62 Initial State of the Shift Registers....................................................................... 63 Initial State of the RAMs..................................................................................... 63 Multiplexers ......................................................................................................... 64 Finite State Machine (FSM) Components........................................................... 66 Implementing Memory........................................................................................ 71 Block RAM Inference .......................................................................................... 72 Distributed RAM Inference ................................................................................ 80 Arithmetic Support .............................................................................................. 83 Synthesis Tool Naming Conventions ................................................................. 94 Instantiating FPGA Primitives............................................................................ 94 Instantiating CORE Generator Software Modules ............................................ 96 Attributes and Constraints .................................................................................. 96 Pipelining ........................................................................................................... 100 Retiming ............................................................................................................. 101 Verilog Language Support................................................................................