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Xilinx Synthesis and Verification Design Guide Synthesis and Simulation Design Guide 8.1i R R Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of the Design may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes. Xilinx does not assume any liability arising out of the application or use of the Design; nor does Xilinx convey any license under its patents, copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Design. Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design. THE DESIGN IS PROVIDED “AS IS” WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE, WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DESIGN, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOST DATA AND LOST PROFITS, ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN, EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTION WITH YOUR USE OF THE DESIGN, WHETHER IN CONTRACT OR TORT OR OTHERWISE, WILL IN NO EVENT EXCEED THE AMOUNT OF FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN. YOU ACKNOWLEDGE THAT THE FEES, IF ANY, REFLECT THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE DESIGN TO YOU WITHOUT THESE LIMITATIONS OF LIABILITY. The Design is not designed or intended for use in the development of on-line control equipment in hazardous environments requiring fail- safe controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air traffic control, life support, or weapons systems (“High-Risk Applications”). Xilinx specifically disclaims any express or implied warranties of fitness for such High-Risk Applications. You represent that use of the Design in such High-Risk Applications is fully at your risk. Copyright © 1995-2005 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. PowerPC is a trademark of IBM, Inc. All other trademarks are the property of their respective owners. Synthesis and Simulation Design Guide www.xilinx.com 8.1i R Preface About This Guide This guide provides a general overview of designing Field Programmable Gate Arrays (FPGA devices) with Hardware Description Languages (HDLs). It includes design hints for the novice HDL user, as well as for the experienced user who is designing FPGA devices for the first time. The design examples in this guide were: • created with Verilog and VHSIC Hardware Description Language (VHDL) • compiled with various synthesis tools • targeted for Spartan™-II, Spartan-IIE, Spartan-3, Spartan-3E, Virtex™, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X and Virtex-4 devices Xilinx® equally endorses both Verilog and VHDL. VHDL may be more difficult to learn than Verilog, and usually requires more explanation. This guide does not address certain topics that are important when creating HDL designs, such as the design environment; verification techniques; constraining in the synthesis tool; test considerations; and system verification. For more information, see your synthesis tool documentation and design methodology notes. Before using this guide, you should be familiar with the operations that are common to all Xilinx software tools. Guide Contents This guide contains the following chapters. • Chapter 1, “Introduction,” provides a general overview of designing Field Programmable Gate Arrays (FPGA devices) with HDLs. This chapter also includes installation requirements and instructions. • Chapter 2, “Understanding High-Density Design Flow,” provides synthesis and Xilinx implementation techniques to increase design performance and utilization. • Chapter 3, “General HDL Coding Styles,” includes HDL coding hints and design examples to help you develop an efficient coding style. • Chapter 4, “Coding Styles for FPGA Devices,” includes coding techniques to help you use the latest Xilinx FPGA devices. • Chapter 5 “Using SmartModels,” describes the special considerations encountered when simulating designs for Virtex-II Pro and Virtex-II Pro X FPGA devices. • Chapter 6, “Simulating Your Design,” describes simulation methods for verifying the function and timing of your designs. • Chapter 7, “Equivalency Checking.” Information on equivalency checking is no longer included in the Synthesis and Simulation Design Guide. For information on Synthesis and Simulation Design Guide www.xilinx.com 3 8.1i Preface: About This Guide R running formal verification with Xilinx devices, see http://www.xilinx.com/xlnx/xil_tt_product.jsp?BV_UseBVCookie=yes&sProduct=f ormal Additional Resources To find additional documentation, see the Xilinx website at: http://www.xilinx.com/literature. To search the Answer Database of silicon, software, and IP questions and answers, or to create a technical support WebCase, see the Xilinx website at: http://www.xilinx.com/support. Conventions This document uses the following conventions. An example illustrates each convention. Typographical The following typographical conventions are used in this document: Convention Meaning or Use Example Messages, prompts, and Courier font program files that the system speed grade: - 100 displays Courier bold Literal commands that you ngdbuild design_name enter in a syntactical statement Commands that you select File → Open Helvetica bold from a menu Keyboard shortcuts Ctrl+C Variables in a syntax statement for which you must ngdbuild design_name supply values See the Development System Italic font References to other manuals Reference Guide for more information. If a wire is drawn so that it Emphasis in text overlaps the pin of a symbol, the two nets are not connected. An optional entry or parameter. However, in bus ngdbuild [ option_name] Square brackets [ ] specifications, such as design_name bus[7:0], they are required. A list of items from which you Braces { } lowpwr ={on|off} must choose one or more 4 www.xilinx.com Synthesis and Simulation Design Guide 8.1i R Conventions Convention Meaning or Use Example Separates items in a list of Vertical bar | lowpwr ={on|off} choices IOB #1: Name = QOUT’ Vertical ellipsis IOB #2: Name = CLKIN’ . Repetitive material that has . been omitted . Repetitive material that has allow block block_name Horizontal ellipsis . been omitted loc1 loc2 ... locn; Online Document The following conventions are used in this document: Convention Meaning or Use Example Cross-reference link to a See the section “Additional location in the current file or Resources” for details. Blue text in another file in the current Refer to “Title Formats” in document Chapter 1 for details.. Cross-reference link to a See Figure 2-5 in the Virtex-II Red text location in another document Platform FPGA User Guide. Go to http://www.xilinx.com Blue, underlined text Hyperlink to a website (URL) for the latest speed files. Synthesis and Simulation Design Guide www.xilinx.com 5 8.1i Preface: About This Guide R 6 www.xilinx.com Synthesis and Simulation Design Guide 8.1i Table of Contents Preface: About This Guide Guide Contents . 3 Additional Resources . 4 Conventions . 4 Typographical. 4 Online Document . 5 Chapter 1: Introduction Device Support . 17 Hardware Description Languages . 17 Advantages of Using HDLs to Design FPGA Devices . 18 Top-Down Approach for Large Projects . 18 Functional Simulation Early in the Design Flow. 18 Synthesis of HDL Code to Gates . 18 Early Testing of Various Design Implementations . 18 Reuse of RTL Code . 19 Designing FPGA Devices with HDLs. 19 Designing FPGA Devices with Verilog. 19 Designing FPGA Devices with VHDL . 19 Designing FPGA Devices with Synthesis Tools . 20 Using FPGA System Features . 20 Designing Hierarchy . 20 Specifying Speed Requirements . 20 Chapter 2: Understanding High-Density Design Flow Design Flow . 24 Entering Your Design and Selecting Hierarchy . 25 Design Entry Recommendations . 25 Use RTL Code . 25 Select the Correct Design Hierarchy . 25 Architecture Wizard . 25 Opening Architecture Wizard. 25 Architecture Wizard Components . 26 CORE Generator. 27 CORE Generator Templates . 27 CORE Generator Files. 27 Functional Simulation. 28 Simulation Recommendations . 28 Perform Separate Simulations. 28 Create a Test Bench. 28 ModelSim Simulators . 29 Synthesizing and Optimizing . 29 Creating an Initialization File . 29 Creating a Compile Run Script . 29 Synthesis and Simulation Design Guide www.xilinx.com 7 8.1i R DCFPGA . 29 LeonardoSpectrum . 31 Precision RTL Synthesis . 32 Synplify. 32 XST . ..
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