DOCSLIB.ORG

Stratix II Vs. Virtex-4 Power Comparison & Estimation Accuracy

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Stratix II Vs. Virtex-4 Power Comparison & Estimation Accuracy White Paper Stratix II vs. Virtex-4 Power Comparison & Estimation Accuracy Introduction This document compares power consumption and power estimation accuracy for Altera® Stratix® II FPGAs and Xilinx Virtex-4 FPGAs. The comparison addresses all components of power: core dynamic power, core static power, and I/O power. This document uses bench-measured results to compare actual dynamic power consumption. To compare power estimation accuracy, the analysis uses the vendor-recommended power estimation software tools. The summary of these comparisons are: Altera’s Quartus® II PowerPlay power analyzer tool is accurate (to within 20%), while Xilinx’s tools are significantly less accurate. Stratix II devices exhibit lower dynamic power than Virtex-4 devices, resulting in total device power that is equal. Having an accurate FPGA power estimate is important to avoid surprises late in the design and prototyping phase. Inaccurate estimates can be costly and cause design issues, including: board re-layout, changes to power-management circuitry, changes cooling solution, unreliable FPGA operation, undue heating of other components, and changes to the FPGA design. Furthermore, without accurate power estimates, it is impossible for the designer and FPGA CAD software to optimize design power. This white paper contains the following sections: Components of total device power Power estimation and measurement methodology Core dynamic power comparison – power tool accuracy and bench measurements Core Static power comparison I/O power comparison Total device power summary For competitive comparisons on performance and density between Stratix II and Virtex-4 devices, refer to the following white papers from the Altera web site: Stratix II vs. Virtex-4 FPGA Performance Comparison White Paper Stratix II vs. Virtex-4 Density Comparison White Paper Components of Total Device Power Total device power is the sum of three components: core dynamic power, core static power, and I/O power. Core dynamic power is the power dissipated by the operation of the FPGA core fabric. This power increases linearly with operating frequency. Core static power is the power dissipated that is independent of frequency (such as leakage current across a transistor) and can be determined by stopping all clocks (an operating frequency of 0 MHz). The final power component, I/O power, is the power dissipated in the FPGA I/O cells to communicate with other chips. Figure 1 shows the breakdown of power into these three components for the average Stratix II design. This data was obtained by estimating the power consumption of 99 complete designs with the Quartus II software version 5.0 SP1 PowerPlay power analyzer. August 2005, ver. 1.0 1 WP-S20805-01 Stratix II vs. Virtex-4 Power Comparison & Estimation Accuracy White Paper Altera Corporation 11.2% 21.7% Core Dynamic Core Static I/O 67.1% Figure 1. Average Breakdown of Total Power in Stratix II Designs (Typical Conditions, 12.5% Toggle Rate) The data in Figure 1 uses the 3.3-V LVTL I/O standard with 10-pF output loading. In addition, Figure 1 reflects static power at typical conditions. At worst-case conditions, the proportion of static power will increase. Figure 1 shows that static power is on average 21.7% of total device power which is relatively significant compared to previous generation FPGAs. However, core dynamic power remains the most important portion of total device power. Power Estimation & Measurement Methodology FPGA vendors provide power estimation tools to help users design the board power supply and the system cooling solution. These power estimation tools also help designers optimize device power consumption. Altera tools generate power estimates based on parameters such as design resource utilization, routing utilization, clock frequencies, device, I/O loading, temperature, and silicon process. Each of these parameters can affect static power, dynamic power, or both. Stratix II static power is primarily affected by device junction temperature, voltage, and silicon process variation. Altera supplies typical and worst-case power specifications. These specifications are based on silicon characterization performed across a wide array of devices across various extremes of silicon process variation. All devices shipped meet the worst-case specification, and this specification should be used in the design of system thermal solutions. Dynamic power is primarily affected by design resource utilization, design implementation, routing utilization, and circuit switching activity. Silicon process and temperature variation have very little effect on dynamic power. A power model of each element within the Stratix II FPGA enables accurate power estimation. If a designer knows the design information (such as utilization, frequency, or I/O loading), then an estimation of power can be made. Either the designer can make an educated guess of the design information or compile the design to gain more accurate design information. 2 Altera Corporation Stratix II vs. Virtex-4 Power Comparison & Estimation Accuracy White Paper Altera’s Power Estimation Tools There are three primary methods of assessing the power consumption of a Stratix II design, which are listed as follows, from least accurate to most accurate: Stratix II PowerPlay Early Power Estimator Spreadsheet. This spreadsheet generates design power estimates based on user-entered resource utilization, toggle rates, and environmental conditions. The early power estimator is used prior to design implementation and as a result, accuracy of the power estimation data is dependant on the accuracy of the design information entered by the user. The power model used in this tool is based on the model in the Quartus II PowerPlay power analyzer tool, but assumes typical logic implementation and routing utilization. The analogous Xilinx tool is the Web Power Tool (WPT). The early power estimator accuracy is generally within ±20% of the Quartus II PowerPlay power analyzer estimates, assuming perfect toggle-rate entry. Quartus II PowerPlay Power Analyzer. The PowerPlay power analyzer is integrated in the Quartus II software and generates design power estimates based on Quartus II software place-and-route information and toggle rate data from a variety of sources. The power analyzer performs power analysis based on the exact resources, logic functions, and routing paths used in the target design. It can derive toggle rates from user entry, statistical circuit analysis techniques, RTL simulation, and gate-level simulation. The power analyzer can optionally filter out pulses, or glitches, from simulation data when those glitches are too fast to toggle the logic and routing of an actual FPGA. The highest-quality estimates are found when using the Power Analyzer with glitch-filtered gate-level simulations. Unless noted, this document shows results comparing Quartus II software version 5.0 SP1 PowerPlay power analyzer estimations to Stratix II bench results, demonstrating estimation error within ±20%, with a bias toward over estimation. Results for the analogous Xilinx tool, ISE XPower 7.1 SP2, are shown alongside Virtex-4 bench results, with estimation error results that range from a 8× underestimation to 3× overestimation. Bench Measurements. The best estimate of a design’s dynamic power is obtained by measuring a design in-system. This is done by measuring the amount of current the FPGA is drawing on each power rail at the required frequency. Static power results from single-unit measurements are not meaningful due to significant unit-to-unit static power variation. The vendor-provided worst-case specification should be used instead (as explained in the static power consumption section of this document). Use the following steps to obtain a worst-case estimate for total device power in-system: 1. Measure the power drawn from each power supply voltage from a device configured with the correct I/O standards and phase-locked loop (PLL)/digital clock manager (DCM) usage, with a 0-MHz clock. This provides the baseline static power consumption for the FPGA. Punconfigured _ static,measured = ∑ I i ⋅Vi (1) i∈All sup plies 2. Program the FPGA with the design-under-test and measure the power drawn from all power rails with each clock running at its target frequency. This provides a measurement of total power (dynamic and static power). 3. Compute the worst-case total power of a device running this design by adding in the difference between the static power of this device measured in #1 and the vendor-supplied worst-case 3 Stratix II vs. Virtex-4 Power Comparison & Estimation Accuracy White Paper Altera Corporation specification for static power (using the correct I/O standards and phase-locked loop (PLL)/digital clock manager (DCM) usage). PTotal ,worst−case = POperation,measured + (Pstatic,worst−case−spec − Punconfigured _ static,measured ) (2) Altera designed and developed a power test board to compare Stratix II and Virtex-4 power consumption. This board, shown in Figure 2, has two electrically isolated halves, one with a Stratix II EP2S60 device and the other with a Virtex-4 LX60 device. The two board halves are identically designed except where device requirements require small differences. The FPGA power rails are isolated and individually regulated, allowing for precise measurements of supply current per power rail. I/O traces for each device are matched in length to allow for accurate I/O power comparisons. Figure 2. EP2S60 & LX60 Board Used for Comparing Dynamic & I/O Power For more information on Altera’s power estimation tools, see the Power Estimation & Analysis section in the Quartus II Development Software Handbook. Dynamic Power Comparison: Stratix II vs. Virtex-4 FPGAs To compare the dynamic power of a Stratix II device to a Virtex-4 device, Altera compared measured and estimated results across a variety of designs selected to provide coverage of many types of FPGA functions. Circuits were coded in an architecture-independent hardware description language (HDL) wherever possible. In some cases, such as RAM designs, the respective MegaWizard® Plug-In Manager or Core Generator tools were used to generate designs with matching parameters.
Load more

Recommended publications
  • Configurable RISC-V Softcore Processor for FPGA Implementation
    1 Configurable RISC-V softcore processor for FPGA implementation Joao˜ Filipe Monteiro Rodrigues, Instituto Superior Tecnico,´ Universidade de Lisboa Abstract—Over the past years, the processor market has and development of several programming tools. The RISC-V been dominated by proprietary architectures that implement Foundation controls the RISC-V evolution, and its members instruction sets that require licensing and the payment of fees to are responsible for promoting the adoption of RISC-V and receive permission so they can be used. ARM is an example of one of those companies that sell its microarchitectures to participating in the development of the new ISA. In the list of the manufactures so they can implement them into their own members are big companies like Google, NVIDIA, Western products, and it does not allow the use of its instruction set Digital, Samsung, or Qualcomm. (ISA) in other implementations without licensing. The RISC-V The main goal of this work is the development of a RISC- instruction set appeared proposing the hardware and software V softcore processor to be implemented in an FPGA, using development without costs, through the creation of an open- source ISA. This way, it is possible that any project that im- a non-RISC-V core as the base of this architecture. The plements the RISC-V ISA can be made available open-source or proposed solution is focused on solving the problems and even implemented in commercial products. However, the RISC- limitations identified in the other RISC-V cores that were V solutions that have been developed do not present the needed analyzed in this thesis, especially in terms of the adaptability requirements so they can be included in projects, especially the and flexibility, allowing future modifications according to the research projects, because they offer poor documentation, and their performances are not suitable.
    [Show full text]
  • Xilinx Synthesis and Verification Design Guide
    Synthesis and Simulation Design Guide 8.1i R R Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of the Design may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes. Xilinx does not assume any liability arising out of the application or use of the Design; nor does Xilinx convey any license under its patents, copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Design. Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design. THE DESIGN IS PROVIDED “AS IS” WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE, WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES.
    [Show full text]
  • AN 307: Altera Design Flow for Xilinx Users Supersedes Information Published in Previous Versions
    Altera Design Flow for Xilinx Users June 2005, ver. 5.0 Application Note 307 Introduction Designing for Altera® Programmable Logic Devices (PLDs) is very similar, both in concept and in practice, to designing for Xilinx PLDs. In most cases, you can simply import your register transfer level (RTL) into Altera’s Quartus® II software and begin compiling your design to the target device. This document will demonstrate the similar flows between the Altera Quartus II software and the Xilinx ISE software. For designs, which the designer has included Xilinx CORE generator modules or instantiated primitives, the bulk of this document guides the designer in design conversion considerations. Who Should Read This Document The first and third sections of this application note are designed for engineers who are familiar with the Xilinx ISE software and are using Altera’s Quartus II software. This first section describes the possible design flows available with the Altera Quartus II software and demonstrates how similar they are to the Xilinx ISE flows. The third section shows you how to convert your ISE constraints into Quartus II constraints. f For more information on setting up your design in the Quartus II software, refer to the Altera Quick Start Guide For Quartus II Software. The second section of this application note is designed for engineers whose design code contains Xilinx CORE generator modules or instantiated primitives. The second section provides comprehensive information on how to migrate a design targeted at a Xilinx device to one that is compatible with an Altera device. If your design contains pure behavioral coding, you can skip the second section entirely.
    [Show full text]
  • Implementation, Verification and Validation of an Openrisc-1200
    (IJACSA) International Journal of Advanced Computer Science and Applications, Vol. 10, No. 1, 2019 Implementation, Verification and Validation of an OpenRISC-1200 Soft-core Processor on FPGA Abdul Rafay Khatri Department of Electronic Engineering, QUEST, NawabShah, Pakistan Abstract—An embedded system is a dedicated computer system in which hardware and software are combined to per- form some specific tasks. Recent advancements in the Field Programmable Gate Array (FPGA) technology make it possible to implement the complete embedded system on a single FPGA chip. The fundamental component of an embedded system is a microprocessor. Soft-core processors are written in hardware description languages and functionally equivalent to an ordinary microprocessor. These soft-core processors are synthesized and implemented on the FPGA devices. In this paper, the OpenRISC 1200 processor is used, which is a 32-bit soft-core processor and Fig. 1. General block diagram of embedded systems. written in the Verilog HDL. Xilinx ISE tools perform synthesis, design implementation and configure/program the FPGA. For verification and debugging purpose, a software toolchain from (RISC) processor. This processor consists of all necessary GNU is configured and installed. The software is written in C components which are available in any other microproces- and Assembly languages. The communication between the host computer and FPGA board is carried out through the serial RS- sor. These components are connected through a bus called 232 port. Wishbone bus. In this work, the OR1200 processor is used to implement the system on a chip technology on a Virtex-5 Keywords—FPGA Design; HDLs; Hw-Sw Co-design; Open- FPGA board from Xilinx.
    [Show full text]
  • RTL Design and IP Generation Tutorial
    RTL Design and IP Generation Tutorial PlanAhead Design Tool UG675(v14.5) April 10, 2013 This tutorial document was last validated using the following software version: ISE Design Suite 14.5 If using a later software version, there may be minor differences between the images and results shown in this document with what you will see in the Design Suite.Suite. Notice of Disclaimer The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent.
    [Show full text]
  • FPGA Architecture: Survey and Challenges Full Text Available At
    Full text available at: http://dx.doi.org/10.1561/1000000005 FPGA Architecture: Survey and Challenges Full text available at: http://dx.doi.org/10.1561/1000000005 FPGA Architecture: Survey and Challenges Ian Kuon University of Toronto Toronto, ON Canada [email protected] Russell Tessier University of Massachusetts Amherst, MA USA [email protected] Jonathan Rose University of Toronto Toronto, ON Canada [email protected] Boston – Delft Full text available at: http://dx.doi.org/10.1561/1000000005 Foundations and Trends R in Electronic Design Automation Published, sold and distributed by: now Publishers Inc. PO Box 1024 Hanover, MA 02339 USA Tel. +1-781-985-4510 www.nowpublishers.com [email protected] Outside North America: now Publishers Inc. PO Box 179 2600 AD Delft The Netherlands Tel. +31-6-51115274 The preferred citation for this publication is I. Kuon, R. Tessier and J. Rose, FPGA Architecture: Survey and Challenges, Foundations and Trends R in Elec- tronic Design Automation, vol 2, no 2, pp 135–253, 2007 ISBN: 978-1-60198-126-4 c 2008 I. Kuon, R. Tessier and J. Rose All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, mechanical, photocopying, recording or otherwise, without prior written permission of the publishers. Photocopying. In the USA: This journal is registered at the Copyright Clearance Cen- ter, Inc., 222 Rosewood Drive, Danvers, MA 01923. Authorization to photocopy items for internal or personal use, or the internal or personal use of specific clients, is granted by now Publishers Inc for users registered with the Copyright Clearance Center (CCC).
    [Show full text]
  • Small Soft Core up Inventory ©2019 James Brakefield Opencore and Other Soft Core Processors Reverse-U16 A.T
    tool pip _uP_all_soft opencores or style / data inst repor com LUTs blk F tool MIPS clks/ KIPS ven src #src fltg max max byte adr # start last secondary web status author FPGA top file chai e note worthy comments doc SOC date LUT? # inst # folder prmary link clone size size ter ents ALUT mults ram max ver /inst inst /LUT dor code files pt Hav'd dat inst adrs mod reg year revis link n len Small soft core uP Inventory ©2019 James Brakefield Opencore and other soft core processors reverse-u16 https://github.com/programmerby/ReVerSE-U16stable A.T. Z80 8 8 cylcone-4 James Brakefield11224 4 60 ## 14.7 0.33 4.0 X Y vhdl 29 zxpoly Y yes N N 64K 64K Y 2015 SOC project using T80, HDMI generatorretro Z80 based on T80 by Daniel Wallner copyblaze https://opencores.org/project,copyblazestable Abdallah ElIbrahimi picoBlaze 8 18 kintex-7-3 James Brakefieldmissing block622 ROM6 217 ## 14.7 0.33 2.0 57.5 IX vhdl 16 cp_copyblazeY asm N 256 2K Y 2011 2016 wishbone extras sap https://opencores.org/project,sapstable Ahmed Shahein accum 8 8 kintex-7-3 James Brakefieldno LUT RAM48 or block6 RAM 200 ## 14.7 0.10 4.0 104.2 X vhdl 15 mp_struct N 16 16 Y 5 2012 2017 https://shirishkoirala.blogspot.com/2017/01/sap-1simple-as-possible-1-computer.htmlSimple as Possible Computer from Malvinohttps://www.youtube.com/watch?v=prpyEFxZCMw & Brown "Digital computer electronics" blue https://opencores.org/project,bluestable Al Williams accum 16 16 spartan-3-5 James Brakefieldremoved clock1025 constraint4 63 ## 14.7 0.67 1.0 41.1 X verilog 16 topbox web N 4K 4K N 16 2 2009
    [Show full text]
  • Introduction to Verilog
    Introduction to Verilog Some material adapted from EE108B Introduction to Verilog presentation In lab, we will be using a hardware description language (HDL) called Verilog. Writing in Verilog lets us focus on the high‐level behavior of the hardware we are trying to describe rather than the low‐level behavior of every single logic gate. Design Flow Verilog Source Synthesis and Implementation Tools (Xilinx ISE) Gate‐level Netlist Place and Route Tools (Xilinx ISE) Verilog Source with Testbench FPGA Bitstream ModelSim Compiler Bitstream Download Tool (ChipScope) Simulation FPGA ModelSim SE Xilinx XC2VP30 Figure 1. Simulation flow (left) and synthesis flow (right) The design of a digital circuit using Verilog primarily follows two design flows. First, we feed our Verilog source files into a simulation tool, as shown by the diagram on the left. The simulation tool simulates in software the actual behavior of the hardware circuit for certain input conditions, which we describe in a testbench. Because compiling our Verilog for the simulation tool is relatively fast, we primarily use simulation tools when we are testing our design. When we are confident that design is correct, we then use a hardware synthesis tool to turn our high‐level Verilog code to a low‐level gate netlist. A mapping tool then maps the netlist to the applicable resources on the device we are targeting—in our case, a field programmable grid array (FPGA). Finally, we download a bitstream describing the way the FPGA should be reconfigured onto the FPGA, resulting in an actual digital circuit. Philosophy Verilog has a C‐like syntax.
    [Show full text]
  • Xilinx Vivado – „EDK” Embedded Development) 4
    EFOP-3.4.3-16-2016-00009 A fels őfokú oktatás min őségének és hozzáférhet őségének együttes javítása a Pannon Egyetemen EMBEDDED SYSTEM DEVELOPMENT (MISAM154R) Created by Zsolt Voroshazi, PhD [email protected] Updated: 02 March. 2020. 2. FPGAS & PLATFORMS Embedded Systems Topics covered 1. Introduction – Embedded Systems 2. FPGAs, Digilent ZyBo development platform 3. Embedded System - Firmware development environment (Xilinx Vivado – „EDK” Embedded Development) 4. Embedded System - Software development environment (Xilinx VITIS – „SDK”) 5. Embedded Base System Build (and Board Bring-Up) 6. Adding Peripherals (from IP database) to BSB 7. Adding Custom (=own) Peripherals to BSB 8. Design and Development of Complex IP cores and applications (e.g. camera/video/ audio controllers) 3 Further references • XILINX official website: http://www.xilinx.com • EE Journal – Electronic Engineering: http://www.eejournal.com/design/embedded • EE Times - News: http://www.eetimes.com/design/embedded 4 PLD & FPGA CIRCUITS General description PAST … • Before ’80s, designing logic networks for digital circuits, modern development tools were not yet available as today. • The design of high complexity (multi I/O) logical combination and sequential networks was therefore slow and cumbersome, often coupled with paper- based design, multiple manual checks, and calculations. • We could not talk about advanced design and simulation tools (CAD) either, so there was a high probability of error in a prototype design. 6 … AND PRESENT • Today, all of these are available in an automated way (EDA - Electronic Design Automation), which, in addition to the use of Programmable Logic Devices (PLD), is relatively fast for both Printed Circuit Boards (PCB) and Application-specific Integrated Circuits and Processors (ASIC / ASSP).
    [Show full text]
  • Starting Active-HDL As the Default Simulator in Xilinx
    7/29/13 Support - Resources - Documentation - Application Notes - Aldec 日本語 Sign In | Register Search aldec.com SOLUTIONS PRODUCTS EVENTS COMPANY SUPPORT DOWNLOADS Home Support Resources Documentation Application Notes RESOURCES Starting Active-HDL as the Default Simulator in Xilinx ISE « Prev | Next » Documentation Application Notes Introduction FAQ This document describes how to start Active-HDL simulator from Xilinx ISE Project Navigator to run behavioral and timing simulations. This Manuals application note has been verified on Active-HDL 9.1 and Xilinx ISE 13.4. This interface allows users to run mixed VHDL, Verilog and White Papers System Verilog (design ) simulation using Active-HDL as a default simulator. Tutorials Installing Xilinx libraries in Active-HDL Multimedia Demonstration In order to run the simulation successfully, depending on the design both VHDL and Verilog libraries for Xilinx may have to be installed in Videos Active-HDL. You can check what libraries are currently installed in your Active-HDL using Library Manager tool. You can access the Library Manager from the menu View>Library Manger>. Recorded Webinars You can install precompiled libraries in multiple ways: 1. If you are using Active-HDL DVD to install the software, during the installation, you will get the option to select and install the Xilinx libraries 2. If you have received a web link to download Active-HDL, on the same page you will find the links to download Xilinx libraries. 3. At any time you can visit the update center to download the latest Xilinx libraries at http://www.aldec.com/support Set Active-HDL as Simulator in Xilinx Project Navigator After creating a project, open your Xilinx project in ISE Project Navigator.
    [Show full text]
  • Eee4120f Hpes
    The background details to FPGAs were covered in Lecture 15. This Lecture 16 lecture launches into HDL coding. Coding in Verilog module myveriloglecture ( wishes_in, techniques_out ); … // implementation of today’s lecture … endmodule Lecturer: Learning Verilog with Xilinx ISE, Icarus Verilog or Simon Winberg Altera Quartus II Attribution-ShareAlike 4.0 International (CC BY-SA 4.0) Why Verilog? Basics of Verilog coding Exercise Verilog simulators Intro to Verilog in ISE/Vivado Test bench Generating Verilog from Schematic Editors Because it is… Becoming more popular than VHDL!! Verilog is used mostly in USA. VHDL is used widely in Europe, but Verilog is gaining popularity. Easier to learn since it is similar to C Things like SystemC and OpenCL are still a bit clunky in comparison (although in years to come they become common) I think it’s high time for a new & better HDL language!! (Let’s let go of C! And scrap ADA for goodness sake. Maybe I’ll present some ideas in a later lecture.) break free from the constraints of the old language constructs History of Verilog 1980 Verilog developed by Gateway Design Automation (but kept as their own ‘secret weapon’) 1990 Verilog was made public 1995 adopted as IEEE standard 1364-1995 (Verilog 95) 2001 enhanced version: Verilog 2001 Particularly built-in operators +, -, /, *, >>>. Named parameter overrides, always, @* 2005 even more refined version: Verilog 2005 (is not same as SystemVerilog!) SystemVerilog (superset of Verilog-2005) with new features. SystemVerilog and Verilog language standards were merged into SystemVerilog 2009 (IEEE Standard 1800-2009, the current version is IEEE standard 1800-2012).
    [Show full text]
  • White Paper FPGA Performance Benchmarking Methodology
    White Paper FPGA Performance Benchmarking Methodology Introduction This paper presents a rigorous methodology for benchmarking the capabilities of an FPGA family. The goal of benchmarking is to compare the results for one FPGA family versus another over a variety of metrics. Since the FPGA industry does not conform to a standard benchmarking methodology, this white paper describes in detail the methodology employed by Altera and shows how a poor methodology can skew results and lead to false conclusions. The complexity of today's designs together with the wealth of FPGA and computer-aided design (CAD) tool features available make benchmarking a difficult and expensive task. To obtain meaningful benchmarking results, a detailed understanding of the designs used in comparisons as well as an intimate knowledge of FPGA device features and CAD tools is required. A poor benchmarking process can easily result in inconclusive and, even worse, incorrect results. Altera invests significant resources to ensure the accuracy of its benchmarking results. Altera benchmarking methodology has been endorsed by industry experts as a meaningful and accurate way to measure FPGAs' performance: To evaluate its FPGAs, Altera has created a benchmarking methodology that fairly considers the intricacies and optimizations of its competitors' tools and devices, as well as its own. Experiments that consider a variety of end-user operating conditions have been run on a suite of industrial benchmark circuits. The results of these experiments have been analyzed to accentuate experimental variations and to clearly identify result trends. I am convinced that the experimental methodology that has been used fairly characterizes appropriate user expectations for Altera's devices in terms of area utilization and speed versus their competitors.
    [Show full text]