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Stratix II Vs. Virtex-4 Power Comparison & Estimation Accuracy

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White Paper Stratix II vs. Virtex-4 Power Comparison & Estimation Accuracy Introduction This document compares power consumption and power estimation accuracy for Altera® Stratix® II FPGAs and Xilinx Virtex-4 FPGAs. The comparison addresses all components of power: core dynamic power, core static power, and I/O power. This document uses bench-measured results to compare actual dynamic power consumption. To compare power estimation accuracy, the analysis uses the vendor-recommended power estimation software tools. The summary of these comparisons are: Altera’s Quartus® II PowerPlay power analyzer tool is accurate (to within 20%), while Xilinx’s tools are significantly less accurate. Stratix II devices exhibit lower dynamic power than Virtex-4 devices, resulting in total device power that is equal. Having an accurate FPGA power estimate is important to avoid surprises late in the design and prototyping phase. Inaccurate estimates can be costly and cause design issues, including: board re-layout, changes to power-management circuitry, changes cooling solution, unreliable FPGA operation, undue heating of other components, and changes to the FPGA design. Furthermore, without accurate power estimates, it is impossible for the designer and FPGA CAD software to optimize design power. This white paper contains the following sections: Components of total device power Power estimation and measurement methodology Core dynamic power comparison – power tool accuracy and bench measurements Core Static power comparison I/O power comparison Total device power summary For competitive comparisons on performance and density between Stratix II and Virtex-4 devices, refer to the following white papers from the Altera web site: Stratix II vs. Virtex-4 FPGA Performance Comparison White Paper Stratix II vs. Virtex-4 Density Comparison White Paper Components of Total Device Power Total device power is the sum of three components: core dynamic power, core static power, and I/O power. Core dynamic power is the power dissipated by the operation of the FPGA core fabric. This power increases linearly with operating frequency. Core static power is the power dissipated that is independent of frequency (such as leakage current across a transistor) and can be determined by stopping all clocks (an operating frequency of 0 MHz). The final power component, I/O power, is the power dissipated in the FPGA I/O cells to communicate with other chips. Figure 1 shows the breakdown of power into these three components for the average Stratix II design. This data was obtained by estimating the power consumption of 99 complete designs with the Quartus II software version 5.0 SP1 PowerPlay power analyzer. August 2005, ver. 1.0 1 WP-S20805-01 Stratix II vs. Virtex-4 Power Comparison & Estimation Accuracy White Paper Altera Corporation 11.2% 21.7% Core Dynamic Core Static I/O 67.1% Figure 1. Average Breakdown of Total Power in Stratix II Designs (Typical Conditions, 12.5% Toggle Rate) The data in Figure 1 uses the 3.3-V LVTL I/O standard with 10-pF output loading. In addition, Figure 1 reflects static power at typical conditions. At worst-case conditions, the proportion of static power will increase. Figure 1 shows that static power is on average 21.7% of total device power which is relatively significant compared to previous generation FPGAs. However, core dynamic power remains the most important portion of total device power. Power Estimation & Measurement Methodology FPGA vendors provide power estimation tools to help users design the board power supply and the system cooling solution. These power estimation tools also help designers optimize device power consumption. Altera tools generate power estimates based on parameters such as design resource utilization, routing utilization, clock frequencies, device, I/O loading, temperature, and silicon process. Each of these parameters can affect static power, dynamic power, or both. Stratix II static power is primarily affected by device junction temperature, voltage, and silicon process variation. Altera supplies typical and worst-case power specifications. These specifications are based on silicon characterization performed across a wide array of devices across various extremes of silicon process variation. All devices shipped meet the worst-case specification, and this specification should be used in the design of system thermal solutions. Dynamic power is primarily affected by design resource utilization, design implementation, routing utilization, and circuit switching activity. Silicon process and temperature variation have very little effect on dynamic power. A power model of each element within the Stratix II FPGA enables accurate power estimation. If a designer knows the design information (such as utilization, frequency, or I/O loading), then an estimation of power can be made. Either the designer can make an educated guess of the design information or compile the design to gain more accurate design information. 2 Altera Corporation Stratix II vs. Virtex-4 Power Comparison & Estimation Accuracy White Paper Altera’s Power Estimation Tools There are three primary methods of assessing the power consumption of a Stratix II design, which are listed as follows, from least accurate to most accurate: Stratix II PowerPlay Early Power Estimator Spreadsheet. This spreadsheet generates design power estimates based on user-entered resource utilization, toggle rates, and environmental conditions. The early power estimator is used prior to design implementation and as a result, accuracy of the power estimation data is dependant on the accuracy of the design information entered by the user. The power model used in this tool is based on the model in the Quartus II PowerPlay power analyzer tool, but assumes typical logic implementation and routing utilization. The analogous Xilinx tool is the Web Power Tool (WPT). The early power estimator accuracy is generally within ±20% of the Quartus II PowerPlay power analyzer estimates, assuming perfect toggle-rate entry. Quartus II PowerPlay Power Analyzer. The PowerPlay power analyzer is integrated in the Quartus II software and generates design power estimates based on Quartus II software place-and-route information and toggle rate data from a variety of sources. The power analyzer performs power analysis based on the exact resources, logic functions, and routing paths used in the target design. It can derive toggle rates from user entry, statistical circuit analysis techniques, RTL simulation, and gate-level simulation. The power analyzer can optionally filter out pulses, or glitches, from simulation data when those glitches are too fast to toggle the logic and routing of an actual FPGA. The highest-quality estimates are found when using the Power Analyzer with glitch-filtered gate-level simulations. Unless noted, this document shows results comparing Quartus II software version 5.0 SP1 PowerPlay power analyzer estimations to Stratix II bench results, demonstrating estimation error within ±20%, with a bias toward over estimation. Results for the analogous Xilinx tool, ISE XPower 7.1 SP2, are shown alongside Virtex-4 bench results, with estimation error results that range from a 8× underestimation to 3× overestimation. Bench Measurements. The best estimate of a design’s dynamic power is obtained by measuring a design in-system. This is done by measuring the amount of current the FPGA is drawing on each power rail at the required frequency. Static power results from single-unit measurements are not meaningful due to significant unit-to-unit static power variation. The vendor-provided worst-case specification should be used instead (as explained in the static power consumption section of this document). Use the following steps to obtain a worst-case estimate for total device power in-system: 1. Measure the power drawn from each power supply voltage from a device configured with the correct I/O standards and phase-locked loop (PLL)/digital clock manager (DCM) usage, with a 0-MHz clock. This provides the baseline static power consumption for the FPGA. Punconfigured _ static,measured = ∑ I i ⋅Vi (1) i∈All sup plies 2. Program the FPGA with the design-under-test and measure the power drawn from all power rails with each clock running at its target frequency. This provides a measurement of total power (dynamic and static power). 3. Compute the worst-case total power of a device running this design by adding in the difference between the static power of this device measured in #1 and the vendor-supplied worst-case 3 Stratix II vs. Virtex-4 Power Comparison & Estimation Accuracy White Paper Altera Corporation specification for static power (using the correct I/O standards and phase-locked loop (PLL)/digital clock manager (DCM) usage). PTotal ,worst−case = POperation,measured + (Pstatic,worst−case−spec − Punconfigured _ static,measured ) (2) Altera designed and developed a power test board to compare Stratix II and Virtex-4 power consumption. This board, shown in Figure 2, has two electrically isolated halves, one with a Stratix II EP2S60 device and the other with a Virtex-4 LX60 device. The two board halves are identically designed except where device requirements require small differences. The FPGA power rails are isolated and individually regulated, allowing for precise measurements of supply current per power rail. I/O traces for each device are matched in length to allow for accurate I/O power comparisons. Figure 2. EP2S60 & LX60 Board Used for Comparing Dynamic & I/O Power For more information on Altera’s power estimation tools, see the Power Estimation & Analysis section in the Quartus II Development Software Handbook. Dynamic Power Comparison: Stratix II vs. Virtex-4 FPGAs To compare the dynamic power of a Stratix II device to a Virtex-4 device, Altera compared measured and estimated results across a variety of designs selected to provide coverage of many types of FPGA functions. Circuits were coded in an architecture-independent hardware description language (HDL) wherever possible. In some cases, such as RAM designs, the respective MegaWizard® Plug-In Manager or Core Generator tools were used to generate designs with matching parameters.
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