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Xilinx UG925, Zynq-7000 EPP ZC702 Base Targeted Reference Design Zynq-7000 EPP ZC702 Base Targeted Reference Design User Guide UG925 (v1.0 ) June 21, 2012 Notice of Disclaimer The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of the Limited Warranties which can be viewed at http://www.xilinx.com/warranty.htm; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in Critical Applications: http://www.xilinx.com/warranty.htm#critapps. Automotive Applications Disclaimer XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III) USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN SUCH APPLICATIONS. © Copyright 2012 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. AMBA, AMBA Designer, ARM, ARM1176JZ-S, CoreSight, Cortex, and PrimeCell are trademarks of ARM in the EU and other countries. PCI Express is a trademark of PCI-SIG and used under license. HDMI, HDMI logo, and High-Definition Multimedia Interface are trademarks of HDMI Licensing LLC. All other trademarks are the property of their respective owners. Revision History The following table shows the revision history for this document. Date Version Revision 06/21/12 1.0 Initial Xilinx release. Zynq-7000 ZC702 Base TRD User Guide www.xilinx.com 2 UG925 (v1.0 ) June 21, 2012 Table of Contents Revision History . 2 Chapter 1: Introduction The Base Targeted Reference Design . 4 Base TRD Key Features . 6 Chapter 2: Functional Description Hardware Architecture . 8 Software Architecture . 20 Appendix A: Register Description TPG Registers . 30 Clock Detect Registers . 33 Appendix B: Directory Structure Included Files and Systems . 35 Appendix C: Install the Zynq-7000 EPP Design and Development Environment Install the Xilinx ISE Design Suite . 37 Set Up Linux System Software Development Tools. 37 Set Up git Tools . 37 Appendix D: Additional Resources Xilinx Resources . 38 References . 38 Zynq-7000 ZC702 Base TRD User Guide www.xilinx.com 3 UG925 (v1.0 ) June 21, 2012 Chapter 1 Introduction This user guide describes the Base Targeted Reference Design (TRD) based on Zynq™-7000 Extensible Processing Platform (EPP) architecture. The TRD is included with the ZC702 Evaluation kit. To learn more about the ZC702 Evaluation kit and how to evaluate different demonstrations based on Zynq-7000 EPP architecture, refer to UG926, Zynq-7000 EPP ZC702 Evaluation Kit Getting Started Guide [Ref 1]. This document explains the functional architecture of the hardware and software components of the TRD. Also provided are register descriptions for IP/logic implemented in programmable logic (PL), Base TRD package directory structure, and pointers to enable the user to further develop embedded platforms based on Zynq-7000 EPP architecture. The Base Targeted Reference Design The Base TRD showcases various features and capabilities of the Zynq Z-7020 EPP device for the embedded domain in a single package using a Xilinx standard Zynq Linux-based video pipeline design. The Base TRD consists of two processing elements: The Zynq-7000 EPP processing system (PS) and a video accelerator based on PL. The EPP allows the user to implement a specific functionality either as a software program running on the Zynq-7000 EPP PS or as a hardware design inside the PL. The Base TRD demonstrates an optimization of how the user can seamlessly switch between a software or a hardware implementation, contributing to ease of use. The TRD also demonstrates the value of offloading computation-intensive tasks onto PL, thereby freeing the CPU resources available for user-specific applications. Software developers can leverage the Base TRD and start programming right away using the widely known Eclipse-based integrated development environment (IDE), GNU compiler tool chain, Linux operating system (OS), and libraries. Embedded hardware designers now have immediate access to the industry standard ARM® Cortex™-A9 core processor system and video IPs running on PL out of the box. In addition, the TRD also provides customers with access to the various PL-based video components VDMA, TPG, VTC, Sobel filter, and the Xylon logiCVC-ML display controller [Ref 28]. These IPs are part of the video pipeline implemented in the PL. The Base TRD consists of a PS based on the embedded ARM Cortex-A9 core processor, a video processing pipeline implemented in PL, and a Linux-based software application that Zynq-7000 ZC702 Base TRD User Guide www.xilinx.com 4 UG925 (v1.0 ) June 21, 2012 The Base Targeted Reference Design includes a Qt-based graphical user interface (GUI) [Ref 29] to provide user control and monitoring. The Linux-based software platform and software application run on the ARM Cortex-A9 cores. The software application works in tandem with hardware and provides the user the choice of offloading computation-intensive processing to the PL-based hardware subsystem. The Zynq-7000 EPP Base TRD reference design (Figure 1-1) consists of these components: • A dual ARM Cortex-A9 core processor-based embedded Linux OS, board support package (BSP), and U-Boot boot loader • PL-based hardware IPs that enable acceleration of computation-intensive video processing tasks • Linux-based application software components to configure and control the PL-implemented hardware processing IPs and the data flow between PL-based video components and the PS X-Ref Target - Figure 1-1 Linux User Space Qt-Based Multithreaded Application Linux Kernel Kernel Libraries and Utilities Device Drivers Processing Programmable System Logic DDR Memory Controller AMBA Switches Video Display Controller Output Video Processing APU (Sobel Filter) Video Test Pattern Generators AMBA Switches S_AXI3_HP 64 bit M_AXI3_GP 32 bit UG925_c1_01_061712 Figure 1-1: Zynq-7000 EPP Base TRD System Block Diagram The TRD deliverables include source code for RTL design and software packages such as the Linux OS, device drivers, the application, and the GUI. Zynq-7000 ZC702 Base TRD User Guide www.xilinx.com 5 UG925 (v1.0 ) June 21, 2012 Base TRD Key Features Base TRD Key Features Components in the Base TRD are further described in this section. The Base TRD processing system (PS) includes: •A dual ARM Cortex-A9 core • ARM AMBA® AXI interconnect • Multi-protocol, 32-bit DDR DRAM controller • 1 GB DDR3 running at 533 MHz • Standard peripheral interfaces including USB, Ethernet, UART, I2C, SD MMC, and GPIO Base TRD programmable logic includes: • Two AXI interconnects, 64-bit wide at 150 MHz • One AXI interconnect, 32-bit wide at 75 MHz •AXI VDMA(s) • A full HD video input and output interface • A Sobel accelerator • Two AXI Performance Monitors Base TRD software includes: • Xilinx Zynq-7000 standard Linux kernel (based on Open Source Linux 3.x) • Linux device drivers for TRD-specific IPs • Qt-based Linux application demonstrating the video processing pipeline List of Acronyms Table 1-1 lists acronyms used in this document. Table 1-1: Acronyms Acronym Definition AFI AXI FIFO interface APU Application processor unit BSP Board support package DTB Device tree binary DTS Device tree source Zynq-7000 ZC702 Base TRD User Guide www.xilinx.com 6 UG925 (v1.0 ) June 21, 2012 Base TRD Key Features Table 1-1: Acronyms (Cont’d) Acronym Definition EDK Embedded Development Kit EPP Extensible processing platform FMC FPGA mezzanine card FPS Frames per second FSBL First-stage boot loader GIC General interrupt controller GUI Graphical user interface HD High definition IDE Integrated development environment IOP Input/output peripherals IP Intellectual property KFLOPS kilo floating-point operations
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