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XC2S50 FPGA Board for Microprocessor and Digital Design Applications AU J.T. 9(1): 41-45 (Jul. 2005) XC2S50 FPGA Board for Microprocessor and Digital Design Applications Wutthikorn Threevithayanon, Kittiphan Techakittiroj, Narong Aphiratsakun, and Soe moe Nyun Faculty of Engineering, Assumption University Bangkok, Thailand Abstract This paper describes the implementation of Field-Programmable Gate Array (FPGA) boards for digital design applications and development of a Spartan-II Xilinx’s FPGA user programmable system (ISP). The objective of the designed board is to use it for conducting experiments in the Microprocessor Laboratory of the Faculty of Engineering. It will help the students to implement CPU or other digital logic devices such as MP3 player, VGA card or a microcomputer interface card such as PCI. Keywords: Field-Programmable Gate Array, FPGA, Digital devices, Xilinx, Spartan-II, ISP. 1. Introduction programmable logic device that supports the implementation of a relatively large logic Traditionally, to implement a designed circuit and a developed chip. Hardware IC circuit, it is first synthesized into net list by programming can be easily done configuring synthesis tools, and then implemented by the device (Brown and Vranesic 2003). Place and Route process. Then, it is fabricated In Thailand, the government into silicon by Layout synthesis process organization NECTEC (Thailand IC Design known as Application Specific Integrated Incubator (TIDI) NECTTEC) is trying to Circuits (ASICs). In a university or in promote the use of FPGA among engineers industries, electronic product design is by organizing training courses such as implemented by making a Printed Circuit “Verilog Applications Workshops” (Chip Board (PCB) and mounting basic multiples of Design with Verilog). To catch up with this IC chips. Testing of the designed circuit can new technology, the research team of the be done only after assembly and soldering the Assumption University is developing an IC chips onto the PCB. Now programmable educational evaluation FPGA board that will logic devices, especially field programmable cost lesser than an imported one. Our work is gate arrays (FPGA), have begun to take on focused on Spartan II XC2S50 FPGA chip this role in system design. FPGA will reduce from Xilinx, which can contain about 50,000 both cost, time and space in implementing the logic gates and can be upgraded to be IC chip and Electronic design as compared to XC2S200 containing about 200,000 logic the old fashioned method. gates (XC2S50 and XC2S200 have the same package design). Digital logic circuits are widely used in This paper consists of 6 sections. Section many applications. So many companies 2 reviews FPGA Spartan-II family from Xilinx. (Xilinx, Atera, Atmel) are trying to develop Board design and specifications will be ways to implement digital logic circuits easier, discussed in Section 3. Sections 4 and 5 discuss quicker and cheaper. To implement larger FPGA software development and board circuits, it is convenient to use a chip that has application. The main conclusions will be larger logic capability. FPGA is a given in the last section of the paper. 41 2. Overview of FPGA The user I/O for each series also depends Spartan-II family on the package of the FPGA. VQ100, TQ144, CS144, PQ208, FG256 and FG456 are The Spartan-II FPGA family currently examples of the package combinations. JTAG composes of six models XC2S15, XC2S30, configuration can be used to configure the XC2S50, XC2S100, XC2S150, and XC2S200. Spartan-II devices, as they have supported the The system gates will range from 15,000 to IEEE 1149.1 boundary-scan instruction standard 200,000 as indicated by the last few digits at (Xilinx 2002). end of the model number. It contains 16K to 56K blocks of RAM. System clock can be used 3. Board Design and Specification up to 200MHz (Xilinx 1998). Chips of this family have Configurable Logic Blocks Our work concentrated on XC2S50 FPGA (CLBs) and programmable architecture, model from Xilinx. Xilinx’s FPGA XC2S50 surrounded by programmable Input/Output chip contains 50,000 gates, 32K RAM with the Blocks (IOBs). The architecture also provides 176 maximum available I/O ports. PQ208 (28 Block RAM and Delay-Locked Loops (DLLs). mm by 28 mm) 208-pin plastic Quad Flat Pack The basic block diagram of XC2S15 Spartan-II (QFP) package is used in our work due to high family is shown as in Fig.2-1 (Xilinx 2001). volume and low cost package (Pragasam 2001; Xilinx 2001a; Xilinx 2001b). 3.3 6.7 cm cm 50 26 24 13 m 3 c 5. AB 1 1 12 25 Fig. 3-1. DIP FPGA designed board Fig. 2-1. Block diagram of Spartan-II family CLBs provide the functional elements for constructing most of the logic that implements combinatorial logic in small look-up tables (LUTs). IOBs provide the interface between the package pins and the internal logic. The Fig. 3-2. FPGA XC2S50 designed board package pins are available as bi-directional user I/O. Blocks of RAM are organized in columns The designed main board contains basic used to provide shallow memory structure in peripherals like: crystal oscillator, 4-way CLBs. These Blocks of RAM also used as a selector DIP switch, LEDs, two 7-segments routing interface between CLBs and other display and 66-pin user I/Os. The board is Blocks of RAM. Clock DLLs are used to designed to be a module plug-in like a dual in- monitor the input clock and automatically line (DIP) package. It will be mounted on two adjusts a delay element. DLLs also allow clock DIP package (A: 50 and B: 24 pins) as shown duplication and frequency adjustment. in Fig 3-1. It can be plugged into a normal 42 AU J.T. 9(1): 41-45 (Jul. 2005) breadboard and can easily expand its I/O ports The Spartan-II FPGA is supported by the by an attachable daughter board. Its final size is Xilinx ISE WebPack free development system. 10x5.3 cm and is shown in Fig. 3-2. It can be It can be downloaded from Xilinx web site. seen that the FPGA board contains the ModelSim is the software use for simulation following peripherals: and one needs to register before using it with • FPGA Spartan-II XC2S50-6PQ208C by the Xilinx ISE Webpack. Xilinx • 74 I/Os pin connector (66 usable I/Os) 5. Board Applications • Crystal oscillator • 4-way selector DIP switch The board designed is very flexible and • Four push buttons can be used for many applications, such as: • 8 LEDs • Learning programmable logic design • Two 7-Segments Display • ASIC replacement DC 5 V can power the board. It contains • System on Chip design two linear voltage regulators; 2.5 and 3.3 V. • Microprocessor development and can operate as stand-alone once • Digital signal processing programmed. The available I/Os and pin assignments are given the Appendix. Once the circuit is designed and is downloaded into to the FPGA chip, the chip 4. Software Development can be considered as an IC itself, as shown in Fig. 5-1. Input and output pins (I/Os) have to Xilinx ISE WebPack can develop a logic be connected to other devices to check for the circuit by Verilog, VHDL, or Schematic designed function. Currently XC2S50 FPGA drawing. Then the input and output pins of the Spartan-II board is used in the Microprocessor designed circuit are assigned to map the System Laboratory to teach students as to how hardware device. After the design has been to implement a CPU by themselves. implemented, the utilization of the gates in the chip can be realized at Place & Route window. JTAG is then used to generate the Input Output pins pins programming files to the FPGA chip (Xilinx FPG A 1998; Xilinx 2002). The download cable is Ch ip compatible with Xilinx Parallel Cable III, so that it can be used to download Xilinx’s software for FPGA configuration. The Desi gned programmed implemented JTAG download cable is shown in Fig. 4-1. Fig. 5-1. CPLD board implemented as an IC chip Conclusion XC2S50 FPGA board is designed by the research team at Assumption University to be used in Microprocessor System Laboratory for teaching and for other digital circuit applications. With the knowledge of Verilog or VHDL, the board can be used effectively to Fig. 4-1. JTAG programming board implement any complicated digital circuit. 43 Appendix DIP B External Pins: 1-24 Pin No. Xilinx Pin No. Pin Name Function Pin mapping for the FPGA board is given 36 182 GCK2 Clk Input under. Used pins have to be assigned to the 37 185 GCK3 Clk Input Xilinx ISE Webpack before configuring the chip. 38 187 IO34 I/O 39 188 IO35 I/O DIP A External Pins: 1-50 40 189 IO36 I/O 41 191 IO37 I/O 42 192 IO38 I/O Xilinx Pin 43 193 IO39 I/O Pin No. No. Pin Name Function 1 Vcc Vcc ( 5V ) 44 194 IO40 I/O 2 57 IO1 I/O 45 195 IO41 I/O 3 58 IO2 I/O 46 199 IO42 I/O 4 59 IO3 I/O 47 200 IO43 I/O 5 60 IO4 I/O 48 201 IO44 I/O 6 61 IO5 I/O 49 202 IO45 I/O 7 62 IO6 I/O 50 GND Ground 8 63 IO7 I/O 9 67 IO8 I/O 10 68 IO9 I/O 11 70 IO11 I/O Pin No. Xilinx Pin No. Pin Name Function 12 69 IO10 I/O 1 3.3V *Vcc ( 3.3V ) 13 71 IO12 I/O 2 94 IO46 I/O 14 73 IO13 I/O 3 95 IO47 I/O 15 74 IO14 I/O 4 96 IO48 I/O 16 75 IO15 I/O 5 97 IO49 I/O 17 77 GCK1 Clk Input 6 98 IO50 I/O 18 82 IO23 I/O 7 99 IO51 I/O 19 83 IO22 I/O 8 100 IO52 I/O 20 84 IO21 I/O 9 101 IO53 I/O 21 86 IO20 I/O 10 102 IO54 I/O 22 87 IO19 I/O 11 132 IO55 I/O 23 88 IO18 I/O 12 GND *Ground 24 89 IO17 I/O 13 GND *Ground 25 90 IO16 I/O 14 133 IO56 I/O 26 81 IO24 I/O 15 146 IO57 I/O 27 172 IO25 I/O 16 147 IO58 I/O 28 173 IO26 I/O 17 148 IO59 Clk Input 29 174 IO27 I/O 18 149 IO60 I/O 30 175 IO28 I/O 19 150 IO61 I/O 31 176 IO29 I/O 20 151 IO62 I/O 32 178 IO30 I/O 21 152 IO63 I/O 33 179 IO31 I/O 22 154 IO64 I/O 34 180 IO32 I/O 23 203 IO65 I/O 35 181 IO33 I/O 24 2.5V *Vcc ( 2.5V ) 44 AU J.T.
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