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Mixed-Signal Simulation User Guide

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Mixed-Signal Simulation User Guide Mixed-Signal Simulation User Guide Version J-2014.09, September 2014 Copyright and Proprietary Information Notice © 2014 Synopsys, Inc. All rights reserved. This software and documentation contain confidential and proprietary information that is the property of Synopsys, Inc. The software and documentation are furnished under a license agreement and may be used or copied only in accordance with the terms of the license agreement. No part of the software and documentation may be reproduced, transmitted, or translated, in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without prior written permission of Synopsys, Inc., or as expressly provided by the license agreement. Destination Control Statement All technical data contained in this publication is subject to the export control laws of the United States of America. Disclosure to nationals of other countries contrary to United States law is prohibited. It is the reader’s responsibility to determine the applicable regulations and to comply with them. Disclaimer SYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Trademarks Synopsys and certain Synopsys product names are trademarks of Synopsys, as set forth at http://www.synopsys.com/Company/Pages/Trademarks.aspx. All other product or company names may be trademarks of their respective owners. Synopsys, Inc. 700 E. Middlefield Road Mountain View, CA 94043 www.synopsys.com ii Mixed-Signal Simulation User Guide J-2014.09 Contents Audience . xv Related Publications . xv Conventions . xvi Customer Support . xvi 1. Getting Started with Mixed-Signal Simulation . 1 Overview . 1 Three Mixed-Signal Simulation Flows . 3 Verilog-SPICE (Flow #1) . 3 VHDL/Verilog-SPICE (Flow #2) . 3 Verilog-AMS-SPICE (Flow #3) . 3 Preparing for a Mixed-Signal Simulation . 4 Donut Configuration . 4 Mixed-Signal Simulation Setup File . 7 Compiling and Running a Mixed-Signal Design. 8 Mixed-Signal Report Files . 8 simv.msv Directory and Mixed-signal Report Files . 9 hierarchy.rpt . 9 interface_element.rpt . 10 mview.rpt . 11 names_map.rpt . 11 port.rpt . 12 runtime_interface_element.rpt . 14 through_net.rpt. 14 use_cell_view.rpt . 15 Save and Restore Feature . 15 Basic Save and Restore Usage . 16 Running Multiple Simulations with Save and Restore . 16 Changing the Analog Configuration in the Middle of a Simulation. 18 The ace reread command . 19 Changes Allowed in the Configuration File . 19 Changes in the SPICE Netlist Allowed with the reread Command . 20 iii Contents Limitations . 20 Examples . 20 Meta-Encrypted SPICE Netlists in Mixed-Signal Design . 23 2. Running a Mixed-Signal Simulation with Verilog-AMS-SPICE . 25 Overview . 25 Running a Mixed-Signal Simulation in Verilog-AMS-SPICE . 25 Compile Options Specific to Verilog-AMS-SPICE . 26 -ams . 26 -ams_discipline logic . 26 -ams_iereport . 27 Required Input Files. 27 Verilog Netlist Files . 27 Mixed-Signal Simulation Setup File . 28 Files Containing Connect Rule and Connect Module Definitions. 28 Compiling and Running the Design . 29 Part I: Verilog-SPICE Mixed-Signal Simulations 3. Using Verilog-SPICE Mixed-Signal Features. 33 Overview . 33 Mixed-Signal Feature Highlights . 33 Verilog-top/SPICE-top Flows and Donut Configurations . 34 Multiple Views . 34 SPICE View Selection for Multi-View Cells Under Verilog . 35 Verilog View Selection for Cells Under a SPICE Parent. 35 Automatic Verilog Dummy Module Generation . 35 Verilog-A Model Instantiation . 36 Parameter Passing Rule. 36 XMR (Cross Module Referencing) Across Analog-Digital Boundary . 37 Logic XMR Access to Analog Nodes . 37 Real XMR Access to Analog Nodes . 39 $snps_force_volt() . 39 $snps_release_volt() . 40 $snps_get_volt(). 40 $snps_get_port_current(). 41 iv Contents snps_above ( ) . 42 snps_cross ( ). 43 Interface A/D and D/A Signal Conversions . 44 Cases Where A/D and D/A Converters are Not Inserted . 46 Signal Conversion from Verilog-to-SPICE and SPICE-to-Verilog. 49 Converting Signal Values . 49 Dynamic Supply in Mixed-Signal . 51 Converting Signal Strength . 53 Creating a Resistance Map File . 56 Postlayout Simulation Through Back-annotation . 58 Using the SDF File. 58 Known Limitations . 59 Known Problems . 59 4. Mixed-Signal Simulation in the Verilog-SPICE Flow. 61 Overview . 61 Mixed-signal Setup Checklist. 62 Netlist-Related Issues . 62 Identical Module/Subcircuit Name . 63 Case Sensitivity . 63 Power Supplies . 63 Method #1 . 63 Method #2 . 64 Method #3 . 67 Netlist Statements . 68 Simulation Time . 68 Port-Related Issues . 69 Port Mapping . ..
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