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Megacore IP Library Release Notes and Errata

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Megacore IP Library Release Notes and Errata MegaCore IP Library Release Notes and Errata 101 Innovation Drive MegaCore Library Version: 8.1 San Jose, CA 95134 Document Version: 8.1.3 www.altera.com Document Date: 1 February 2009 Copyright © 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending ap- plications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. RN-IP-3.3 Contents About These Release Notes System Requirements . xi Update Status . xi Chapter 1. 8B10B Encoder/Decoder Revision History . 1–1 Errata . 1–1 Chapter 2. ASI Revision History . 2–1 Errata . 2–1 NativeLink Simulation Fails . 2–1 VCS Simulator . 2–2 NativeLink Does Not Support Gate-Level Simulation . 2–2 Chapter 3. CIC Revision History . 3–1 Errata . 3–1 Synthesis Error When Number of Stages is Greater than 10 . 3–1 Chapter 4. CRC Compiler Revision History . 4–1 Errata . 4–1 Incorrect crcchannel Value in Multi-Channel Mode . 4–1 Testbench Directory Generated When You Create a Simulation Model . 4–2 Chapter 5. DDR and DDR2 SDRAM Controller Compiler Revision History . 5–1 Errata . 5–1 VHDL Package Declaration Error When Upgrading the MegaCore Function . 5–1 Read Requests Are Sometimes Discarded . 5–2 “Cannot Find Source Node” Error During Post-Compile Timing Analysis . 5–2 Error: Can't Find the Clock Output Pins. Stop. 5–3 ODT Launches Off System Clock . 5–3 Simulating with the NCSim Software . 5–4 Simulating with the VCS Simulator . 5–4 Error Message When Recompiling a Project . 5–5 Pin Planner HDL Syntax Error . 5–6 Chapter 6. DDR and DDR2 SDRAM High-Performance Controller Revision History . 6–1 Errata . 6–1 Intermittent Read Failure After Calibration . 6–2 Incorrect Controller Latency Information in User Guide . 6–2 DDR and DDR2 High-Performance Controllers Verilog HDL Design Doesn’t Work . 6–3 SOPC Builder Does Not Recognize Decimal Points . 6–3 Inefficient Write Request to An Open Bank . 6–4 Unnecessary Warning During Generation . 6–4 © 1 February 2009 Altera Corporation Library Version 8.1 MegaCore IP Library Release Notes and Errata Preliminary iv Memory Timing Parameter tWR Is Set Incorrectly . 6–5 Unable to Deliberately Corrupt the ECC Data When Using the Native Interface . 6–5 DDR or DDR2 SDRAM High-Performance Controllers May Not Appear in SOPC Builder . 6–6 Possibility of Calibration Failure . 6–6 Precharge-all Command Not Always Issued Before Auto-Refresh Command . 6–7 RTL Simulation May Fail When Dedicated Memory Clock Outputs Are Selected . 6–7 Gate Level Simulation Fails . 6–8 VHDL Simulation Fails When DDR CAS Latency 2.0 or 2.5 Is Selected . 6–8 Memory Presets Contain Some Incorrect Memory Timing Parameters . 6–9 Mimic Path Incorrectly Placed . 6–10 Simulating with the NCSim Software . 6–10 Simulating with the VCS Simulator . 6–11 Chapter 7. DDR3 SDRAM High-Performance Controller Revision History . 7–1 Errata . 7–1 Incorrect Controller Latency Information in User Guide . 7–1 Unable to Deliberately Corrupt the ECC Data When Using the Native Interface . 7–2 DDR3 SDRAM High-Performance Controllers May Not Appear in SOPC Builder . 7–2 Generate Netlist Option Does Not Work . 7–3 Chapter 8. FFT Revision History . 8–1 Errata . 8–1 Display Symbol Button in IP Toolbench is Missing . 8–1 Cannot Find Memory Initialization File if Not in Project Directory . 8–2 Floating-Point FFT Produces Non-Zero Output . 8–3 Simulation Errors—Synopsys VCS . ..
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