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Quartus II Software Version 6.1 Release Notes

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Quartus II Software Version 6.1 Release Notes Quartus II Software Release Notes December 2006 Quartus II software version 6.1 This document provides late-breaking information about the following areas of this version of the Altera® Quartus® II software. For information about memory, disk space, and system requirements, refer to the readme.txt file in your \altera\<version number> \quartus directory. For information about device support in this version of the Quartus II software, along with the latest information about timing and power models, refer to the Quartus II Device Support Release Notes on the Altera website at http://www.altera.com/literature/lit-qts.jsp. New Features & Enhancements .............................................................................2 EDA Interface Information ....................................................................................3 Changes to Software Behavior...............................................................................4 Known Issues & Workarounds.............................................................................12 General Quartus II Software Issues........................................................... 12 Platform-Specific Issues............................................................................ 23 Device Family Issues................................................................................. 31 Design Flow Issues.................................................................................... 43 SOPC Builder Issues ................................................................................. 46 EDA Integration Issues ............................................................................. 49 Simulation Model Changes ....................................................................... 51 Latest Known Quartus II Software Issues............................................................53 Software Issues Resolved.....................................................................................53 Revision History...................................................................................................56 Altera Corporation 1 RN-01015-1.0 Quartus II Software Release Notes Version 6.1 New Features & Enhancements The Quartus II software version 6.1 includes the following new features and enhancements: Advanced support for the Stratix III device family. The Chip Planner, an integrated floorplan editor and Chip Editor that provides a visual display of chip resources. The Tutorial, a new Flash-based Quartus II interactive tutorial that you can access from the Help menu. Advanced I/O Timing, which allows you to specify the board trace and any resistive or capacitive termination connected to each of the FPGA outputs. Multiprocessor support, which allows parallel processing during compilation for computers with multiple processors and results in a reduction in compilation times. Programmable Power Technology for Stratix III devices. Pin Planner enhancements to allow you to specify board trace model assignments. Detachable windows support. Windows 64-bit version. SUSE Linux Enterprise Server 9 in addition to Red Hat Enterprise Linux 3.0 and 4.0. Full device support for Cyclone II devices: EP2C8AF256, EP2C15AF256, EP2C15AF484, EP2C20AF256, and EP2C20AF484. Full device support for HardCopy II devices: HC210F484, HC240F1020, and HC240F1508. Full device support for MAX II devices: EPM240GF100, EPM240GM100, EPM570GF100, EPM570GM100, EPM570GM256, and EPM1270GM256. Full device support for Stratix II GX devices: EP2SGX30CF780, EP2SGX30DF780, EP2SGX60CF780, EP2SGX60DF780, EP2SGX60EF1152, and EP2SGX130GF1508. Altera Corporation 2 RN-01002-1.0 Quartus II Software Release Notes Version 6.1 EDA Interface Information The current version of the Quartus II software supports the following EDA tools. Supported EDA Tools Synthesis Tools Version NativeLink Support Synplicity Synplify & Synplify Pro 8.8 3 Mentor Graphics Precision RTL Synthesis 2006a 3 Mentor Graphics LeonardoSpectrum 2006a 3 Synopsys Design Compiler FPGA 2005.09 Synopsys FPGA Compiler II 3.8 3 Synopsys Design Compiler 2004.12-SP4 Magma Design Automation PALACE 2.4 3 Simulation Tools Version NativeLink Support Mentor Graphics ModelSim 6.1g 3 Mentor Graphics ModelSim-Altera 6.1g 3 Cadence NC-Sim (Windows) 5.4 s011 3 Cadence NC-Sim (UNIX) 5.82 p001 Synopsys VCS / VCS MX 2005.06-SP2 3 Aldec Active-HDL 7.1 SP1 3 Formal Verification Tools Version NativeLink (Equivalence Checking) Support Cadence Encounter Conformal 6.1 USR1 Synopsys Formality 2005.09 Chip Level Static Timing Analysis Version NativeLink Support Synopsys PrimeTime 2006.06 3 Board Level Static Timing Analysis Version NativeLink Support Mentor Graphics TAU 3.6 Board Level Symbol/Pin-out Management Version NativeLink Support Mentor Graphics I/O Designer 2005.1 Altera Corporation 3 RN-01002-1.0 Quartus II Software Release Notes Version 6.1 Changes to Software Behavior This section documents instances in which the behavior and default settings of this release of the Quartus II software have been changed from earlier releases of the software. Items listed in the following table represent cases in which the behavior of the current release of the Quartus II software is different from a previous version. Description Workaround Version 6.1 A minor change has been made to the power breakdown between I/O power and Core power in the PowerPlay Power Analyzer report. The total power dissipated on the device and the total current drawn from each voltage supply are unaffected. I/O routing power refers to the power dissipated by device core routing resources that are driven by input I/O cells. In Quartus II software versions 6.0 and 6.0 SP1, I/O routing power was reported on the PowerPlay Power Analyzer Summary report section as I/O power rather than core dynamic power. For a typical design, the net change is a change of less than 2% of power from I/O Power to Core Dynamic Thermal Power Dissipation in the Summary report section of the PowerPlay Power Analyzer. Also, the Core Dynamic Thermal Power Dissipation by Clock Domain report section did not enumerate the I/O routing power. The current version now supports the following Stratix II GX industrial ordering codes: EP2SGX90EF1152I4 EP2SGX90FF1508I4 EP2SGX130GF1508I4 EP2SGX60DF780I4 EP2SGX60EF1152I4 EP2SGX30DF780I4 Altera Corporation 4 RN-01002-1.0 Quartus II Software Release Notes Version 6.1 Description Workaround Designs that contain a user-edited Memory Correct the syntax of the Memory Initialization File (.mif) that compile Initialization File by referring to the Memory successfully earlier versions of the Quartus II Initialization File syntax description in the software may fail with the error "File Quartus II Help, or create a new Memory <filename>.mif contains illegal Initialization File with the Quartus II syntax at line <num>" in the software. Quartus II 6.1 software. These Memory Initialization Files contain illegal syntax. Illegal Memory Initialization Files were ignored by previous releases of the software. In the Quartus II software version 6.1, the tcllib library is updated from 1.7 to 1.8. If you are using advanced Tcl scripting, this change may cause your script to produce unexpected results. You may receive the following warnings Change get_nodes to use one of when you use the write_sdc command in get_ports, get_pins, get_nets, the TimeQuest Timing Analyzer: get_registers, or get_keepers. Warning: Ignored assignment create_generated_clock Warning: Collection filter Positional argument <source_objects> with value [get_nodes Pll_Inst\|altpll_component\|pll \|clk\[0\]] requires type (port pin reg kpr net ), but found type node. You receive these warnings because the create_clock or create_generated_clock assignments are ignored by the TimeQuest Timing Analyzer when using get_nodes collections. This issue is most likely to occur when using a Synopsys Design Constraints File (.sdc) generated from the Quartus II software version 6.0 or 6.0sp1 using the write_sdc command. Altera Corporation 5 RN-01002-1.0 Quartus II Software Release Notes Version 6.1 Description Workaround In the Quartus II software version 6.1, when you simulate designs that use MAX II UFM or any PLL, you might see X's in the initial part of the simulation time instead of 0's. The behavior after the X's are correct. This behavior is the same as in any third party simulators, but different from Quartus II Simulator in versions earlier than Quartus II software version 6.1. Version 6.0 SP1 In the Quartus II software version 6.0 and In the Quartus II software version 6.0 SP1, a earlier, when you created a receiver-only CMU PLL is no longer created when you instance of the alt2gxb megafunction, a CMU create a receiver-only instance. You must PLL was created that has pll_inclk and recreate the megafunction instance with the pll_locked ports. These ports prevented MegaWizard Plug-In Manager or manually the combination of two receiver-only remove the pll_inclk and pll_locked implementations at different data rates in the ports from the wrapper file. same quad. In the Quartus II software version 6.0 SP1 and You must manually change the pin name later, the TimeQuest Timing Analyzer no suffixes to lowercase in your SDC file. For longer recognizes uppercase pin suffix names example [get_pins myreg|CLK] should in an SDC constraints file. be changed to [get_pins myreg|clk]. Version 6.0 The TimeQuest Timing Analyzer's QSF2SDC The QSF2SDC conversion utility is conversion utility cannot properly convert all considered a guide to help reduce
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