Simulation User Guide (UG072)

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Simulation User Guide (UG072) All Achronix Devices www.achronix.com Simulation User Guide (UG072) Copyrights, Trademarks and Disclaimers Copyright © 2019 Achronix Semiconductor Corporation. All rights reserved. Achronix, Speedcore, Speedster, and ACE are trademarks of Achronix Semiconductor Corporation in the U.S. and/or other countries All other trademarks are the property of their respective owners. All specifications subject to change without notice. NOTICE of DISCLAIMER: The information given in this document is believed to be accurate and reliable. However, Achronix Semiconductor Corporation does not give any representations or warranties as to the completeness or accuracy of such information and shall have no liability for the use of the information contained herein. Achronix Semiconductor Corporation reserves the right to make changes to this document and the information contained herein at any time and without notice. All Achronix trademarks, registered trademarks, disclaimers and patents are listed at http://www.achronix.com/legal. Achronix Semiconductor Corporation 2903 Bunker Hill Lane Santa Clara, CA 95054 USA Website: www.achronix.com E-mail : [email protected] www.achronix.com 2 Simulation User Guide (UG072) Table of Contents Chapter - 1: Simulation Software Tool Flow . 7 Chapter - 2: Simulation Libraries . 9 Chapter - 3: General Project Setup . 10 User Design Project Directory Structure . 10 ACE Installation Library Directory Structure . 11 ACE Extension I/O Ring Library Directory Structure (Speedcore Only) . 11 Including Memory Initialization Files . 11 Chapter - 4: General RTL Simulation Flow . 13 Chapter - 5: General Gate-Level Simulation Flow . 14 Chapter - 6: General Post-Route Simulation Flow . 15 Chapter - 7: Example Design Description . 16 Chapter - 8: Synopsys VCS Simulator Example . 18 RTL Simulation in VCS . 18 Step 1 – Run the VCS Simulator . 18 Step 2 – Start the Simulation GUI . 19 Step 3 – Open the Simulation Database . 19 Step 4 – Reset the Layout . 20 Step 5 – Add Signals to the Waveform . 21 Step 6 – View the Simulation Results . 22 Gate-Level Simulation in VCS . 23 Step 1 – Create the Synthesis Project . 23 Step 2 – Synthesize the Design . 23 Step 3 – Run the VCS Simulator . 23 Post-Route Simulation in VCS . 23 Step 1 – Create the ACE Project . 23 Step 2 – Run Place and Route . 23 Step 3 – Run the VCS Simulator . 23 Chapter - 9: Cadence Incisive Simulator Example . 25 RTL Simulation in Incisive . 25 Step 1 – Invoke the Incisive Tool . 25 Step 2 – Add Signals to the Waveform . 26 www.achronix.com 3 Simulation User Guide (UG072) Step 2 – Add Signals to the Waveform . 26 Step 3 – Run the Simulation . 29 Step 4 – View the Waveform . 29 Step 5 – View Console Messages . 30 Gate-Level Simulation in Incisive . 31 Step 1 – Create the Synthesis Project . 31 Step 2 – Synthesize the Design . 31 Step 3 – Run Simulation . 31 Step 4 – View Simulation Results . 31 Post-Route Simulation in Incisive . 32 Step 1 – Create the ACE Project . 32 Step 2 – Run Place and Route . 32 Step 3 – Run Simulation . 33 Step 4 – View Simulation Results . 33 Chapter - 10: Mentor Questa Sim Simulator Example . 34 RTL Simulation in Questa Sim . 34 Step 1 - Create the Project . 34 Step 2 - Initialize the Work Library . 34 Step 3 - Create the File List . 34 Step 4 - Compile the Design . 35 Step 5 – Prepare the Simulation Run . 35 Step 6 – Set up the Waveform . 36 Step 7 – Run the Simulation . ..

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G A N E S H S UNDARARAJAN PO Box 5621, 4601 Lafayette St, Santa Clara, California 95056 H (469) 656-1095 [email protected] C (858)213 3219 SUMMARY A highly accomplished DESIGN/VERIFICATION ENGINEER with extensive experience in front-end RTL design in various technologies such as wireless MODEM (CDMA, WCDMA), imaging, data network, memory interfaces (WideIO), pre- and post-silicon verification strategy formulation and execution, embedded processor design aspects, and ASIC/FPGA design methodologies (front and backend flow). Possess a proven track record in converting concepts to products both as an individual contributor as well as a team leader. Worked with cross-functional teams including systems/architecture/SW teams to define specifications and successful completion of projects TECHNICAL SKILLS o Languages: System Verilog, Verilog, VHDL, System-C, C, C++, Perl, TCL, QuickCov (functional coverage), PSL/Sugar (Assertion Based Verification), PythonSV, Matlab o Simulation Tool: NCSIM, Modelsim, NCVerilog o Silicon Validation Environment: Ti Top-Sim Env o Synthesis: Cadence, Synopsys, Synplify o RTL linting: Spyglass o Static Timing Analysis: Primetime o ASIC Vendor: Agere Systems, Texas Instruments, AMI o Emulation Platform: Veloce (Mentor) o FPGA: Xilinx, Altera, Actel, Lattice PATENTS & HONORS . WIPO Patent WO2012068449: CONTROL NODE FOR A PROCESSING CLUSTER, May 2012, Texas Instruments Inc. WIPO Patent WO2012068486: LOAD/STORE CIRCUITRY FOR A PROCESSING CLUSTER, May 2012, Texas Instruments Inc. WIPO Patent WO2012068475, WO2012068498: METHOD AND APPARATUS FOR MOVING DATA FROM A SIMD REGISTER FILE TO GENERAL PURPOSE REGISTER FILE, May 2012, Texas Instruments Inc. WIPO Patent WO2012068478: SHARED FUNCTION-MEMORY CIRCUITRY FOR A PROCESSING CLUSTER, May 2012, Texas Instruments Inc.
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