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Intel® MAX® 10 FPGA Design Guidelines

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Intel® MAX® 10 FPGA Design Guidelines Intel® MAX® 10 FPGA Design Guidelines Subscribe M10-GUIDELINES | 2020.10.19 Send Feedback Latest document on the web: PDF | HTML Contents Contents 1. Intel® MAX® 10 FPGA Design Guidelines......................................................................... 4 1.1. Intel® MAX® 10 FPGA Design Guidelines...................................................................4 1.2. Before You Begin................................................................................................... 4 1.2.1. Read through the Device Overview of the FPGA............................................. 5 1.2.2. Estimate design requirements..................................................................... 5 1.2.3. Review available design tools...................................................................... 5 1.2.4. Review available IP.................................................................................... 5 1.3. Design Specifications............................................................................................. 6 1.3.1. Create detailed design specifications............................................................ 6 1.3.2. Create detailed functional verification or test plan.......................................... 6 1.3.3. Select IP that affects system design, especially I/O interfaces..........................6 1.3.4. Ensure your board design supports the Intel FPGA IP Evaluation Mode tethered mode.......................................................................................... 6 1.3.5. Review available system development tools...................................................7 1.4. Device Selection....................................................................................................7 1.4.1. Consider the available device variants.......................................................... 7 1.4.2. Estimate the required logic, memory, and multiplier density............................ 7 1.4.3. Consider vertical device migration availability and requirements.......................8 1.4.4. Review resource utilization reports of similar designs......................................8 1.4.5. Reserve device resources for future development and debugging..................... 8 1.4.6. Estimate the number of I/O pins that you require...........................................8 1.4.7. Consider the I/O pins you need to reserve for debugging................................ 9 1.4.8. Verify that the number of LVDS channels are enough......................................9 1.4.9. Verify the number of PLLs and clock routing resources.................................... 9 1.4.10. Determine the device speed grade that you require...................................... 9 1.4.11. Determine the number of images supported for the device.......................... 10 1.5. Board Design...................................................................................................... 10 1.5.1. Early Board Design...................................................................................10 1.5.2. Power Pin Connections..............................................................................13 1.5.3. Configuration Pin Connections....................................................................15 1.5.4. General I/O Pin Connections......................................................................17 1.6. I/O and Clock Planning......................................................................................... 20 1.6.1. Early Pin Planning and I/O Assignment Analysis........................................... 20 1.6.2. I/O Features and Pin Connections...............................................................21 1.6.3. Clock Planning.........................................................................................27 1.6.4. I/O Simultaneous Switching Noise..............................................................28 1.7. Design Entry....................................................................................................... 29 1.7.1. Use synchronous design practices.............................................................. 29 1.7.2. Consider the following recommendations to avoid clock signals problems:....... 30 1.7.3. Use IP cores with the parameter editor....................................................... 30 1.7.4. Review the information on dynamic reconfiguration feature........................... 30 1.7.5. Consider the Intel's recommended coding styles to achieve optimal synthesis results...................................................................................... 30 1.7.6. Enable the chip-wide reset to clear all registers if required.............................31 1.7.7. Use device architecture-specific register control signals.................................31 1.7.8. Review recommended reset architecture..................................................... 31 1.7.9. Review the synthesis options available in your synthesis tool......................... 32 ® ® Intel MAX 10 FPGA Design Guidelines Send Feedback 2 Contents 1.7.10. Consider resources available for register power-up and control signals.......... 32 1.7.11. Consider Intel's recommendations for creating design partitions................... 33 1.7.12. Perform timing budgeting and resource balancing between partitions............ 33 1.7.13. Create a design floorplan for incremental compilation partitions....................34 1.8. Design Implementation.........................................................................................34 1.8.1. Synthesis and Compilation........................................................................ 34 1.8.2. Timing Optimization and Analysis...............................................................37 1.8.3. Formal Verification................................................................................... 40 1.8.4. Power Analysis and Optimization................................................................ 40 1.9. Document Revision History for Intel MAX 10 Device Design Guidelines........................ 43 ® ® Send Feedback Intel MAX 10 FPGA Design Guidelines 3 M10-GUIDELINES | 2020.10.19 Send Feedback 1. Intel® MAX® 10 FPGA Design Guidelines 1.1. Intel® MAX® 10 FPGA Design Guidelines This application note provides a set of checklists that consist of design guidelines, recommendations, and factors to consider when you create designs using Intel® MAX® 10 FPGAs. • Use this document to help you plan the FPGA and system early in the design process, which is crucial for a successful design. • Follow Intel’s recommendations throughout the design process to achieve good results, avoid common issues, and improve your design productivity. Figure 1. Intel MAX 10 Design Flow Board Design Power Pins Planning Specifications Early Planning Design Entry Design Implementation Configuration Pins Planning Design Specifications Early Board Design Synthesis • IP Selection Planning and Compilation I/O and Clock Planning Early Pin Planning Timing Optimization Device Selection and I/O Assignment and Analysis I/O Features and Pin Connections Hierarchical Team-based Functional Timing Design Planning Simulation Clock Planning Formal Verification I/O SSN Considerations Power Analysis and Optimization 1.2. Before You Begin Before you begin planning and designing your FPGA system, familiarize yourself with the FPGA device features, and the design tools and IP that are available for the Intel MAX 10 device family. Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in ISO accordance with Intel's standard warranty, but reserves the right to make changes to any products and services 9001:2015 at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any Registered information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. 1. Intel® MAX® 10 FPGA Design Guidelines M10-GUIDELINES | 2020.10.19 1.2.1. Read through the Device Overview of the FPGA The Device Overview provides an overview of the capabilities and options available for a device family. Read through the document to familiarize yourself with the device family offerings and general features. Related Information Intel MAX 10 FPGA Device Overview 1.2.2. Estimate design requirements Create a rough estimate of the design in the following terms: • Basic functions of the product • Similar previous designs • General device requirements 1.2.3. Review available design tools Consider the available design, estimators, system builders, and verification tools. The following items are some of the available tools provided by Intel: • Intel Quartus® Prime software for design, synthesis, simulation, and programming; including integration with Platform Designer (Standard), simulation tools, and verification tools. • Platform Designer (Standard) system integration tool—next-generation tool that automatically generates interconnect logic to connect intellectual property (IP) functions and subsystems. • Mentor
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