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Vivado Design Suite User Guide: Logic Simulation (UG900)

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Vivado Design Suite User Guide: Logic Simulation (UG900) Vivado Design Suite User Guide Logic Simulation UG900 (v2018.2) June 6, 2018 Revision History The following table shows the revision history for this document. Section Revision Summary 06/06/2018 Version 2018.2 Library Mapping File (xsim.ini) Added a note supporting two init files (xsim.ini and xsim_legacy.ini) from current release. export_simulation • Updated information in export_simulation Options table. • Added Riviera Pro and Active HDL for supported simulators • Updated the argument for -lib_map_path 04/04/2018 Version 2018.1 General Updates • Updated File and Tools menu commands • Added Cadence Xcelium Simulator support Information Subprogram Call-Stack Support Added Subprogram Call-Stack support feature Table D-3: Data Types Allowed on the Added SV open array support information for DPI C-SystemVerilog Boundary Table 7-2: xelab, xvhd, and xvlog Command Added Standalone support for Vivado Simulator in the -a Options command description as a note. Logic Simulation Send Feedback 2 UG900 (v2018.2) June 6, 2018 www.xilinx.com Table of Contents Revision History . 2 Chapter 1: Logic Simulation Overview Introduction . 7 Supported Simulators . 7 Simulation Flow . 8 Language and Encryption Support . 11 Chapter 2: Preparing for Simulation Overview . 12 Using Test Benches and Stimulus Files . 12 Pointing to the Simulator Install Location . 13 Compiling Simulation Libraries . 15 Using Xilinx Simulation Libraries. 19 Using Simulation Settings . 29 Adding or Creating Simulation Source Files . 34 Generating a Netlist. 36 Chapter 3: Simulating with Third-Party Simulators Introduction . 39 Running Simulation Using Third Party Simulators with Vivado IDE . 40 Dumping SAIF for Power Analysis. 43 Dumping VCD for Power Analysis. 44 Simulating IP. 46 Using a Custom DO File During an Integrated Simulation Run. 46 Running Third-Party Simulators in Batch Mode . 47 Chapter 4: Simulating with Vivado Simulator Introduction . 49 Running the Vivado Simulator . 49 Running Functional and Timing Simulation . 67 Saving Simulation Results . 71 Distinguishing Between Multiple Simulation Runs . 71 Logic Simulation Send Feedback 3 UG900 (v2018.2) June 6, 2018 www.xilinx.com Closing a Simulation. 71 Adding a Simulation Start-up Script File. 72 Viewing Simulation Messages. 73 Using the launch_simulation Command . 75 Re-running the Simulation After Design Changes (relaunch) . 76 Using the Saved Simulator User Interface Settings . 77 Chapter 5: Analyzing Simulation Waveforms with Vivado Simulator Introduction . 79 Using Wave Configurations and Windows. 79 Opening a Previously Saved Simulation Run . 81 Understanding HDL Objects in Waveform Configurations . 82 Customizing the Waveform. 85 Controlling the Waveform Display . 92 Organizing Waveforms . 96 Analyzing Waveforms . 98 Chapter 6: Debugging a Design with Vivado Simulator Introduction . 103 Debugging at the Source Level . 103 Forcing Objects to Specific Values . 108 Power Analysis Using Vivado Simulator. 116 Using the report_drivers Tcl Command . 118 Using the Value Change Dump Feature . 119 Using the log_wave Tcl Command . 120 Cross Probing Signals in the Object, Wave, and Text Editor Windows . 121 Chapter 7: Simulating in Batch or Scripted Mode in Vivado Simulator Introduction . 126 Exporting Simulation Files and Scripts . 126 Running the Vivado Simulator in Batch Mode. 132 Elaborating and Generating a Design Snapshot, xelab . 135 Simulating the Design Snapshot, xsim . 146 Example of Running Vivado Simulator in Standalone Mode . 148 Project File (.prj) Syntax . 149 Predefined Macros. 150 Library Mapping File (xsim.ini) . 150 Running Simulation Modes . 151 Using Tcl Commands and Scripts . 154 export_simulation . 155 Logic Simulation Send Feedback 4 UG900 (v2018.2) June 6, 2018 www.xilinx.com export_ip_user_files . ..
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