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Masters Thesis: Low Power Digital Baseband Architecture for Wireless CONFIDENTIAL Low power digital baseband ar- chitecture for wireless sensor nodes Yuteng Hao Master of Science Thesis Department of Microelectronics mscconfidential Low power digital baseband architecture for wireless sensor nodes Master of Science Thesis For the degree of Master of Science in Microelectronics at Delft University of Technology Yuteng Hao June 22, 2015 Faculty of Electrical Engineering, Mathematics and Computer Science (EEMCS) · Delft University of Technology The work in this thesis was supported by Holst Centre. Their cooperation is hereby gratefully acknowledged. Copyright c Department of Microelectronics All rights reserved. Delft University of Technology Department of Department of Microelectronics The undersigned hereby certify that they have read and recommend to the Faculty of Electrical Engineering, Mathematics and Computer Science (EEMCS) for acceptance a thesis entitled Low power digital baseband architecture for wireless sensor nodes by Yuteng Hao in partial fulfillment of the requirements for the degree of Master of Science Microelectronics Dated: June 22, 2015 Supervisor(s): Dr.ir. Nick van der Meijs Dr. Christian A. Bachmann Committee member(s): Dr.ir. Gerard Janssen Dr.ir. Rene Van Leuken Dr. R.R. Venkatesha Prasad Abstract This thesis presents a digital baseband design for an upcoming wireless standards: IEEE 802.11ah. It is a branch of Wi-Fi (IEEE 802.11) standards. Compared with the previous Wi-Fi standards, this new standard has larger coverage range and consumes less energy. It is particularly suited for energy-constrained sensor applications. In contrast to the Digital Baseband (DBB)s of other Wi-Fi standards, this design consumes much less power. The basic modulation method of the system is Orthogonal Frequency Divi- sion Multiplexing (OFDM) and the detailed algorithms are explored. To prove the robustness of the system, some error tests for the system are performed. A gate-level hardware design and the synthesis netlist are also presented to prove the low-power design. Based on the synthesis results, a series of optimization is done to lower the power consumption. The DBB has been implemented in 40nm Low-power CMOS process to prove the concept. It includes the key blocks of this system. Measurement results show that the DBB for IEEE 802.11ah is suitable for low power applications. The power consumption of this DBB is around 200 - 400 µW, which is hundreds times less than that of the traditional 802.11 baseband. Keywords: IEEE 802.11ah, Digital baseband, OFDM, Low-power, Synchronizer Master of Science Thesis CONFIDENTIAL Yuteng Hao ii Yuteng Hao CONFIDENTIAL Master of Science Thesis Table of Contents Glossary xi List of Acronyms................................... xi List of Symbols................................... xii Acknowledgements xiii 1 Introduction1 1-1 Background..................................... 1 1-2 Motivations and objectives............................. 2 1-3 Thesis Overview................................... 5 2 High level modeling7 2-1 OFDM Basics.................................... 7 2-2 OFDM Frame Format................................ 10 2-3 Parameters for all the supplied cases........................ 12 2-4 Digital transmitter and receiver........................... 12 2-4-1 Convolutional encoder and Viterbi decoder................. 13 2-4-2 Interleaver and deinterleaver........................ 14 2-4-3 Modulator and demodulator........................ 15 2-4-4 Pilot inserter and remover......................... 17 2-4-5 Fast Fourier Transform........................... 17 2-4-6 Cyclic Prefix (CP) insertion and removing................. 18 2-4-7 Timing synchronization........................... 19 2-4-8 Channel estimation............................. 24 2-4-9 Oversampling................................ 27 2-5 High level simulation results............................. 28 2-5-1 Verification................................. 29 2-5-2 Floating-point simulation.......................... 29 2-5-3 Fixed-point simulation............................ 32 2-6 Summary....................................... 34 Master of Science Thesis CONFIDENTIAL Yuteng Hao iv Table of Contents 3 Hardware implementation 35 3-1 Implementation design flow............................. 35 3-2 Quantization..................................... 36 3-3 RTL Implementation................................ 37 3-3-1 Modulator and demodulator........................ 39 3-3-2 Pilot inserter and remover......................... 40 3-3-3 IFFT and FFT................................ 41 3-3-4 Cyclic Prefix Extender............................ 41 3-3-5 Synchronizer................................. 42 3-3-6 Packet buffers................................ 44 3-4 Logic synthesis.................................... 48 3-5 Summary....................................... 49 4 Simulation results and analysis 51 4-1 Synthesis results................................... 51 4-2 Power consumption................................. 53 4-3 Summary....................................... 60 5 Conclusions and future work 61 5-1 Conclusions..................................... 61 5-2 Future work..................................... 62 A The comparison of channel estimation using LS and MMSE estimators 65 B Verification for the functionality of RTL model and gate-level netlist 67 Yuteng Hao CONFIDENTIAL Master of Science Thesis List of Figures 1-1 Smart grid with an 802.11ah AP (after [3]).................... 3 1-2 Magnitude spectrum of baseband signal and high frequency signal........ 3 1-3 Digital baseband and front-end........................... 4 2-1 Frequency-Time Representative of an OFDM signal [14]............. 8 2-2 Spectrum of an FDM subcarriers.......................... 8 2-3 Spectrum of OFDM symbols with overlapping subcarriers............. 9 2-4 Architecture of the OFDM system (Transmitter and Receiver).......... 9 2-5 802.11ah PPDU frame format (bandwidth: 1 MHz) [1].............. 10 2-6 Subcarrier frequency allocation (bandwidth is 1 MHz) [1]............. 11 2-7 802.11ah PPDU frame format (bandwidth ≥ 1 MHz) [1]............. 11 2-8 Convolutional encoder (K = 7) [[1]]........................ 13 2-9 The coded bits before and after interleaving.................... 15 2-10 The constellation diagrams of BPSK and QPSK.................. 16 2-11 The constellation diagrams of 16-QAM....................... 17 2-12 The QPSK constellation diagrams with noise................... 18 2-13 The basic concept of cyclic prefix.......................... 19 2-14 Inter-symbol interference with a delayed signal (without CP)........... 19 2-15 Magnitude of short training sequence in S1G_1M................. 20 2-16 Block diagram of the auto-correlation algorithm (Equation 2-14 with N = 16). 22 2-17 Output of auto-correlation for an incoming signal with an SNR of 20 dB (S1G_1M) 23 2-18 Block diagram of the cross-correlation algorithm (S1G_1M)........... 24 2-19 Output of cross-correlation for an incoming signal with an SNR of 20 dB (S1G_1M) 24 2-20 Correlation output for an incoming signal with an SNR of 20 dB (S1G_1M)... 25 Master of Science Thesis CONFIDENTIAL Yuteng Hao vi List of Figures 2-21 Channel estimation principle [33].......................... 26 2-22 Channel frequency response for the original channel and estimated channel (over- lapping)....................................... 27 2-23 Oversampling principle............................... 28 2-24 The bit streams which can be compared to verify the modules.......... 29 2-25 Theoretical BER for BPSK, QPSK and 16-QAM................. 31 2-26 BER simulation over an AWGN channel and theoretical BER for BPSK (these two curves are overlapping )............................... 31 2-27 PER vs SNR for all the supported S1G_1M cases................. 32 2-28 Effect of timing synchronization on PER (CBW1, MCS1)............ 32 2-29 Effect of Rayleigh Fading channel (CBW1, MCS1)................ 33 2-30 Fixed-point simulation (CBW1, MCS3)...................... 34 3-1 The design flow for hardware implementation................... 36 3-2 A basic example for "dia − doa" structure..................... 38 3-3 The OFDM transmitter block diagram in RTL design............... 38 3-4 The OFDM receiver block diagram in RTL design................. 38 3-5 The circuitry used for constellation mapping (BPSK, QPSK and 16-QAM).... 39 3-6 The waveform of the signals in the modulator (BPSK, S1G_1M)......... 40 3-7 The circuitry used for constellation demapping (BPSK, QPSK and 16-QAM).. 40 3-8 The circuitry used for pilot insertion and zero padding............... 41 3-9 The circuitry used for cyclic prefix extension.................... 42 3-10 The circuitry used for removing cyclic prefix.................... 42 3-11 The circuitry designed for auto-correlation..................... 43 3-12 The circuitry designed for cross-correlation..................... 44 3-13 The circuitry of synchronization........................... 44 3-14 The waveform of the signals in the synchronizer.................. 45 3-15 Timing diagram of OFDM symbols at the transmitter............... 46 3-16 The waveform of the "fake" clock signal...................... 46 3-17 Block diagram for Ping-Pong buffer........................ 47 3-18 The waveform of signals in packet buffer at Tx.................. 48 3-19 Top level view of the RTL circuitry......................... 49 3-20 The synthesis flow.................................. 50 4-1 Cell area vs clock frequency constraints...................... 52 4-2 Power consumption over time (top level, CBW1, MCS3)............
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