DOCSLIB.ORG

A Pythonic Approach for Rapid Hardware Prototyping and Instrumentation

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
A Pythonic Approach for Rapid Hardware Prototyping and Instrumentation A Pythonic Approach for Rapid Hardware Prototyping and Instrumentation John Clow, Georgios Tzimpragos, Deeksha Dangwal, Sammy Guo, Joseph McMahan and Timothy Sherwood University of California, Santa Barbara, CA, 93106 USA Email: fjclow, gtzimpragos, deeksha, sguo, jmcmahan, [email protected] Abstract—We introduce PyRTL, a Python embedded hardware To achieve these goals, PyRTL intentionally restricts users design language that helps concisely and precisely describe to a set of reasonable digital design practices. PyRTL’s small digital hardware structures. Rather than attempt to infer a and well-defined internal core structure makes it easy to add good design via HLS, PyRTL provides a wrapper over a well- defined “core” set of primitives in a way that empowers digital new functionality that works across every design, including hardware design teaching and research. The proposed system logic transforms, static analysis, and optimizations. Features takes advantage of the programming language features of Python such as elaboration-through-execution (e.g. introspection), de- to allow interesting design patterns to be expressed succinctly, and sign and simulation without leaving Python, and the option encourage the rapid generation of tooling and transforms over to export to, or import from, common HDLs (Verilog-in via a custom intermediate representation. We describe PyRTL as a language, its core semantics, the transform generation interface, Yosys [1] and BLIF-in, Verilog-out) are also supported. More and explore its application to several different design patterns and information about PyRTL’s high level flow can be found in analysis tools. Also, we demonstrate the integration of PyRTL- Figure 1. generated hardware overlays into Xilinx PYNQ platform. The resulting system provides an almost “pure” pythonic experience for the prototyping and evaluation of FPGA-based SoCs. • RTL modules I. INTRODUCTION Yosys From Systems-on-Chip to warehouse sized computing, sys- • Scripts PyRTL IR • Instrumentation tem engineers are increasingly turning to custom and recon- • Testbench • Transforms • Hardware Design figurable hardware blocks to provide performance and energy RTL efficiency where it counts most. Traditional hardware descrip- tion languages, such as Verilog and VHDL, were developed CAD tools Analysis & Simulation more than three decades ago and are still the dominant HDLs. • System development. • Estimation of design’s area, In recent years, High-Level-Synthesis (HLS) approaches are • Reports (timing, area, etc.) latency and max clock RTL modules RTL frequency. also gaining ground, leading to the market’s expansion to • Bitstream a usership beyond traditional RTL coders to include “non- • PyRTL built-in simulator. • Hardware execution. • Commercially available experts”. However, the tremendous amount of work focusing • On-chip HW-SW co-verification simulators. on how good designs can be inferred via these methods proves that deep hardware understanding is still required, in both Fig. 1. Overview of PyRTL’s flow. cases, for the development of reasonably optimized solutions. In this paper, we introduce PyRTL. PyRTL is an open- The paper first gives an overview of the related work, source Python-based HDL aiming to enable the rapid prototyp- highlighting the similarities and differences between existing ing of complex digital hardware. PyRTL provides a collection projects and our approach. Section III describes the PyRTL of classes for pythonic RTL design, simulation, tracing, and language and its main features. In Section IV, PyRTL’s inter- testing, suitable for teaching and research. Simplicity, usability, mediate representation is presented. An instrumentation API clarity and extensibility, rather than performance or optimiza- along with a set of possible transforms over PyRTL’s core tion, are the overarching goals. are discussed in Section V. The performance of our tool At a high level, PyRTL builds the hardware structure that is quantified in Section VI. The on-board deployment and the user explicitly defines. In contrast with HLS approaches, SoC integration of PyRTL-generated designs are presented in PyRTL does not promise to take “random” high-level code and this section as well. Finally, concluding remarks are given in turn it into hardware. However, our system aims at (a) lowering Section VII. Overall, the main contributions of this paper are the barrier of entry to digital design (for both students and the following: software engineers), (b) promoting the co-design of hardware transforms and analysis with digital designs (through a simple • A Python embedded hardware design language that allows core and translation interface), and (c) ultimately allowing the use of dynamic typing, introspection, comprehensions, complex hardware design patterns to be expressed in a way and other Python features to capture reoccurring design that promotes reuse beyond just hardware blocks. patterns and facilitate extensive reusability. • A concise intermediate representation that simplifies the converted into implementable hardware. In contrast with these co-design of hardware transforms and analysis with digital approaches, PyRTL always uses a single clock domain and designs. does not contain any unsynthesizable hardware primitives (i.e., • An instrumentation API that supports transforms through bottom-up design based on the use of composable set of data an interface similar to software-like binary instrumentation structures), which is of great help to less-experienced users, toolkits. The applicability and efficiency of these methods for whom it can be very unclear why certain code can be syn- are also demonstrated across a variety of sample designs. thesized and certain code cannot. Moreover, PyRTL introduces • The integration of PyRTL-generated hardware overlays into a hardware instrumentation framework that provides methods Xilinx PYNQ (and therefore Zynq) for quick and easy SoC of walking and augmenting accelerator functionality concisely development and evaluation via Python. and efficiently (e.g. insertion of counters, probes, and other arbitrary analysis logic). II. RELATED WORK The SysPy project [6] looks at the hardware realization Traditional HDLs have a very long learning curve, even for problem from a different perspective. To bridge the gap be- experienced engineers. On the other hand, HLS approaches tween software expressions and hardware implementations, the promise to raise the level of abstraction and compile regular authors proposed a “glue software” solution between ready- C/C++ functions into logic elements. However, there is still to-use VHDL components and programmable processor soft no clear way as to how to come up with an optimized design IP cores. PHDL [7] is also aiming to enable the utilization without prior hardware engineering experience. PyRTL’s goal of available HDL components, importable from pre-existing is to provide an alternative between these two extremes libraries. Although these approaches are interesting, we do by enabling programmers to directly specify their hardware not consider them PyRTL’s counterparts, as their focus is designs in a language they already know. As expected, this is different. not the first attempt to cover this need. Chisel [2] is a Scala-based project with similar goals to III. PYRTL OVERVIEW PyRTL. Chisel is (like PyRTL) an elaborate-through-execution PyRTL is a new hardware design language based on Python. hardware design language. With support for signed types, The main motivation behind PyRTL’s design is to help the user named hierarchies of wires, and a well-designed control struc- concisely and precisely describe a digital hardware structure ture, Chisel is a powerful tool used in some great research through a set of Python classes. To achieve simplicity and clar- projects, including OpenRISC. Unlike Chisel, PyRTL has ity, PyRTL intentionally restricts users to a set of reasonable concentrated on a complete tool chain, which is useful for digital design practices. For instance, clock and reset signals instructional projects, and provides a clearly defined and are implicit, block memories are synchronous by default, there relatively easy to manipulate intermediate structure, which are no undriven or high-impedance states, and no unregistered allows rapid prototyping of hardware analysis routines. feedbacks are allowed. That way, any design expressed as valid ClaSH [3] is a hardware description embedded DSL in code always corresponds to synthesizable hardware. Moreover, Haskell. In a similar way to PyRTL, ClaSH provides an Python’s dynamic and object-oriented nature allows the user approach suitable for both combinational and synchronous se- to write introspective containers and build hardware using quential circuits, and allows the transformation of these high- common software abstractions. level descriptions to low-level synthesizable Verilog HDL. A. PyRTL Datatypes & Operators Unlike PyRTL, which is based on Python (one of the most popular languages with support for both functional and im- The primary data structure users interact with is perative style programming), in ClaSH the user has to deal WireVector. To allow users to build on their exist- with the challenges that come with functional programming. ing experience with Python, we have designed multi-bit Moreover, designs have to be statically typed (like VHDL). WireVectors to act much as a list of individual wires. This To be more specific, in PyRTL variable types do not have to allows for WireVectors to use the various
Load more

Recommended publications
  • Debugging System for Openrisc 1000- Based Systems
    Debugging System for OpenRisc 1000- based Systems Nathan Yawn [email protected] 05/12/09 Copyright (C) 2008 Nathan Yawn Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license should be included with this document. If not, the license may be obtained from www.gnu.org, or by writing to the Free Software Foundation. This document is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. History Rev Date Author Comments 1.0 20/7/2008 Nathan Yawn Initial version Contents 1.Introduction.............................................................................................................................................5 1.1.Overview.........................................................................................................................................5 1.2.Versions...........................................................................................................................................6 1.3.Stub-based methods.........................................................................................................................6 2.System Components................................................................................................................................7
    [Show full text]
  • Co-Simulation Between Cλash and Traditional Hdls
    MASTER THESIS CO-SIMULATION BETWEEN CλASH AND TRADITIONAL HDLS Author: John Verheij Faculty of Electrical Engineering, Mathematics and Computer Science (EEMCS) Computer Architecture for Embedded Systems (CAES) Exam committee: Dr. Ir. C.P.R. Baaij Dr. Ir. J. Kuper Dr. Ir. J.F. Broenink Ir. E. Molenkamp August 19, 2016 Abstract CλaSH is a functional hardware description language (HDL) developed at the CAES group of the University of Twente. CλaSH borrows both the syntax and semantics from the general-purpose functional programming language Haskell, meaning that circuit de- signers can define their circuits with regular Haskell syntax. CλaSH contains a compiler for compiling circuits to traditional hardware description languages, like VHDL, Verilog, and SystemVerilog. Currently, compiling to traditional HDLs is one-way, meaning that CλaSH has no simulation options with the traditional HDLs. Co-simulation could be used to simulate designs which are defined in multiple lan- guages. With co-simulation it should be possible to use CλaSH as a verification language (test-bench) for traditional HDLs. Furthermore, circuits defined in traditional HDLs, can be used and simulated within CλaSH. In this thesis, research is done on the co-simulation of CλaSH and traditional HDLs. Traditional hardware description languages are standardized and include an interface to communicate with foreign languages. This interface can be used to include foreign func- tions, or to make verification and co-simulation possible. Because CλaSH also has possibilities to communicate with foreign languages, through Haskell foreign function interface (FFI), it is possible to set up co-simulation. The Verilog Procedural Interface (VPI), as defined in the IEEE 1364 standard, is used to set-up the communication and to control a Verilog simulator.
    [Show full text]
  • An Open-Source Python-Based Hardware Generation, Simulation
    An Open-Source Python-Based Hardware Generation, Simulation, and Verification Framework Shunning Jiang Christopher Torng Christopher Batten School of Electrical and Computer Engineering, Cornell University, Ithaca, NY { sj634, clt67, cbatten }@cornell.edu pytest coverage.py hypothesis ABSTRACT Host Language HDL We present an overview of previously published features and work (Python) (Verilog) in progress for PyMTL, an open-source Python-based hardware generation, simulation, and verification framework that brings com- FL DUT pelling productivity benefits to hardware design and verification. CL DUT generate Verilog synth RTL DUT PyMTL provides a natural environment for multi-level modeling DUT' using method-based interfaces, features highly parametrized static Sim FPGA/ elaboration and analysis/transform passes, supports fast simulation cosim ASIC and property-based random testing in pure Python environment, Test Bench Sim and includes seamless SystemVerilog integration. Figure 1: PyMTL’s workflow – The designer iteratively refines the hardware within the host Python language, with the help from 1 INTRODUCTION pytest, coverage.py, and hypothesis. The same test bench is later There have been multiple generations of open-source hardware reused for co-simulating the generated Verilog. FL = functional generation frameworks that attempt to mitigate the increasing level; CL = cycle level; RTL = register-transfer level; DUT = design hardware design and verification complexity. These frameworks under test; DUT’ = generated DUT; Sim = simulation. use a high-level general-purpose programming language to ex- press a hardware-oriented declarative or procedural description level (RTL), along with verification and evaluation using Python- and explicitly generate a low-level HDL implementation. Our pre- based simulation and the same TB.
    [Show full text]
  • Intro to Programmable Logic and Fpgas
    CS 296-33: Intro to Programmable Logic and FPGAs ADEL EJJEH UNIVERSITY OF ILLINOIS URBANA-CHAMPAIGN © Adel Ejjeh, UIUC, 2015 2 Digital Logic • In CS 233: • Logic Gates • Build Logic Circuits • Sum of Products ?? F = (A’.B)+(B.C)+(A.C’) A B Black F Box C © Adel Ejjeh, UIUC, 2015 3 Programmable Logic Devices (PLDs) PLD PLA PAL CPLD FPGA (Programmable (Programmable (Complex PLD) (Field Prog. Logic Array) Array Logic) Gate Array) •2-level structure of •Enhanced PLAs •For large designs •Has a much larger # of AND-OR gates with reduced costs •Collection of logic blocks with programmable multiple PLDs with •Larger interconnection connections an interconnection networK structure •Largest manufacturers: Xilinx - Altera Slide taken from Prof. Chehab, American University of Beirut © Adel Ejjeh, UIUC, 2015 4 Combinational Programmable Logic Devices PLAs, CPLDs © Adel Ejjeh, UIUC, 2015 5 Programmable Logic Arrays (PLAs) • 2-level AND-OR device • Programmable connections • Used to generate SOP • Ex: 4x3 PLA Slide adapted from Prof. Chehab, American University of Beirut © Adel Ejjeh, UIUC, 2015 6 PLAs contd • O1 = I1.I2’ + I4.I3’ • O2 = I2.I3.I4’ + I4.I3’ • O3 = I1.I2’ + I2.I1’ Slide adapted from Prof. Chehab, American University of Beirut © Adel Ejjeh, UIUC, 2015 7 Programmable Array Logic (PALs) • More Versatile than PLAs • User Programmable AND array followed by fixed OR gates • Flip-flops/Buffers with feedback transforming output ports into I/O ports © Adel Ejjeh, UIUC, 2015 8 Complex PLDs (CPLD) • Programmable PLD blocks (PALs) I/O Block I/O I/O
    [Show full text]
  • Nanoelectronic Mixed-Signal System Design
    Nanoelectronic Mixed-Signal System Design Saraju P. Mohanty Saraju P. Mohanty University of North Texas, Denton. e-mail: [email protected] 1 Contents Nanoelectronic Mixed-Signal System Design ............................................... 1 Saraju P. Mohanty 1 Opportunities and Challenges of Nanoscale Technology and Systems ........................ 1 1 Introduction ..................................................................... 1 2 Mixed-Signal Circuits and Systems . .............................................. 3 2.1 Different Processors: Electrical to Mechanical ................................ 3 2.2 Analog Versus Digital Processors . .......................................... 4 2.3 Analog, Digital, Mixed-Signal Circuits and Systems . ........................ 4 2.4 Two Types of Mixed-Signal Systems . ..................................... 4 3 Nanoscale CMOS Circuit Technology . .............................................. 6 3.1 Developmental Trend . ................................................... 6 3.2 Nanoscale CMOS Alternative Device Options ................................ 6 3.3 Advantage and Disadvantages of Technology Scaling . ........................ 9 3.4 Challenges in Nanoscale Design . .......................................... 9 4 Power Consumption and Leakage Dissipation Issues in AMS-SoCs . ................... 10 4.1 Power Consumption in Various Components in AMS-SoCs . ................... 10 4.2 Power and Leakage Trend in Nanoscale Technology . ........................ 10 4.3 The Impact of Power Consumption
    [Show full text]
  • Review of FPD's Languages, Compilers, Interpreters and Tools
    ISSN 2394-7314 International Journal of Novel Research in Computer Science and Software Engineering Vol. 3, Issue 1, pp: (140-158), Month: January-April 2016, Available at: www.noveltyjournals.com Review of FPD'S Languages, Compilers, Interpreters and Tools 1Amr Rashed, 2Bedir Yousif, 3Ahmed Shaban Samra 1Higher studies Deanship, Taif university, Taif, Saudi Arabia 2Communication and Electronics Department, Faculty of engineering, Kafrelsheikh University, Egypt 3Communication and Electronics Department, Faculty of engineering, Mansoura University, Egypt Abstract: FPGAs have achieved quick acceptance, spread and growth over the past years because they can be applied to a variety of applications. Some of these applications includes: random logic, bioinformatics, video and image processing, device controllers, communication encoding, modulation, and filtering, limited size systems with RAM blocks, and many more. For example, for video and image processing application it is very difficult and time consuming to use traditional HDL languages, so it’s obligatory to search for other efficient, synthesis tools to implement your design. The question is what is the best comparable language or tool to implement desired application. Also this research is very helpful for language developers to know strength points, weakness points, ease of use and efficiency of each tool or language. This research faced many challenges one of them is that there is no complete reference of all FPGA languages and tools, also available references and guides are few and almost not good. Searching for a simple example to learn some of these tools or languages would be a time consuming. This paper represents a review study or guide of almost all PLD's languages, interpreters and tools that can be used for programming, simulating and synthesizing PLD's for analog, digital & mixed signals and systems supported with simple examples.
    [Show full text]
  • Myhdl Manual Release 0.11
    MyHDL manual Release 0.11 Jan Decaluwe April 10, 2020 Contents 1 Overview 1 2 Background information3 2.1 Prerequisites.......................................3 2.2 A small tutorial on generators.............................3 2.3 About decorators.....................................4 3 Introduction to MyHDL7 3.1 A basic MyHDL simulation...............................7 3.2 Signals and concurrency.................................8 3.3 Parameters, ports and hierarchy............................9 3.4 Terminology review................................... 11 3.5 Some remarks on MyHDL and Python........................ 12 3.6 Summary and perspective................................ 12 4 Hardware-oriented types 13 4.1 The intbv class..................................... 13 4.2 Bit indexing........................................ 14 4.3 Bit slicing......................................... 15 4.4 The modbv class..................................... 17 4.5 Unsigned and signed representation.......................... 18 5 Structural modeling 19 5.1 Introduction........................................ 19 5.2 Conditional instantiation................................ 19 5.3 Converting between lists of signals and bit vectors................. 21 5.4 Inferring the list of instances.............................. 22 6 RTL modeling 23 6.1 Introduction........................................ 23 6.2 Combinatorial logic................................... 23 6.3 Sequential logic...................................... 25 6.4 Finite State Machine modeling............................
    [Show full text]
  • Small Soft Core up Inventory ©2019 James Brakefield Opencore and Other Soft Core Processors Reverse-U16 A.T
    tool pip _uP_all_soft opencores or style / data inst repor com LUTs blk F tool MIPS clks/ KIPS ven src #src fltg max max byte adr # start last secondary web status author FPGA top file chai e note worthy comments doc SOC date LUT? # inst # folder prmary link clone size size ter ents ALUT mults ram max ver /inst inst /LUT dor code files pt Hav'd dat inst adrs mod reg year revis link n len Small soft core uP Inventory ©2019 James Brakefield Opencore and other soft core processors reverse-u16 https://github.com/programmerby/ReVerSE-U16stable A.T. Z80 8 8 cylcone-4 James Brakefield11224 4 60 ## 14.7 0.33 4.0 X Y vhdl 29 zxpoly Y yes N N 64K 64K Y 2015 SOC project using T80, HDMI generatorretro Z80 based on T80 by Daniel Wallner copyblaze https://opencores.org/project,copyblazestable Abdallah ElIbrahimi picoBlaze 8 18 kintex-7-3 James Brakefieldmissing block622 ROM6 217 ## 14.7 0.33 2.0 57.5 IX vhdl 16 cp_copyblazeY asm N 256 2K Y 2011 2016 wishbone extras sap https://opencores.org/project,sapstable Ahmed Shahein accum 8 8 kintex-7-3 James Brakefieldno LUT RAM48 or block6 RAM 200 ## 14.7 0.10 4.0 104.2 X vhdl 15 mp_struct N 16 16 Y 5 2012 2017 https://shirishkoirala.blogspot.com/2017/01/sap-1simple-as-possible-1-computer.htmlSimple as Possible Computer from Malvinohttps://www.youtube.com/watch?v=prpyEFxZCMw & Brown "Digital computer electronics" blue https://opencores.org/project,bluestable Al Williams accum 16 16 spartan-3-5 James Brakefieldremoved clock1025 constraint4 63 ## 14.7 0.67 1.0 41.1 X verilog 16 topbox web N 4K 4K N 16 2 2009
    [Show full text]
  • UCLA Electronic Theses and Dissertations
    UCLA UCLA Electronic Theses and Dissertations Title Minimizing Leakage Energy in FPGAs Using Intentional Post-Silicon Device Aging Permalink https://escholarship.org/uc/item/75h4m6qb Author Wei, Sheng Publication Date 2013 Peer reviewed|Thesis/dissertation eScholarship.org Powered by the California Digital Library University of California University of California Los Angeles Minimizing Leakage Energy in FPGAs Using Intentional Post-Silicon Device Aging A thesis submitted in partial satisfaction of the requirements for the degree Master of Science in Computer Science by Sheng Wei 2013 c Copyright by Sheng Wei 2013 Abstract of the Thesis Minimizing Leakage Energy in FPGAs Using Intentional Post-Silicon Device Aging by Sheng Wei Master of Science in Computer Science University of California, Los Angeles, 2013 Professor Miodrag Potkonjak, Chair The presence of process variation (PV) in deep submicron technologies has be- come a major concern for energy optimization attempts on FPGAs. We develop a negative bias temperature instability (NBTI) aging-based post-silicon leakage energy optimization scheme that stresses the components that are not used or are off the critical paths to reduce the total leakage energy consumption. Further- more, we obtain the input vectors for aging by formulating the aging objectives into a satisfiability (SAT) problem. We synthesize the low leakage energy designs on Xilinx Spartan6 FPGA and evaluate the leakage energy savings on a set of ITC99 and Opencores benchmarks. ii The thesis of Sheng Wei is approved. Jason Cong Milos Ercegovac Miodrag Potkonjak, Committee Chair University of California, Los Angeles 2013 iii Table of Contents 1 Introduction :::::::::::::::::::::::::::::::: 1 2 Related Work ::::::::::::::::::::::::::::::: 7 2.1 Process Variation .
    [Show full text]
  • Evaluation of Synthesizable CPU Cores
    Evaluation of synthesizable CPU cores DANIEL MATTSSON MARCUS CHRISTENSSON Maste r ' s Thesis Com p u t e r Science an d Eng i n ee r i n g Pro g r a m CHALMERS UNIVERSITY OF TECHNOLOGY Depart men t of Computer Engineering Gothe n bu r g 20 0 4 All rights reserved. This publication is protected by law in accordance with “Lagen om Upphovsrätt, 1960:729”. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise, without the prior permission of the authors. Daniel Mattsson and Marcus Christensson, Gothenburg 2004. Evaluation of synthesizable CPU cores Abstract The three synthesizable processors: LEON2 from Gaisler Research, MicroBlaze from Xilinx, and OpenRISC 1200 from OpenCores are evaluated and discussed. Performance in terms of benchmark results and area resource usage is measured. Different aspects like usability and configurability are also reviewed. Three configurations for each of the processors are defined and evaluated: the comparable configuration, the performance optimized configuration and the area optimized configuration. For each of the configurations three benchmarks are executed: the Dhrystone 2.1 benchmark, the Stanford benchmark suite and a typical control application run as a benchmark. A detailed analysis of the three processors and their development tools is presented. The three benchmarks are described and motivated. Conclusions and results in terms of benchmark results, performance per clock cycle and performance per area unit are discussed and presented. Sammanfattning De tre syntetiserbara processorerna: LEON2 från Gaisler Research, MicroBlaze från Xilinx och OpenRISC 1200 från OpenCores utvärderas och diskuteras.
    [Show full text]
  • Towards Higher-Level Synthesis and Co-Design with Python
    Towards Higher-Level Synthesis and Co-design with Python Alexandre Quenon Vitor Ramos Gomes da Silva [email protected] [email protected] University of Mons University of Mons Mons, Belgium Mons, Belgium ABSTRACT In this paper, we promote the idea to go further in the concept of Several methods have arisen to fasten the hardware design process. high-level synthesis and co-design thanks to the Python program- Among them, the high-level synthesis (HLS), i.e., the use of a higher- ming language. We believe that making hardware and software level programming language than the usual Verilog or VHDL to designers work closer will fasten production and generate inno- create an implementation of a register transfer level (RTL). In this vation. We start by reviewing shortly the existing frameworks for paper, the direction towards even higher-level synthesis is promoted HLS, as well as higher-level HDLs, in section2. Then, in section3, with the use of Python as a high-level language/interface. Existing we focus on Python and propose strategies of hardware accelera- HLS frameworks and high-level hardware description languages tion to use this high-level language directly on an FPGA. Section4 are reviewed, then strategies to use Python code directly on the summarizes the main ideas and draws the conclusions. hardware are proposed. This brings the power of scientific high- level computation libraries of Python to the hardware design, which 2 A SHORT OVERVIEW OF HIGH-LEVEL we believe is the ultimate goal of HLS. SYNTHESIS FRAMEWORKS AND HARDWARE DESCRIPTION LANGUAGES KEYWORDS On the one hand, many high-level hardware description languages FPGA, framework, hardware description language (HDL), high- have been designed for more than twenty years.
    [Show full text]
  • Wesley New, FPGA Toolflows, Casper and Beyond
    FPGA Tool-flows: CASPER and Beyond Wesley New SKA-SA [email protected] Who am I? • SKA-SA • DBE Team - Digital Back End • Real-time data processing • Use FPGA based hardware • ROACH Board • CASPER Collaboration ! ! Aims • Provide and overview of FPGA technologies • Introduce the CASPER Collaboration • Examine the CASPER FPGA Design-flow • Introductions to the tutorials • Discuss the future of FPGA design-flows and how CASPER and SKA can take advantage of these ! ! Background: FPGAs • FPGA - Field Programmable Gate Array • Effectively a reconfigurable semiconductor • Consists of Logic Elements and Interconnects • Well suited to parallel DSP computing • Contain Hard Cores • Getting progressively more complex • Design for FPGAs using Hardware Description Languages (HDL) Verilog and VHDL • There is a move towards higher-level design • CPU, GPU, FPGA, ASIC ! ! ! FPGA: Logic and Interconnects FPGA Vendors • 2 Major players, Xilinx and Altera plus a few smaller ones • Each provide there own software for designing for their FPGAs • Xilinx - ISE/Vivado • Altera - Quartus • Both offer plug-ins for Simulink to take advantage of block diagram style design and simulation • Complexities of porting designs between vendors • IP specific to a vendor ! HDL (HW Description Lang) • 2 Major languages Verilog and VHDL • Verilog more of a C syntax • HDL use the event-driven methodology • Generally values of registers change on the edges of clocks ! ! CPU v GPU v FPGA v ASIC • Tradeoffs, tradeoffs, tradeoffs • ASICs, Long time to develop, hard to make changes, high NRE costs, run at a higher speed • FPGAs, Short development time, expensive per unit, bad at floating-point, highly reconfigurable • GPU, Easier to design for, good at floating-point, high power consumption • CPU, very general purpose, easy to develop for, lower performance ! ! FPGA vs ASIC Cost Per Unit HDL vs Traditions SW • HDL is very susceptible to bad coding • This can make designs use more power and resources • The way of thinking when writing in an HDL is very different to software.
    [Show full text]