Digital Electronics 2: Introduction

Martin Schoeberl

Technical University of Denmark Embedded Systems Engineering

February 4, 2021

1 / 68 Overview

I Remote teaching and learning I Motivation and the digital abstraction I Course organization I Languages for digital hardware design I A first round of Chisel I Tools and tool setup I Lab: a hardware “Hello World”

2 / 68 Remote Learning

I First: this is all new for the most of us I We need to be patient with each other I We should use Slack for quicker communication I Zoom for lecturing and lab: you are already there I Please have your camera on I Please mute your mic when not talking I Some nice features I You can raise your hand I You can ask questions with the mic or on chat I Everyone can share their screen or an individual window

3 / 68 Lab/Exercise Organization

I Everyone at DTU can use the professional version of Zoom

I http://dtudk.zoom.us/signin I You can also use Zoom for your group work I Zoom will also be used for the supervised lab I We will keep this Zoom meeting running with breakout rooms I Schedule a TA for help with Slack I You can also schedule a Zoom meeting with me at other times I This is a chance to learn how to collaborate remotely I This will be part of your future work as an engineer anyway I This experiment might change how we teach in the future

4 / 68 Lab Work

I We will stick to the plan of a working Vending Machine I At the end it shall run in your FPGA board I I am a big fan of running stuff in real hardware I Demo your work to a TA via the camera I I know many groups have only one physical FPGA board I A lot can be done in simulation I I developed a simulation of the Basys3 board (during last lockdown) I I assume you will find a solution for file sharing I GitHub is a popular one for source code I Can also be used if you plan to write your report in LaTeX

5 / 68 Questions?

I On lectures I On the group/lab work

6 / 68 A BIG Chip

I https://singularityhub.com/2019/08/26/ this-giant-ai-chip-is-the-size-of-an-ipad-and-holds-1-2-trillion-transistors/ I 1.2 × 1012 transistors I If you design 1 gate (= 4 transistors) per second I It takes you 10 thousand years! I This calls for some abstraction

7 / 68 Digital Systems are Everywhere

I Digital systems are all over in our live I No more analog media I CD, mobile phone, TV, DVD,... all digital now I Analog circuits only at the edge I The rest is processed in digital I If performance allows, functions are moved to software I But processor speedup has slowed down I Algorithms are moved back into hardware

8 / 68 FPGAs in the Cloud

I High performance algorithm in an FPGA I An FPGA in the cloud I Intel offers FPGAs for servers I There was some reason why Intel bought Altera I And why AMD will buy Xilinx I We need digital designers to make this work I A good time to be a digital designer

9 / 68 The Digital Abstraction

I Just two values: 0 and 1, a or low and hight b AND logic I Represented as voltage c OR I Digital signals tolerate noise I Digital Systems are simple, just: D Q I Combinational circuits and I Registers clock

10 / 68 Hardware Design in DK

I Demant (former Oticon) I WSAudiology (former Widex) I GN ReSound I Microsemi I Intel (former Altera) Denmark I SyoSil I Comcores I Synopsys I Napatech I Teledyn I probably some more... I I They are all hiring

11 / 68 Example Design from Microsemi DK

A picture of the board with the $50k Xilinx FPGA. This is a new board and is developed for ASIC prototyping in order to do pre-silicon validation as well as SW development. We have on the board currently mapped our current project: 8port industrial gigabit Ethernet switch with full TSN, CPU system ARM A7 with DDR, USB, PCIe and hardware security engines (SHA, AES) for secure boot of Linux and on the fly DRAM encryption. We scale and map all the digital logic to the FPGA.

12 / 68 Digital Design within an EE Master

I Not an obvious choice, as there is no specialization in digital systems I Select some of the following courses I 02155: Computer Architecture and Engineering I 02203: Design of Digital Systems I 02211: Advanced Computer Architecture I 02205: VLSI Design I 02217: Design of Arithmetic Processors I 02204: Design of Asynchronous Circuits I 02209: Test of Digital Systems

13 / 68 Computer Engineering Education at DTU

I On the border between hardware and software I Very well payed jobs :-) I Not an easy choice at DTU as well I No BSc available I Between EE and CS I Start with Bsc. in EE I Specialization in Indlejrede systemer og programmering I 02155: Computer Architecture and Engineering I 02105: Algoritmer og datastrukturer I Continue as MSc. in Computer Science and Engineering I Specialization in I Digital Systems I Embedded and Distributed Systems

14 / 68 Web Resources

I DTU Learn I Vending machine document I Project report hand in I Course website I General information, starting point I Lab website I Lab material on GitHub I Chisel book website I Download the free PDF

15 / 68 Organization and Workload

I Usually 2 hours lectures and 2 hours supervised lab I 5 ECTS is equivalent to 9 hours per week I That means 5 hours work on your own I Do some reading, prepare for the lecture and lab I Get the tools installed on your laptop I You have an FPGA board, experiment with it I You will learn a lot in this course, it will make you a better: I engineer I hardware designer I programmer, and I computer user in general I Try to have fun with building stuff that is real!

16 / 68 Communication and Getting Help

I Several sources of information: I The Internet, Google, and Stackoverflow I Your fellow students (e.g., via Slack) I The TAs: Kasper and Tjark I Me I We will use Slack for easy communication (if ok for you) I https://de2021.slack.com/ I You can always just (virtually) knock on my door or shoot me an email I There is also anonymous feedback

17 / 68 Cheating and Plagiarism

I It is ok and good practice to discuss problems and solutions with your fellow students I But you need to hand in your own solution I Copying stuff or offering stuff for copying is cheating I Copying material from somewhere is plagiarism and copyright violation I Cheating is handled quite rigorous at DTU, you might get expelled I Using source code control (GitHub) is good practice I However, keep it private. Otherwise you might contribute to cheating

18 / 68 This is an Open-Access/Open-Source Course

I Almost all material is public visible I Slides are open access I Lab material is open access I Hosted on GitHub I You can contribute with a pull request I Becoming an author of this course :-) I The Chisel book is freely available

19 / 68 Lab Work

I Some paper and pencil exercises I Most work on designing digital circuits with a hardware description language I Builds up to the final project: a vending machine I The vending machine and the report are graded

20 / 68 A Vending Machine from 1952

Source: Minnesota Historical Society, CC BY-SA 2.0 21 / 68 The Vending Machine

I Final project is a vending machine I Inputs: coins, buy I Display: price and current amount I Output: release can or error I Small challenge to multiplex the display I State machine with data path is the brain of the VM I Will be guided step by step over several weeks I More details next week I VM in hardware versus VM in software I This is an exercise that you can solve with reasonable effort

22 / 68 Motivating Example for Chisel: Lipsi: Probably the Smallest Processor in the World

I Tiny processor I Simple instruction set I Shall be small I Around 200 logic cells, one FPGA memory block I Hardware described in Chisel I Available at https://github.com/schoeberl/lipsi I Usage I Utility processor for small stuff I Could be used for your vending machine I In teaching for introduction to computer architecture I The design took place on the island Lipsi

23 / 68 The Design of Lipsi on Lipsi

24 / 68 Lipsi Implementation

I Hardware described in Chisel I Tester in Chisel I Assembler in Scala I Core case statement about 20 lines I Reference design of Lipsi as software simulator in Scala I Testing: I Self testing assembler programs I Comparing hardware with a software simulator I All in a single programming language! I All in a single program I How much work is this?

25 / 68 Chisel is Productive

I All coded and tested in less than 14 hours!

I The hardware in Chisel I Assembler in Scala I Some assembler programs (blinking LED) I Simulation in Scala I Two testers

I BUT, this does not include the design (done on paper)

26 / 68 Motivating Example: Lipsi, a Tiny Processor

I Show in IntelliJ (if beamer allows)

27 / 68 The Slides are Online

I http://www2.imm.dtu.dk/courses/02139/ I https://github.com/schoeberl/chisel-book/tree/ master/slides

28 / 68 20 Minutes Break

I An active break I In Engineering we often use drawings for communication I How can we do this interactive in home office? I Use your smartphone with Zoom! I Break work: build your own smartphone camera stand

29 / 68 Why Chisel Instead of VHDL/Verilog/SystemVerilog?

I Company O does Verilog, company W does VHDL I Why Chisel? I We learn principles of digital design, not tools I We pick a language that is modern and productive I When knowing principles, switching the language is a matter of a week I You are the future engineers and shall learn new tools I You may then bring Chisel into the company

30 / 68 More on Chisel Success Stories

I Last year at CCC 2020 in silicon valley I 90 participants I More than 30 different chip companies present I Several companies are looking into Chisel I IBM did an open-source PowerPC I SiFive is a RISC-V startup success I High productivity with Chisel I Open-source Rocket chip I Esperanto uses the BOOM processor in Chisel I Google did a machine learning processor I Intel is looking at Chisel I Chisel is open-source, if there is a bug you can fix it I You can even contribute to the Chisel ecosystem :-)

31 / 68 Introduction to Chisel

I Get an idea what Chisel is I Will show you code snippets I Basic hardware constructs in Chisel I Pointers to more information I Have your first Chisel design running in an FPGA! I From 0 to 100 in one afternoon

32 / 68 Chisel

I A hardware construction language I Constructing Hardware In a Scala Embedded Language I If it compiles, it is synthesisable hardware I Say goodby to your unintended latches I Chisel is not a high-level synthesis language I Single source for two targets I Cycle accurate simulation (testing) I Verilog for synthesis I Embedded in Scala I Full power of Scala available I But to start with, no Scala knowledge needed I Developed at UC Berkeley

33 / 68 The C Language Family

C

Verilog C++ Java C#

SystemVerilog SystemC Scala

Chisel

34 / 68 Other Language Families

Algol 68 Python Ada MyHDL VHDL

35 / 68 Some Notes on Scala

I Object oriented I Functional I Strongly typed I With very good type inference I Could be seen as Java++ I Compiled to the JVM I Good Java interoperability I Many libraries available I You can write your testing code in Java

36 / 68 Chisel vs. Scala

I A Chisel hardware description is a Scala program I Chisel is a Scala library I When the program is executed it generates hardware I Chisel is a so-called embedded domain-specific language

37 / 68 A Small Language

I Chisel is a small language I On purpose I Not many constructs to remember I The Chisel Cheatsheet fits on two pages I The power comes with Scala for circuit generators I With Scala, Chisel can grow with you

38 / 68 Tool Flow for Chisel Defined Hardware

chisel3.lib Hello.scala scala.lib

scalac

Hello.class

Chisel JVM

FIRRTL Hello.fir JVM Chisel Tester JVM

Verilog Treadle Emitter JVM JVM

good/bad Hello.vcd Hello.v

GTKWave Circuit Synthesis

Hello.bit

39 / 68 Signal Types

I All types in hardware are a collection of bits I The base type in Chisel is Bits I UInt represents an unsigned integer I SInt represents a signed integer (in two’s complement)

Bits(8.W) UInt(8.W) SInt(10.W)

40 / 68 Number of Bits: n.W

I A collection of bits has a width I The width is the number of bits I Is written as number followed by .W I Following example shows the width of n

n.W Bits(n.W)

41 / 68 Constants

I Constants can represent signed or unsigned numbers I We use .U and .S to distinguish

0.U// definesa UInt constant of0 -3.S// definesa SInt constant of -3

I Constants can also be specified with a width

3.U(4.W)// An 4-bit constant of3

42 / 68 Hexadecimal and Binary Representation

I We can specify constants with a different base I May come handy sometimes

"hff".U// hexadecimal representation of 255 "o377".U// octal representation of 255 "b1111_1111".U// binary representation of 255

43 / 68 Boolean Values

I Type for logical values I Can be true or false I Almost exchangeable with UInt(1.W) I Sometimes a signal, such as valid, may be better represented by a Boolean type

Bool() true.B false.B

44 / 68 Combinational Circuits

I Chisel uses Boolean operators, similar to C or Java I & is the AND operator and | is the OR operator I The following code is the same as the schematics I val logic gives the circuit/expression the name logic I That name can be used in following expressions

a b AND logic c OR

val logic=(a&b)|c

45 / 68 Standard Logic Operations

val and=a&b// bitwise and val or=a|b// bitwise or val xor=aˆb// bitwise xor val not =˜a// bitwise negation

I Note that we do not need to define the width of the values I Note also that this is hardware I All expressions are evaluated in parallel I Order does not matter

46 / 68 Arithmetic Operations

I Same as in Java or C I The width of the result is automatically computed I E.g., the width of the multiplication is the sum of the width of a and the width of b

val add=a+b// addition val sub=a-b// subtraction val neg = -a// negate val mul=a*b// multiplication val div=a/b// division val mod=a%b// modulo operation

47 / 68 Wires

I A signal (or wire) can be first defined I And later assigned an expression with :=

valw = Wire(UInt())

w := a & b

48 / 68 Chisel Defined Hardware Operators

Operator Description Data types */% multiplication, division, modulus UInt, SInt + - addition, subtraction UInt, SInt === =/= equal, not equal UInt, SInt, returns Bool > >= < <= comparison UInt, SInt, returns Bool << >> shift left, shift right (sign extend on SInt) UInt, SInt ˜ NOT UInt, SInt, Bool & | ˆ AND, OR, XOR UInt, SInt, Bool ! logical NOT Bool && || logical AND, OR Bool

49 / 68 Subfields and Concatenation

A single bit can be extracted as follows: val sign = x(31)

A subfield can be extracted from end to start position: val lowByte = largeWord(7, 0)

Bit fields are concatenated with Cat: val word = Cat(highByte, lowByte)

50 / 68 A Multiplexer sel

a y b

I A Multiplexer selects between alternatives I So common that Chisel provides a construct for it I Selects a when sel is true.B otherwise b

val result = Mux(sel, a, b)

51 / 68 Conditional Update

I With when we can express a conditional update I The resulting circuit is a multiplexer I In contrast to the Mux component, we can have several assignments in the when block I The rule is the the last enabled assignment counts I Here the order of statements has a meaning

valw = Wire(UInt())

w := 0.U when (cond) { w := 3.U }

52 / 68 The World of Combinational Logic

I With the shown operations (logic, arithmetic, Mux) all possible combinational circuits can be described I Even the Mux is already syntactic sugar I A Mux is basically: (a & sel) | (b & !sel) I But Chisel provides further constructs for more elegant description of circuits I Stay tuned!

53 / 68 Register

I A register is a collection of flip-flops I Updated on the rising edge of the clock I May be set to a value on reset I Clock and reset are implicitly connected to the register I A register can be any Chisel type that can be represented as a collection of bits

54 / 68 A Register with Reset reset

0 D Q q d

clock

55 / 68 A Register with Reset

Following code defines an 8-bit register, initialized with 0 at reset: val reg = RegInit(0.U(8.W))

An input is connected to the register with the := update operator and the output of the register can be used just with the name in an expression: reg := d valq = reg

56 / 68 Hello World in Chisel

class Hello extends Module{ val io = IO(new Bundle { val led = Output(UInt(1.W)) }) valCNT_MAX = (50000000 / 2 - 1).U;

val cntReg = RegInit(0.U(32.W)) val blkReg = RegInit(0.U(1.W))

cntReg := cntReg + 1.U when(cntReg === CNT_MAX) { cntReg := 0.U blkReg := ˜blkReg } io.led := blkReg }

57 / 68 Chisel is a Hardware Construction Language

I The code I showed you looks much like Java code I But it is not a program in the usual sense I It represents a circuit I The “program” constructs the circuit I All statements are “executed” in parallel I Statement order has mostly no meaning

58 / 68 Free Tools for Chisel and FPGA Design

I Java OpenJDK 8 already installed for Java course I sbt, the Scala (and Java) build tool I IntelliJ (the free Community version) I GTKWave I Vivado WebPACK already installed from DE1 I Nice to have: I make, git

59 / 68 Tool Setup for Different OSs

I Windows I Use the installers from the websites I macOS I brew install sbt I For the rest, use the installer from the websites I Use an Ubuntu VM to run Vivado I Linux/Ubuntu I sudo apt install openjdk-8-jdk git make gtkwave I Install sbt, see https://github.com/schoeberl/ chisel-lab/blob/master/Setup.md I IntelliJ as from the website I If setup fails, we have you covered with a Virtual Machine

60 / 68 Virtual Machine Setup for Chisel

I Ubuntu based I Ubuntu VM with Vivado uid: de2lab, pwd: de2lab I But this is VERY large (40 GB for the .zip file) I Ubuntu VM with Quartus uid: patmos, pwd: patmos I Use the VMWare Workstation Player (free for Linux and Windows) I Use payed VMWare Fusion for macOS

61 / 68 An IDE for Chisel

I IntelliJ I Scala plugin I For IntelliJ: File - New - Project from Existing Sources..., open build.sbt I Show it (down to the Basys3)

62 / 68 A Chisel Book

I Available in open access (as PDF) I Optimized for reading on a tablet (size, hyper links) I Amazon can do the printout

63 / 68 Further Information

I https://www.chisel-lang.org/ I https: //github.com/freechipsproject/chisel-cheatsheet/ releases/latest/download/chisel_cheatsheet.pdf I https://github.com/ucb-bar/chisel-tutorial I https://github.com/ucb-bar/generator-bootcamp I http://groups.google.com/group/chisel-users I https://github.com/schoeberl/chisel-book

64 / 68 Lab Time: Hello World in Chisel

I Get a blinking LED working on your FPGA board I Clone or download the repository from: I https://github.com/schoeberl/chisel-lab I Follow the instructions from the lab page I Start IntelliJ and follow the instructions from the lab page I sbt run I Create a Vivado project I Synthesize with the Play button I Configure the FPGA with the Programmer button I You have your first Chisel design running in an FPGA!

65 / 68 Change the Design

I Use IntelliJ, gedit, or the editor you like most I Source is in .../src/main/scala/Hello.scala I Change blinking frequency I Rerun the example I Optional: I Change to an asymmetric blinking, e.g., 200 ms on every second

66 / 68 Summary

I The world is digital I Processors do not get much faster – we need to design custom hardware I We need a modern language for hardware/systems design for efficient/fast development I Chisel builds on the power of object-oriented and functional Scala

67 / 68 Let’s have a Chat

I I will put you in random breakout rooms I Step in to chat, answer questions I Just a few minutes, then is lab time

68 / 68