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Realtek Gigabit Ethernet Media Access Controller with Power Management Rtl8169 1

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Realtek Gigabit Ethernet Media Access Controller with Power Management Rtl8169 1 RTL8169 REALTEK GIGABIT ETHERNET MEDIA ACCESS CONTROLLER WITH POWER MANAGEMENT RTL8169 1. Features........................................................................ 2 8.2.1 Target Read................................................... 37 2. General Description.................................................... 3 8.2.2 Target Write.................................................. 38 3. Block Diagram............................................................. 4 8.2.3 Master Read.................................................. 38 4. Pin Assignments .......................................................... 5 8.2.4 Master Write................................................. 39 5. Pin Description............................................................ 6 8.2.5 Configuration Access ................................... 40 5.1 Power Management/Isolation Interface ................. 6 8.3 Packet Buffering .................................................. 40 5.2 PCI Interface .......................................................... 7 8.3.1 Transmit Buffer Manager ............................. 40 5.3 FLASH/BootPROM/EEPROM/MII Interface ....... 9 8.3.2 Receive Buffer Manager............................... 40 5.4 LED Interface....................................................... 10 8.3.3 Packet Recognition....................................... 40 5.5 GMII, TBI, PHY CP ............................................ 10 8.4 PCI Configuration Space Table............................ 41 5.6 Clock and NC Pins............................................... 12 8.5 PCI Configuration Space Functions..................... 42 5.7 Power Pins ........................................................... 12 8.6 Default Value After Power-on (RSTB Asserted). 46 6. Register Descriptions................................................ 13 8.7 Power Management functions.............................. 47 6.1 DTCCR: Dump Tally Counter Command............ 15 8.8 Vital Product Data (VPD) .................................... 49 6.2 FLASH: Flash Memory Read/Write .................... 16 9. Functional Description ............................................. 50 6.3 ERSR: Early Rx Status......................................... 16 9.1 Transmit & Receive Operations........................... 50 6.4 Command............................................................. 17 9.1.1 Transmit........................................................ 50 6.5 TPPoll: Transmit Priority Polling......................... 17 9.1.2 Receive......................................................... 55 6.6 Interrupt Mask...................................................... 18 9.2 Loopback Operation............................................. 58 6.7 Interrupt Status..................................................... 19 9.3 Collision............................................................... 58 6.8 Transmit Configuration........................................ 20 9.4 Flow Control........................................................ 58 6.9 Receive Configuration ......................................... 21 9.4.1. Control Frame Transmission ....................... 58 6.10 9346CR: 93C46 (93C56) Command.................. 23 9.4.2. Control Frame Reception ............................ 58 6.11 CONFIG 0.......................................................... 23 9.5 Memory Functions ............................................... 59 6.12 CONFIG 1.......................................................... 24 9.5.1 Memory Read Line (MRL) .......................... 59 6.13 CONFIG 2.......................................................... 25 9.5.2 Memory Read Multiple (MRM)................... 59 6.14 CONFIG 3.......................................................... 25 9.5.3 Memory Write and Invalidate (MWI) .......... 60 6.15 CONFIG 4.......................................................... 26 9.5.4 Dual Address Cycle (DAC).......................... 60 6.16 CONFIG 5.......................................................... 27 9.6 LED Functions..................................................... 61 6.17 Multiple Interrupt Select .................................... 28 9.6.1 Link Monitor ................................................ 61 6.18 PHYAR: PHY Access ........................................ 28 9.6.2 Rx LED ........................................................ 61 6.19 TBICSR: Ten Bit Interface Control and Status.. 28 9.6.3 Tx LED......................................................... 62 6.20 TBI_ANAR: TBI Auto-Negotiation Advertisement .. 29 9.6.4 Tx/Rx LED................................................... 62 6.21 TBI_LPAR: TBI Auto-Negotiation Link Partner Ability ....... 29 9.6.5 LINK/ACT LED........................................... 63 6.22 PHYStatus: PHY(GMII or TBI) Status.............. 30 9.7 Physical Layer Interfaces..................................... 64 6.23 RMS: Receive (Rx) Packet Maximum Size ....... 30 9.7.1 Media Independent Interface (MII).............. 64 6.24 C+CR: C+ Command......................................... 31 9.7.2 Gigabit Media Independent Interface (GMII) ...... 64 6.25 RDSAR: Receive Descriptor Start Address....... 31 9.7.3 Ten Bit Interface (TBI)................................. 64 6.26 ETThR: Early Transmit Threshold..................... 31 9.7.4 MII/GMII Management Interface................. 64 6.27 Function Event ................................................... 32 10. Application Diagrams............................................. 65 6.28 Function Event Mask ......................................... 32 10.1 10/100/1000Base-T Application........................ 65 6.29 Function Preset State.......................................... 33 10.2 1000Base-X Application.................................... 65 6.30 Function Force Event......................................... 33 11. Electrical Characteristics ....................................... 66 7. EEPROM (93C46 or 93C56) Contents ................... 34 11.1 Temperature Limit Ratings................................. 66 7.1 EEPROM Registers.............................................. 35 11.2 DC Characteristics ............................................. 66 7.2 EEPROM Power Management Registers............. 35 11.3 AC Characteristics ............................................. 67 8. PCI Configuration Space Registers......................... 36 11.3.1 FLASH/BOOT ROM Timing..................... 67 8.1 PCI Bus Interface................................................. 36 11.3.2 Serial EEPROM Interface Timing.............. 69 8.1.1 Byte Ordering ............................................... 36 11.3.3 PCI Bus Operation Timing ......................... 70 8.1.2 Interrupt Control........................................... 36 11.3.4 MII Timing ................................................. 87 8.1.3 Latency Timer............................................... 36 11.3.5 GMII Timing .............................................. 89 8.1.4 64-Bit Data Operation .................................. 37 11.3.6 TBI Timing ................................................. 90 8.1.5 64-Bit Addressing......................................... 37 12. Mechanical Dimensions.......................................... 91 8.2 Bus Operation ...................................................... 37 2002/03/27 Rev.1.21 1 RTL8169 1. Features 208 pin QFP Supports Wake-On-LAN function and remote wake-up Supports descriptor-based buffer management (Magic Packet*, LinkChg and Microsoft® wake-up Supports Microsoft* NDIS5 Checksum Offloads (IP, frame) TCP, UDP), and Largesend Offload Supports 4 Wake-On-LAN (WOL) signals (active high, Supports IEEE 802.1Q VLAN tagging active low, positive pulse, and negative pulse) Supports Transmit (Tx) Priority Queue for QoS, CoS Supports auxiliary power-on internal reset, to be ready applications for remote wake-up when main power still remains off Supports major Tally Counters Supports auxiliary power auto-detect, and sets the 10Mbps, 100Mbps, and 1000Mbps operation at related capability of power management registers in PCI MII/GMII, and 1000Mbps at TBI interfaces configuration space Supports 10Mbps, 100Mbps, and 1000Mbps N-way Advanced power saving mode when LAN function or Auto-negotiation operation wakeup function is not used PCI local bus single-chip Fast Ethernet controller 3.3V and 1.8V power supplies needed Compliant to PCI Revision 2.2 5V tolerant I/Os Supports both Little-Endian and Big-Endian Includes a programmable, PCI burst size and early Supports 16.75MHz-66MHz PCI clock Tx/Rx threshold Supports both 32-bit and 64-bit PCI bus Supports a 32-bit general-purpose timer with the Supports PCI target fast back-to-back transaction external PCI clock as clock source, to generate Supports Memory Read Line, Memory Read timer-interrupt Multiple, Memory Write and Invalidate, and Contains two large independent transmit (8KB) and Dual Address Cycle receive (48KB) FIFO devices Provides PCI bus master data transfers and PCI Uses 93C46 (64*16-bit EEPROM) or 93C56 memory space or I/O space mapped data (128*16-bit EEPROM) to store resource configuration, transfers of the RTL8169 operational registers ID parameter, and VPD data. The 93C56 can also be Supports PCI VPD (Vital Product Data) used to store the CIS data structure for CardBus Supports ACPI, PCI power management applications Supports optional PCI multi-function with Supports LED pins for various network activity additional slave mode only functions indications Supports CardBus. The
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