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Intel® E7230 Chipset Memory Controller Hub (MCH)

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Intel® E7230 Chipset Memory Controller Hub (MCH) Intel® E7230 Chipset Memory Controller Hub (MCH) Datasheet July 2005 Reference Number: 308333-001 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel® E7230 MCH may contain design defects or errors known as errata, which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Intel, Pentium, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright© 2005, Intel Corporation 2 Intel® E7230 Chipset Memory Controller Hub (MCH) Datasheet Contents 1 Introduction.......................................................................................................................15 1.1 Terminology .......................................................................................................................16 1.2 Reference Documents .......................................................................................................17 1.3 MCH Overview...................................................................................................................18 1.3.1 Host Interface ......................................................................................................18 1.3.2 System Memory Interface....................................................................................18 1.3.3 Direct Media Interface (DMI) ...............................................................................19 1.3.4 Intel® 6700PXH 64-bit PCI Hub/Intel® 6702PXH 64-bit PCI Hub Interface (PCI Express* x8 Equivalent)........................................................20 1.3.5 System Interrupts ................................................................................................20 1.3.6 MCH Clocking......................................................................................................21 1.3.7 Power Management ............................................................................................21 2 Signal Description ............................................................................................................23 2.1 Host Interface Signals........................................................................................................25 2.2 DDR2 DRAM Channel A Interface .....................................................................................27 2.3 DDR2 DRAM Channel B Interface .....................................................................................28 2.4 DDR2 DRAM Reference and Compensation.....................................................................29 2.5 PCI Express Interface Signals ...........................................................................................29 2.6 Clocks, Reset, and Miscellaneous .....................................................................................30 2.7 Direct Media Interface (DMI)..............................................................................................31 2.8 Power, Ground...................................................................................................................31 2.9 Reset States and Pull-up/Pull-downs.................................................................................31 3 MCH Register Description................................................................................................35 3.1 Register Terminology.........................................................................................................36 3.2 Platform Configuration .......................................................................................................36 3.3 Configuration Mechanism ..................................................................................................39 3.3.1 Standard PCI Configuration Mechanism .............................................................39 3.3.2 PCI Express Enhanced Configuration Mechanism..............................................39 3.4 Routing Configuration Accesses........................................................................................40 3.4.1 Internal Device Configuration Accesses..............................................................42 3.4.2 Bridge Related Configuration Accesses..............................................................42 3.5 I/O Mapped Registers ........................................................................................................43 3.5.1 CONFIG_ADDRESS—Configuration Address Register......................................43 3.5.2 CONFIG_DATA—Configuration Data Register ...................................................45 Intel® E7230 Chipset Memory Controller Hub (MCH) Datasheet 3 4 Host Bridge Registers (Device 0, Function 0)..................................................................47 4.1 Configuration Register Details (D0:F0) ............................................................................. 49 4.1.1 VID—Vendor Identification (D0:F0) .................................................................... 49 4.1.2 DID—Device Identification (D0:F0)..................................................................... 49 4.1.3 PCICMD—PCI Command (D0:F0) ..................................................................... 49 4.1.4 PCISTS—PCI Status (D0:F0)............................................................................. 50 4.1.5 RID—Revision Identification (D0:F0).................................................................. 52 4.1.6 CC—Class Code (D0:F0) ................................................................................... 52 4.1.7 MLT—Master Latency Timer (D0:F0) ................................................................. 53 4.1.8 HDR—Header Type (D0:F0) .............................................................................. 53 4.1.9 SVID—Subsystem Vendor Identification (D0:F0) ............................................... 53 4.1.10 SID—Subsystem Identification (D0:F0) .............................................................. 54 4.1.11 CAPPTR—Capabilities Pointer (D0:F0) ............................................................. 54 4.1.12 EPBAR—Egress Port Base Address (D0:F0)..................................................... 54 4.1.13 MCHBAR—MCH Memory Mapped Register Range Base Address (D0:F0)...... 55 4.1.14 PCIEXBAR—PCI Express Register Range Base Address (D0:F0).................... 56 4.1.15 DMIBAR—Root Complex Register Range Base Address (D0:F0)..................... 57 4.1.16 DEVEN—Device Enable (D0:F0) ....................................................................... 58 4.1.17 DEAP - DRAM Error Address Pointer (D0:F0) ................................................... 58 4.1.18 DERRSYN - DRAM Error Syndrome (D0:F0)..................................................... 59 4.1.19 DERRDST - DRAM Error Destination (D0:F0).................................................... 59 4.1.20 PAM0—Programmable Attribute Map 0 (D0:F0) ................................................ 60 4.1.21 PAM1—Programmable Attribute Map 1 (D0:F0) ................................................ 61 4.1.22 PAM2—Programmable Attribute Map 2 (D0:F0) ................................................ 61 4.1.23 PAM3—Programmable Attribute Map 3 (D0:F0) ................................................ 62 4.1.24 PAM4—Programmable Attribute Map 4 (D0:F0) ................................................ 63 4.1.25 PAM5—Programmable Attribute Map 5 (D0:F0) ................................................ 63 4.1.26 PAM6—Programmable Attribute Map 6 (D0:F0) ................................................ 64 4.1.27 LAC—Legacy Access Control (D0:F0) ............................................................... 65 4.1.28 REMAPBASE - Remap Base Address Register................................................. 66 4.1.29 REMAPLIMIT - Remap Limit Address Register.................................................. 66 4.1.30 TOLUD—Top of Low Usable DRAM (D0:F0) ..................................................... 67 4.1.31 SMRAM—System Management RAM Control (D0:F0) ...................................... 67 4.1.32 ESMRAMC—Extended System Management RAM Control (D0:F0)................. 68 4.1.33 TOM - Top of Memory ........................................................................................ 69 4.1.34
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