Plug-And-Play-HOWTO.Pdf

Total Page:16

File Type:pdf, Size:1020Kb

Plug-And-Play-HOWTO.Pdf Plug-and-Play-HOWTO Plug-and-Play-HOWTO Table of Contents Plug-and-Play-HOWTO....................................................................................................................................1 David S. Lawyer mailto:dave@lafn.org..................................................................................................1 1. Introduction..........................................................................................................................................1 2. What PnP Should Do: Allocate "Bus-Resources"...............................................................................1 3. Setting up a PnP BIOS.........................................................................................................................1 4. How to Deal with PnP Cards...............................................................................................................2 5. Tell the Driver the Configuration ??....................................................................................................2 6. How Do I Find Devices and How Are They Configured?...................................................................2 7. PCI Interrupts.......................................................................................................................................2 8. PnP for External and Plug-in Devices.................................................................................................3 9. Error Messages.....................................................................................................................................3 10. Interrupt Sharing and Interrupt Conflicts...........................................................................................3 11. Appendix............................................................................................................................................3 1. Introduction..........................................................................................................................................3 1.1 1. Copyright, Trademarks, Disclaimer, & Credits.............................................................................3 Copyright...........................................................................................................................................3 Disclaimer.........................................................................................................................................4 Trademarks........................................................................................................................................4 Credits...............................................................................................................................................4 1.2 Future Plans; You Can Help..............................................................................................................4 1.3 New Versions of this HOWTO..........................................................................................................4 1.4 New in Recent Versions.....................................................................................................................4 1.5 General Introduction. Do you need this HOWTO?...........................................................................5 2. What PnP Should Do: Allocate "Bus-Resources"...............................................................................6 2.1 What is Plug-and-Play (PnP)?...........................................................................................................6 2.2 Hardware Devices and Communication with them..........................................................................6 2.3 Addresses...........................................................................................................................................7 2.4 I/O Addresses (principles relevant to other resources too)................................................................7 2.5 Memory Ranges................................................................................................................................8 2.6 IRQs --Overview...............................................................................................................................9 2.7 DMA (Direct Memory Access) or Bus Mastering..........................................................................10 2.8 DMA Channels (not for PCI bus)...................................................................................................10 2.9 "Resources" for both Device and Driver.........................................................................................10 2.10 Resources are Limited....................................................................................................................11 Ideal Computers..............................................................................................................................11 Real Computers...............................................................................................................................11 2.11 Second Introduction to PnP...........................................................................................................12 2.12 How Pnp Works (simplified).........................................................................................................12 2.13 Starting Up the PC.........................................................................................................................13 2.14 Buses..............................................................................................................................................14 2.15 How Linux Does PnP...................................................................................................................14 2.16 Problems with Linux PnP..............................................................................................................15 3. Setting up a PnP BIOS......................................................................................................................16 3.1 Do you have a PnP operating system?............................................................................................16 Linux prior to the 2.4 kernel...........................................................................................................16 Windows 2000 and XP....................................................................................................................16 MS Windows 95, 98 (and Me ?).....................................................................................................17 3.2 Assigning Resources by the BIOS..................................................................................................18 i Plug-and-Play-HOWTO Table of Contents Plug-and-Play-HOWTO 3.3 Reset the configuration?.................................................................................................................18 4. How to Deal with PnP Cards.............................................................................................................19 4.1 Introduction to Dealing with PnP Devices.......................................................................................19 4.2 Device Driver Configures, Reserving Resources...........................................................................19 4.3 /sys User Interface Configures........................................................................................................19 4.4 BIOS Configures.............................................................................................................................20 Intro to Using the BIOS to Configure PnP......................................................................................20 The BIOS's ESCD Database..........................................................................................................20 Using Windows to set the ESCD...................................................................................................21 Adding a New Device (under Linux or Windows).........................................................................22 4.5 ISA cards only: Disable PnP ?........................................................................................................22 4.6 ISA Bus: Isapnp (part of isapnptools).............................................................................................22 4.7 PCI Utilities....................................................................................................................................23 4.8 Windows Configures......................................................................................................................23 4.9 PnP Software/Documents...............................................................................................................24 5. Tell the Driver the Configuration ??.................................................................................................24 5.1 Introduction......................................................................................................................................24 5.2 Serial Port Driver Example..............................................................................................................25 6. How Do I Find Devices and How Are They Configured?................................................................25 6.1 Finding and How-Configured Are Related......................................................................................26
Recommended publications
  • Fujitsu Plug-And-Play Controller (Ppc)
    cO MB86701 FUJITSU PLUG-AND-PLAY CONTROLLER (PPC) ADVANCE INFORMATION JULY 1994 KEY FEATURES • Provides Plug-and-Play compatibility for ISA add-in • Read the card's resource requirements data cards • Identify the card and configure its resources • Conforms to Intel/Microsoft Plug-and-Play specifica­ • Locate a driver for the card tion vl.Oa (May 5, 1994) lbis process is done automatically at every hard reset of • Interface to serial resource EEPROM with read and write the system. Plug-and-Play ISA cards will interoperate capability for storage of data structures required by Plug­ and-Play and additional user defined data. with standard ISA cards in a fully compatible manner. Information that identifies the card and describes the sys­ • Provides five chip select outputs: tem resources which are requested by the card, such as - Two I/O chip selects, /CSO and /CSl, f{AO-AlS} memory and IJO space, DMA channel, and interrupt level - Two memory chip selects, JC,S2 and /CS3, f{AO-A23} supported is maintained in a standardized read-only for­ - JC,S4 is the OR of CSO and CS3 and is used as described mat below In a system that uses only Plug-and-Play ISA cards, it • Supports two DMA channels and two interrupts from the will be possible to achieve full auto-configuration. It is logical device recognized that the current generation of standard ISA - Interrupts directed to any of 11 interrupt channels on the cards will coexist with Plug-and-Play ISA cards in the ISA bus same system. In such systems, the configuration solution - DMA directed to any of 7 DMA channels on the ISA needs to be augmented in the BIOS and/or operating sys­ bus tem to manage and arbitrate the allocation of ISA bus re­ • Provides four quasi-bidirectional general purpose I/O sources.
    [Show full text]
  • Designing PCI Cards and Drivers for Power Macintosh Computers
    Designing PCI Cards and Drivers for Power Macintosh Computers Revised Edition Revised 3/26/99 Technical Publications © Apple Computer, Inc. 1999 Apple Computer, Inc. Adobe, Acrobat, and PostScript are Even though Apple has reviewed this © 1995, 1996 , 1999 Apple Computer, trademarks of Adobe Systems manual, APPLE MAKES NO Inc. All rights reserved. Incorporated or its subsidiaries and WARRANTY OR REPRESENTATION, EITHER EXPRESS OR IMPLIED, WITH No part of this publication may be may be registered in certain RESPECT TO THIS MANUAL, ITS reproduced, stored in a retrieval jurisdictions. QUALITY, ACCURACY, system, or transmitted, in any form America Online is a service mark of MERCHANTABILITY, OR FITNESS or by any means, mechanical, Quantum Computer Services, Inc. FOR A PARTICULAR PURPOSE. AS A electronic, photocopying, recording, Code Warrior is a trademark of RESULT, THIS MANUAL IS SOLD “AS or otherwise, without prior written Metrowerks. IS,” AND YOU, THE PURCHASER, ARE permission of Apple Computer, Inc., CompuServe is a registered ASSUMING THE ENTIRE RISK AS TO except to make a backup copy of any trademark of CompuServe, Inc. ITS QUALITY AND ACCURACY. documentation provided on Ethernet is a registered trademark of CD-ROM. IN NO EVENT WILL APPLE BE LIABLE Xerox Corporation. The Apple logo is a trademark of FOR DIRECT, INDIRECT, SPECIAL, FrameMaker is a registered Apple Computer, Inc. INCIDENTAL, OR CONSEQUENTIAL trademark of Frame Technology Use of the “keyboard” Apple logo DAMAGES RESULTING FROM ANY Corporation. (Option-Shift-K) for commercial DEFECT OR INACCURACY IN THIS purposes without the prior written Helvetica and Palatino are registered MANUAL, even if advised of the consent of Apple may constitute trademarks of Linotype-Hell AG possibility of such damages.
    [Show full text]
  • Scalable Cache Coherent Shared Memory at Cluster Prices
    numascale Scalable Cache Coherent Shared Memory at Cluster Prices White Paper Redefining Scalable OpenMP and MPI Price-to-Performance with Numascale’s NumaConnect By: Douglas Eadline About the Author: Douglas Eadline, Ph.D. has been writing and working with high performance computers and Linux for over twenty years. He is also the Editor of Cluster- Monkey.net. NW4V1 ABSTRACT Using commodity hardware and the “plug-and-play” NumaConnect interconnect, Numascale delivers true shared memory programming and simpler administration at standard HPC cluster price points. One such system currently offers users over 1,700 cores with a 4.6 TB single memory image. The NumaConnect cluster excels at both OpenMP and MPI computing within the same shared memory environment. No extra software or program modifications are needed to take advantage of the entire system. Results for the NASA Advanced Supercomputing (NAS) Parallel Benchmarks have set a new record for OpenMP core count and problem size. OpenMP results show good scalability, with best results coming from larger problem sizes. In addition, NumaConnect shared memory MPI performance delivers better results than InfiniBand clus- ters, using standard tools without modification for the underlying hardware environment. A cost compari- son with a small FDR InfiniBand cluster shows a comparable price point when ease of programming, high performance, and ease of administration are considered. Several production systems are performing satisfactorily, including those in University of Oslo in Norway, Statoil,
    [Show full text]
  • Macintosh Ilsi Overview
    Macintosh Ils i Overview The Apple® Macintosh" Hsi is the lowest­ amount of dynamic random-access such as printers, scanners, and CD-ROM cost member of the Macintosh II line, memory (DRAM) through a new feature, disc drives, as well as access the built-in Apple Computer's most powetfulline of virtual memory. networking capabilities foundin all Macintosh personal computers. Offering The Macintosh Hsi comes with built-in Macintosh computers. high performance and a wide range of support forfour Apple monitors as well One exciting new Macintosh advance­ expansion and video options, the as third-party monitors, so you can ment incorporated into the Macintosh Hsi Macintosh Hsi is ideal forpeople who choose the monitor that best suits your is sound input. The Macintosh Hsi comes need a powetfulbut very affordable needs-then simply plug it in. In addi­ with a microphone and phono jack Macintosh system that can easily grow tion, by adding a video expansion card, adapter, which let you input your voice with their needs over time. you can use any other Apple or third­ into documents, presentations, and even Like other Macintosh II systems, the partymonitor with the Macintosh Hsi. electronic mail messages. Macintosh Hsi offersexcellent perfor­ The Macintosh Hsi can be easily Best of all, the Macintosh Hsi provides mance. At the heart of the Macintosh Hsi expanded to incorporate new capabilities all of the important benefitsfor which is a 20-megahertz 68030 microprocessor or increase system performance. An inter­ the Macintosh is known-powetfultech­
    [Show full text]
  • PCI-X & PCI Core User's Guide
    PCI-X & PCI Core User's Guide Version 7.1.0 27-Feb-2007 © PLD Applications, 1996-2007 PLD Applications Web: http://www.plda.com Europarc Pichaury A2 Email: [email protected] 1330, rue Guillibert USA : 1 866 513 0362 (toll free) 13856 Aix-en-Provence Intl : + 33 442 393 600 CEDEX 3 - France Fax : + 33 442 394 902 Associate Member PCI-X & PCI Core User's Guide Features General ° 32-bit/64-bit PCI-X & PCI master/target interface ° Supports bus speed up to 133 MHz ° Multi-function core can implement up to 2 independent functions ° Full support for 64-bit addressing ° PCI-X Specification 2.0a mode 1 compliant ° PCI Specification 3.0 compliant ° Supports PCI power management ° Built-in support for in-site programming through JTAG interface ° Supports Message Signalled Interrupts Customization ° Easy customization with the PCI Wizard's user interface and on-line help. ° PCI Wizard has built-in support for VHDL and Verilog. ° All features can be parameterized, removing all unused logic ° Full plug-and-play support Configuration ° Supports all required and optional type 0 configuration registers ° Up to 6 BARs plus expansion ROM can be implemented ° Up to 32 user defined configuration registers Data transfer ° Supports up to 4KB burst transfers with zero wait-state insertion. ° Supports all memory and I/O commands ° Supports interrupt acknowledge cycles in target mode ° Can insert wait-states and generate all types of terminations ° Up to two split channels and 32 outstanding split transactions DMA ° Up to 4 independent DMA channels with rotating priority ° Flexible backend interface can directly control FIFO devices.
    [Show full text]
  • M-1: the Mealy Open Source Custom MIDI Controller Student’S Names: Garrett Leung, Darren Mistica Advisor’S Name: Bryan Mealy
    The Mealy Open Source Custom MIDI Controller Computer Engineering CALIFORNIA POLYTECHNIC STATE UNIVERSITY, SAN LUIS OBISPO Advisor Garrett Leung, EE Bryan Mealy June 2015 Darren Mistica, CPE Page 1 ABSTRACT With the high price of large mixing consoles, aspiring artists are restricted to using a mouse to control digital facsimiles of knobs, faders, switches, and buttons. Though using the software controls is considered a simple task, dedicated hardware allows for tactile, visual, and utility. At a low cost, the heart of the MTech M-1 can be customized and placed into any shell with any combination of controls as possible with the underlying platform. Modern MIDI controllers require significant physical space due to their preset button layout and space consuming setups. Despite their high price, modern MIDI controllers have only one setup. With one setup, music producers or artists have a hard time carrying their MIDI controllers around for concerts or other performances. The M-1 MIDI controller addresses the high cost that physical MIDI controllers currently hold on the market by allowing users to make/create their own specific MIDI control board using any combination of knobs, dials, buttons, and sliders. This customization of the controller allows the user to save space and money, while also accommodating for their style or a specific performance. The M-1 controller is an affordable and fully customizable mechanical system. The fully customizable MIDI controller represents a digital MIDI controller while allowing the user to fully customize the physical layout of the controller. Users can place the buttons for the delay, reverb, compression, distortion, etc.
    [Show full text]
  • Volume 12: PCIE Configuration Registers (Haswell)
    © 2013 Intel Corporation Intel Open Source Graphics Programmer’s Reference Manual (PRM) for the 2013 Intel® Core™ Processor Family, including Intel HD Graphics, Intel Iris™ Graphics and Intel Iris Pro Graphics Volume 12: PCIE Configuration Registers (Haswell) 12/18/2013 1 Copyright INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. A "Mission Critical Application" is any application in which failure of the Intel Product could result, directly or indirectly, in personal injury or death. SHOULD YOU PURCHASE OR USE INTEL'S PRODUCTS FOR ANY SUCH MISSION CRITICAL APPLICATION, YOU SHALL INDEMNIFY AND HOLD INTEL AND ITS SUBSIDIARIES, SUBCONTRACTORS AND AFFILIATES, AND THE DIRECTORS, OFFICERS, AND EMPLOYEES OF EACH, HARMLESS AGAINST ALL CLAIMS COSTS, DAMAGES, AND EXPENSES AND REASONABLE ATTORNEYS' FEES ARISING OUT OF, DIRECTLY OR INDIRECTLY, ANY CLAIM OF PRODUCT LIABILITY, PERSONAL INJURY, OR DEATH ARISING IN ANY WAY OUT OF SUCH MISSION CRITICAL APPLICATION, WHETHER OR NOT INTEL OR ITS SUBCONTRACTOR WAS NEGLIGENT IN THE DESIGN, MANUFACTURE, OR WARNING OF THE INTEL PRODUCT OR ANY OF ITS PARTS. Intel may make changes to specifications and product descriptions at any time, without notice.
    [Show full text]
  • Pocket UDD (Ultra Digidrive) II
    Pocket UDD (Ultra DigiDrive) II Models: PUDDEPU3, PUDDESP, PUDDES, PPROEPU3, PPROESP, PPROES INTRODUCTION The Addonics Pocket UDD (Ultra DigiDrive) II is one of the fastest Readers/Writers for Flash media, PCMCIA hard drives and ATA Flash. Built on the same utilitarian concept of its predecessor Pocket UDD, the Pocket UDD II supports maximum throughput of 150 Mbytes/sec via eSATA or the latest USB 3.0 connection, cutting almost half of the data transfer time between the new high speed media and the computer. LED Eject Button By using an optional CF DigiAdapter or the Addonics Flash Flash Media Slot DigiAdapter Extreme, the Pocket UDD II can also be used like a regular flash reader to read/write to other popular Flash media - CF-I, CF-II, Smart Media, Memory stick, Secure Digital Card, Multimedia Card, Micro Drive or XD Card. 5V Power Input eSATA Port Addonics Technologies Inc. www.addonics.com 1918 Junction Avenue, San Jose, CA 95131 Phone: 408.573.8580 | Fax: 408.573.8588 Pocket UDD (Ultra DigiDrive) II Models: PUDDEPU3, PUDDESP, PUDDES, PPROEPU3, PPROESP, PPROES FEATURES • Choice of model for connection to computer via USB 3.0 / 2.0, eSATAp (Hybrid eSATA USB) or standard eSATA • Powered from USB, eSATAp port or optional AC/DC power adapter • Read and write directly to PCMCIA hard drive or ATA Flash • Read and write to CF-I, CF-II, Micro Drive via optional CF-PCMCIA adapter • Read and write to Secure Digital Card (SD, SDHC mini SD, SDXC), Memory Stick (MS, MS DUO, MS PRO DU), Smart Memory, Memory Stick, Multimedia Card, and XD Card via
    [Show full text]
  • UM10204 I2C-Bus Specification and User Manual Rev
    UM10204 I2C-bus specification and user manual Rev. 03 — 19 June 2007 User manual Document information Info Content Keywords I2C, I2C-bus, Standard-mode, Fast-mode, Fast-mode Plus, Fm+, High Speed, Hs, inter-IC, SDA, SCL Abstract Philips Semiconductors (now NXP Semiconductors) developed a simple bidirectional 2-wire bus for efficient inter-IC control. This bus is called the Inter-IC or I2C-bus. Only two bus lines are required: a serial data line (SDA) and a serial clock line (SCL). Serial, 8-bit oriented, bidirectional data transfers can be made at up to 100 kbit/s in the Standard-mode, up to 400 kbit/s in the Fast-mode, up to 1 Mbit/s in the Fast-mode Plus (Fm+), or up to 3.4 Mbit/s in the High-speed mode. NXP Semiconductors UM10204 I2C-bus specification and user manual Revision history Rev Date Description 03 20070619 Many of today’s applications require longer buses and/or faster speeds. Fast-mode plus was introduced to meet this need by increasing drive strength by as much as 10× and increasing the data rate to 1 Mbit/s while maintaining downward compatibility to Fast-mode and Standard-mode speeds and software commands. Modifications: • Re-ordered sections and clarified several requirements • Added description of Fast-mode Plus (Fm+) specifications • Added description of the Device ID Field • Added Bus Clear procedures • Moved level shifting information to a separate application note (AN10441) • Clarified the process of sizing Rp • Added limits for tVD;DAT and tVD;ACK 2.1 2000 Version 2.1 of the I2C-bus specification 2.0 1998 The I2C-bus has become a de facto world standard that is now implemented in over 1000 different ICs and licensed to more than 50 companies.
    [Show full text]
  • Introduction to PCI Express
    An Introduction to PCI Express by Ravi Budruk Abstract The Peripheral Component Interconnect - Express (PCI Express) architecture is a third- generation, high-performance I/O bus used to interconnect peripheral devices in appli- cations such as computing and communication platforms. The term “third generation” describes the developmental history of the bus: first-generation buses included the ISA, EISA, VESA, and Micro Channel buses, while second-generation buses include PCI, AGP, and PCI-X. Due to its comparitively high speed, low cost and low power, PCI Express is very likely to find a home in mobile, desktop, workstation, server, embedded computing and communication platforms. The intent of this paper is to introduce the reader to the terminology and basics of this exciting new technology. The Role of the Original PCI Solution Keep the Good Parts of PCI The PCI Express architects have carried forward many of the best features of previous generation bus architectures and taken advantage of new developments in computer architecture to improve on them. For example, PCI Express architecture employs the same usage model and load-store communication model that PCI and PCI-X used, and supports familiar transactions such as memory read/write, IO read/write and configuration read/write transactions. The memory, IO and configuration address space model is also the same as in PCI and PCI- X, which allows existing OSs and driver software to run in a PCI Express system with- out any modifications. This makes PCI Express software backwards compatible with PCI and PCI-X systems. As an example of this, PCI/ACPI power management software written for current designs should be able to run without modification on a PCI Express machine.
    [Show full text]
  • Designcon 2003 Tecforum I2C Bus Overview January 27 2003
    DesignCon 2003 TecForum I2C Bus Overview January 27 2003 Philips Semiconductors Jean Marc Irazabal –Technical Marketing Manager for I2C Devices Steve Blozis –International Product Manager for I2C Devices Agenda • 1st Hour • Serial Bus Overview • I2C Theory Of Operation • 2nd Hour • Overcoming Previous Limitations • I2C Development Tools and Evaluation Board • 3rd Hour • SMBus and IPMI Overview • I2C Device Overview • I2C Patent and Legal Information • Q & A Slide speaker notes are included in AN10216 I2C Manual 2 DesignCon 2003 TecForum I C Bus Overview 2 1st Hour 2 DesignCon 2003 TecForum I C Bus Overview 3 Serial Bus Overview 2 DesignCon 2003 TecForum I C Bus Overview 4 Com m uni c a t i o ns Automotive SERIAL Consumer BUSES IEEE1394 DesignCon 2003 TecForum I UART SPI 2 C Bus Overview In d u s t r ia l 5 General concept for Serial communications SCL SDA select 3 select 2 select 1 READ Register or enable Shift Reg# enable Shift Reg# enable Shift Reg# WRITE? // to Ser. // to Ser. // to Ser. Shift R/W Parallel to Serial R/W R/W “MASTER” DATA SLAVE 1 SLAVE 2 SLAVE 3 • A point to point communication does not require a Select control signal • An asynchronous communication does not have a Clock signal • Data, Select and R/W signals can share the same line, depending on the protocol • Notice that Slave 1 cannot communicate with Slave 2 or 3 (except via the ‘master’) Only the ‘master’ can start communicating. Slaves can ‘only speak when spoken to’ 2 DesignCon 2003 TecForum I C Bus Overview 6 Typical Signaling Characteristics LVTTL 2 RS422/485
    [Show full text]
  • Creating a Pci Express Interconnect in the Gem5 Simulator
    CREATING A PCI EXPRESS INTERCONNECT IN THE GEM5 SIMULATOR BY KRISHNA PARASURAM SRINIVASAN THESIS Submitted in partial fulfillment of the requirements for the degree of Master of Science in Electrical and Computer Engineering in the Graduate College of the University of Illinois at Urbana-Champaign, 2018 Urbana, Illinois Adviser: Associate Professor Nam Sung Kim ABSTRACT In this thesis, the objective was to implement a PCI (Peripheral Component Interconnect) Express interconnect in the gem5 architecture simulator. The interconnect was designed with the goal of aiding accurate modeling of PCI Express-based devices in gem5 in the future. The PCI Express interconnect that was created consisted of a root complex, PCI Express switch, as well as individual PCI Express links. Each of these created components can work independently, and can be easily integrated into the existing gem5 platforms for the ARM Instruction Set Architecture. The created PCI Express interconnect was evaluated against a real PCI Express interconnect present on an Intel Xeon server platform. The bandwidth offered by both interconnects was compared by reading data from storage devices using the Linux utility “dd”. The results indicate that the gem5 PCI Express interconnect can provide between 81% - 91.6% of the bandwidth of the real PCI Express interconnect. However, architectural differences between the gem5 and Intel Xeon platforms used, as well as unimplemented features of the PCI Express protocol in the gem5 PCI Express interconnect, necessitate more strenuous validation
    [Show full text]