DOCSLIB.ORG

I2C Manual INTEGRATED CI RCUITS

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
I2C Manual INTEGRATED CI RCUITS AN10216-01 I2C Manual INTEGRATED CI RCUITS APPLICATION NOTE AN10216-01 I2C MANUAL Abstract – The I2C Manual provides a broad overview of the various serial buses, why the I2C bus should be considered, technical detail of the I2C bus and how it works, previous limitations/solutions, comparison to the SMBus, Intelligent Platform Management Interface implementations, review of the different I2C devices that are available and patent/royalty information. The I2C Manual was presented during the 3 hour TecForum at DesignCon 2003 in San Jose, CA on 27 January 2003. Jean-Marc Irazabal – I2C Technical Marketing Manager Steve Blozis – I2C International Product Manager Specialty Logic Product Line Logic Product Group Philips Semiconductors March 24, 2003 1 AN10216-01 I2C Manual TABLE OF CONTENTS TABLE OF CONTENTS...................................................................................................................................................2 OVERVIEW .......................................................................................................................................................................4 DESCRIPTION.....................................................................................................................................................................4 SERIAL BUS OVERVIEW...............................................................................................................................................4 UART OVERVIEW.............................................................................................................................................................6 SPI OVERVIEW..................................................................................................................................................................6 CAN OVERVIEW ...............................................................................................................................................................7 USB OVERVIEW................................................................................................................................................................9 1394 OVERVIEW .............................................................................................................................................................10 2 I C OVERVIEW ................................................................................................................................................................11 SERIAL BUS COMPARISON SUMMARY .............................................................................................................................12 2 I C THEORY OF OPERATION ....................................................................................................................................13 2 I C BUS TERMINOLOGY...................................................................................................................................................13 START AND STOP CONDITIONS ....................................................................................................................................14 HARDWARE CONFIGURATION ...............................................................................................................................14 BUS COMMUNICATION.............................................................................................................................................14 TERMINOLOGY FOR BUS TRANSFER ................................................................................................................................15 2 I C DESIGNER BENEFITS .................................................................................................................................................17 2 I C MANUFACTURERS BENEFITS.....................................................................................................................................17 OVERCOMING PREVIOUS LIMITATIONS .............................................................................................................18 ADDRESS CONFLICTS ......................................................................................................................................................18 CAPACITIVE LOADING > 400 PF (ISOLATION) .................................................................................................................19 VOLTAGE LEVEL TRANSLATION .....................................................................................................................................20 2 INCREASE I C BUS RELIABILITY (SLAVE DEVICES).........................................................................................................21 2 INCREASING I C BUS RELIABILITY (MASTER DEVICES)..................................................................................................22 CAPACITIVE LOADING > 400 PF (BUFFER)......................................................................................................................22 2 LIVE INSERTION INTO THE I C BUS .................................................................................................................................24 2 LONG I C BUS LENGTHS .................................................................................................................................................25 2 PARALLEL TO I C BUS CONTROLLER ..............................................................................................................................25 DEVELOPMENT TOOLS AND EVALUATION BOARD OVERVIEW..................................................................26 2 PURPOSE OF THE DEVELOPMENT TOOL AND I C EVALUATION BOARD...........................................................................26 WIN-I2CNT SCREEN EXAMPLES.....................................................................................................................................28 HOW TO ORDER THE I2C 2002-1A EVALUATION KIT .....................................................................................................31 2 COMPARISON OF I C WITH SMBUS........................................................................................................................31 2 I C/SMBUS COMPLIANCY ...............................................................................................................................................31 DIFFERENCES SMBUS 1.0 AND SMBUS 2.0 ....................................................................................................................32 INTELLIGENT PLATFORM MANAGEMENT INTERFACE (IPMI) ....................................................................32 INTEL SERVER MANAGEMENT.........................................................................................................................................33 PICMG ...........................................................................................................................................................................33 VMEBUS.........................................................................................................................................................................34 2 I C DEVICE OVERVIEW..............................................................................................................................................35 TV RECEPTION................................................................................................................................................................36 RADIO RECEPTION ..........................................................................................................................................................36 2 AN10216-01 I2C Manual AUDIO PROCESSING ........................................................................................................................................................37 DUAL TONE MULTI-FREQUENCY (DTMF)......................................................................................................................37 LCD DISPLAY DRIVER....................................................................................................................................................37 LIGHT SENSOR ................................................................................................................................................................38 REAL TIME CLOCK/CALENDAR .......................................................................................................................................38 GENERAL PURPOSE I/O EXPANDERS ...............................................................................................................................38 LED DIMMERS AND BLINKERS .......................................................................................................................................40 DIP SWITCH....................................................................................................................................................................42 MULTIPLEXERS AND SWITCHES.......................................................................................................................................43 VOLTAGE LEVEL TRANSLATORS.....................................................................................................................................45 BUS REPEATERS AND HUBS ............................................................................................................................................45
Load more

Recommended publications
  • Allgemeines Abkürzungsverzeichnis
    Allgemeines Abkürzungsverzeichnis L.
    [Show full text]
  • What Is It and How We Use It
    Infiniband Overview What is it and how we use it What is Infiniband • Infiniband is a contraction of "Infinite Bandwidth" o can keep bundling links so there is no theoretical limit o Target design goal is to always be faster than the PCI bus. • Infiniband should not be the bottleneck. • Credit based flow control o data is never sent if receiver can not guarantee sufficient buffering What is Infiniband • Infiniband is a switched fabric network o low latency o high throughput o failover • Superset of VIA (Virtual Interface Architecture) o Infiniband o RoCE (RDMA over Converged Ethernet) o iWarp (Internet Wide Area RDMA Protocol) What is Infiniband • Serial traffic is split into incoming and outgoing relative to any port • Currently 5 data rates o Single Data Rate (SDR), 2.5Gbps o Double Data Rate (DDR), 5 Gbps o Quadruple Data Rate (QDR), 10 Gbps o Fourteen Data Rate (FDR), 14.0625 Gbps o Enhanced Data Rate (EDR) 25.78125 Gbps • Links can be bonded together, 1x, 4x, 8x and 12x HDR - High Data Rate NDR - Next Data Rate Infiniband Road Map (Infiniband Trade Association) What is Infiniband • SDR, DDR, and QDR use 8B/10B encoding o 10 bits carry 8 bits of data o data rate is 80% of signal rate • FDR and EDR use 64B/66B encoding o 66 bits carry 64 bits of data Signal Rate Latency SDR 200ns DDR 140ns QDR 100ns Hardware 2 Hardware vendors • Mellanox o bought Voltaire • Intel o bought Qlogic Infiniband business unit Need to standardize hardware. Mellanox and Qlogic cards work in different ways.
    [Show full text]
  • Fujitsu Plug-And-Play Controller (Ppc)
    cO MB86701 FUJITSU PLUG-AND-PLAY CONTROLLER (PPC) ADVANCE INFORMATION JULY 1994 KEY FEATURES • Provides Plug-and-Play compatibility for ISA add-in • Read the card's resource requirements data cards • Identify the card and configure its resources • Conforms to Intel/Microsoft Plug-and-Play specifica­ • Locate a driver for the card tion vl.Oa (May 5, 1994) lbis process is done automatically at every hard reset of • Interface to serial resource EEPROM with read and write the system. Plug-and-Play ISA cards will interoperate capability for storage of data structures required by Plug­ and-Play and additional user defined data. with standard ISA cards in a fully compatible manner. Information that identifies the card and describes the sys­ • Provides five chip select outputs: tem resources which are requested by the card, such as - Two I/O chip selects, /CSO and /CSl, f{AO-AlS} memory and IJO space, DMA channel, and interrupt level - Two memory chip selects, JC,S2 and /CS3, f{AO-A23} supported is maintained in a standardized read-only for­ - JC,S4 is the OR of CSO and CS3 and is used as described mat below In a system that uses only Plug-and-Play ISA cards, it • Supports two DMA channels and two interrupts from the will be possible to achieve full auto-configuration. It is logical device recognized that the current generation of standard ISA - Interrupts directed to any of 11 interrupt channels on the cards will coexist with Plug-and-Play ISA cards in the ISA bus same system. In such systems, the configuration solution - DMA directed to any of 7 DMA channels on the ISA needs to be augmented in the BIOS and/or operating sys­ bus tem to manage and arbitrate the allocation of ISA bus re­ • Provides four quasi-bidirectional general purpose I/O sources.
    [Show full text]
  • Dell EMC Poweredge T340 Technical Guide
    Dell EMC PowerEdge T340 Technical Guide Regulatory Model: E60S Regulatory Type: E60S001 Dec. 2020 Rev. A07 Notes, cautions, and warnings NOTE: A NOTE indicates important information that helps you make better use of your product. CAUTION: A CAUTION indicates either potential damage to hardware or loss of data and tells you how to avoid the problem. WARNING: A WARNING indicates a potential for property damage, personal injury, or death. © 2018 - 2020 Dell Inc. or its subsidiaries. All rights reserved. Dell, EMC, and other trademarks are trademarks of Dell Inc. or its subsidiaries. Other trademarks may be trademarks of their respective owners. 1 Product Overview Topics: • Introduction • New technologies Introduction The Dell EMC PowerEdge T340 is the reliable, easy to manage, and scalable 1-socket tower server for growing businesses and remote offices/ branch offices. New technologies The PowerEdge T340 equipped with Intel® Xeon® E-2100 and E-2200 product family processors support to help run applications faster and support for full-feature remote management (iDRAC9). The T340 is versatile enough to address many customer segments and workloads. Target workloads include ● Small and medium businesses and organizations: Collaboration/sharing productivity applications, databases, web serving, backup/recovery, and mail and messaging. ● ROBO: Applications and workloads specific to the particular industry, e.g. Retail, Healthcare, Finance, Education, etc. The following table shows the list of new technologies offered by the PowerEdge T340: New Technologies Detailed Descriptions Intel® C246 series chipset Please refer to the chipset section for details. Intel® Xeon® processor E- 2100 and E-2200 Product The Intel® processor that works with Intel® C246 series Family chipset.
    [Show full text]
  • 3. System Management Bus
    Input/Output Systems and Peripheral Devices 1 3. SYSTEM MANAGEMENT BUS This laboratory work presents the System Management Bus (SMBus). After an over- view of SMBus, bit and data transfers are described, the bus arbitration procedure is present- ed, the differences between SMBus and the I2C bus are highlighted, and several command protocols are detailed. Next, the Intel SMBus controller is presented, including its registers and commands, as well as its use with I2C devices. The applications aim to detect the devices connected to the computer’s SMBus, read the contents of SPD memories present in the sys- tem, and decode the contents of these memories. 3.1. Overview of SMBus System Management Bus (SMBus) is a simple serial bus with only two signal lines. This bus can be used for communication between various system devices and between these devices and the rest of a system. The operating principles of SMBus are similar to those of the I2C bus. There are, however, several differences between the two buses, differences which will be presented later. SMBus represents a control bus for system management and power management op- erations. A system may use the SMBus to transfer messages to and from various devices in- stead of using individual control lines, which allows to reduce pin count and interconnection wires. A device may use the SMBus to provide manufacturer information, provide the device model number, report different types of errors, accept control parameters, and return the de- vice status. SMBus was initially proposed by Intel as a link between an intelligent battery, a charger for the battery and a microcontroller that communicates with the rest of the system.
    [Show full text]
  • Designing PCI Cards and Drivers for Power Macintosh Computers
    Designing PCI Cards and Drivers for Power Macintosh Computers Revised Edition Revised 3/26/99 Technical Publications © Apple Computer, Inc. 1999 Apple Computer, Inc. Adobe, Acrobat, and PostScript are Even though Apple has reviewed this © 1995, 1996 , 1999 Apple Computer, trademarks of Adobe Systems manual, APPLE MAKES NO Inc. All rights reserved. Incorporated or its subsidiaries and WARRANTY OR REPRESENTATION, EITHER EXPRESS OR IMPLIED, WITH No part of this publication may be may be registered in certain RESPECT TO THIS MANUAL, ITS reproduced, stored in a retrieval jurisdictions. QUALITY, ACCURACY, system, or transmitted, in any form America Online is a service mark of MERCHANTABILITY, OR FITNESS or by any means, mechanical, Quantum Computer Services, Inc. FOR A PARTICULAR PURPOSE. AS A electronic, photocopying, recording, Code Warrior is a trademark of RESULT, THIS MANUAL IS SOLD “AS or otherwise, without prior written Metrowerks. IS,” AND YOU, THE PURCHASER, ARE permission of Apple Computer, Inc., CompuServe is a registered ASSUMING THE ENTIRE RISK AS TO except to make a backup copy of any trademark of CompuServe, Inc. ITS QUALITY AND ACCURACY. documentation provided on Ethernet is a registered trademark of CD-ROM. IN NO EVENT WILL APPLE BE LIABLE Xerox Corporation. The Apple logo is a trademark of FOR DIRECT, INDIRECT, SPECIAL, FrameMaker is a registered Apple Computer, Inc. INCIDENTAL, OR CONSEQUENTIAL trademark of Frame Technology Use of the “keyboard” Apple logo DAMAGES RESULTING FROM ANY Corporation. (Option-Shift-K) for commercial DEFECT OR INACCURACY IN THIS purposes without the prior written Helvetica and Palatino are registered MANUAL, even if advised of the consent of Apple may constitute trademarks of Linotype-Hell AG possibility of such damages.
    [Show full text]
  • Scalable Cache Coherent Shared Memory at Cluster Prices
    numascale Scalable Cache Coherent Shared Memory at Cluster Prices White Paper Redefining Scalable OpenMP and MPI Price-to-Performance with Numascale’s NumaConnect By: Douglas Eadline About the Author: Douglas Eadline, Ph.D. has been writing and working with high performance computers and Linux for over twenty years. He is also the Editor of Cluster- Monkey.net. NW4V1 ABSTRACT Using commodity hardware and the “plug-and-play” NumaConnect interconnect, Numascale delivers true shared memory programming and simpler administration at standard HPC cluster price points. One such system currently offers users over 1,700 cores with a 4.6 TB single memory image. The NumaConnect cluster excels at both OpenMP and MPI computing within the same shared memory environment. No extra software or program modifications are needed to take advantage of the entire system. Results for the NASA Advanced Supercomputing (NAS) Parallel Benchmarks have set a new record for OpenMP core count and problem size. OpenMP results show good scalability, with best results coming from larger problem sizes. In addition, NumaConnect shared memory MPI performance delivers better results than InfiniBand clus- ters, using standard tools without modification for the underlying hardware environment. A cost compari- son with a small FDR InfiniBand cluster shows a comparable price point when ease of programming, high performance, and ease of administration are considered. Several production systems are performing satisfactorily, including those in University of Oslo in Norway, Statoil,
    [Show full text]
  • Macintosh Ilsi Overview
    Macintosh Ils i Overview The Apple® Macintosh" Hsi is the lowest­ amount of dynamic random-access such as printers, scanners, and CD-ROM cost member of the Macintosh II line, memory (DRAM) through a new feature, disc drives, as well as access the built-in Apple Computer's most powetfulline of virtual memory. networking capabilities foundin all Macintosh personal computers. Offering The Macintosh Hsi comes with built-in Macintosh computers. high performance and a wide range of support forfour Apple monitors as well One exciting new Macintosh advance­ expansion and video options, the as third-party monitors, so you can ment incorporated into the Macintosh Hsi Macintosh Hsi is ideal forpeople who choose the monitor that best suits your is sound input. The Macintosh Hsi comes need a powetfulbut very affordable needs-then simply plug it in. In addi­ with a microphone and phono jack Macintosh system that can easily grow tion, by adding a video expansion card, adapter, which let you input your voice with their needs over time. you can use any other Apple or third­ into documents, presentations, and even Like other Macintosh II systems, the partymonitor with the Macintosh Hsi. electronic mail messages. Macintosh Hsi offersexcellent perfor­ The Macintosh Hsi can be easily Best of all, the Macintosh Hsi provides mance. At the heart of the Macintosh Hsi expanded to incorporate new capabilities all of the important benefitsfor which is a 20-megahertz 68030 microprocessor or increase system performance. An inter­ the Macintosh is known-powetfultech­
    [Show full text]
  • EPC612D8A-TB EPC612D8A EPC612D8 User Manual
    EPC612D8A-TB EPC612D8A EPC612D8 User Manual Version 1.1 Published August 2016 Copyright©2016 ASRock Rack INC. All rights reserved. Version 1.1 Published October 2016 Copyright©2016 ASRock Rack Inc. All rights reserved. Copyright Notice: No part of this documentation may be reproduced, transcribed, transmitted, or translated in any language, in any form or by any means, except duplication of documentation by the purchaser for backup purpose, without written consent of ASRock Rack Inc. Products and corporate names appearing in this documentation may or may not be registered trademarks or copyrights of their respective companies, and are used only for identification or explanation and to the owners’ benefit, without intent to infringe. Disclaimer: Specifications and information contained in this documentation are furnished for informational use only and subject to change without notice, and should not be constructed as a commitment by ASRock Rack. ASRock Rack assumes no responsibility for any errors or omissions that may appear in this documentation. With respect to the contents of this documentation, ASRock Rack does not provide warranty of any kind, either expressed or implied, including but not limited to the implied warranties or conditions of merchantability or fitness for a particular purpose. In no event shall ASRock Rack, its directors, officers, employees, or agents be liable for any indirect, special, incidental, or consequential damages (including damages for loss of profits, loss of business, loss of data, interruption of business and the like), even if ASRock Rack has been advised of the possibility of such damages arising from any defect or error in the documentation or product.
    [Show full text]
  • PCI20EX PCI Express (Pcie)
    PCI20EX PCI Express (PCIe) Bus ARCNET® Network Interface Modules INSTALLATION GUIDE INTRODUCTION The PCI20EX series of ARCNET network interface modules (NIMs) links PCI Express (PCIe) bus compatible computers with the ARCNET local area network (LAN). Since most PC motherboards have migrated from the legacy PCI and PCI-X Bus, a PCI Express style NIM is required. The PCI20EX series is compliant to the PCI Express Card Electromechanical Specification Revision 2.0 and both standard height and low-profile brackets are provided. The PCI Express interface allows for jumperless configuration and Plug and Play operation. The module operates with either an NDIS driver or a null stack driver in a Windows® environment. The PCI20EX incorporates the COM20022 ARCNET controller chip with enhanced features over the earlier generation ARCNET chips. New features include command chaining, sequential access to internal RAM, duplicate node ID detection and variable data rates up to 10 Mbps. Bus contention problems are minimized since the module’s interrupt and I/O base address are assigned through Plug and Play. The PCI20EX exploits the new features of the COM20022 which includes 10 Mbps communications utilizing the various EIA-485 transceiver options. Each PCI20EX module has two LEDs on the board for monitoring network operation and bus access to the module. It is equipped with an 8 position, general purpose DIP switch typically used to assign the ARCNET node address. Ultimately, the node address is configured via software so the DIP switch can also indicate user-defined functions such as data rate, cable interface, or master/slave status of the system.
    [Show full text]
  • M-1: the Mealy Open Source Custom MIDI Controller Student’S Names: Garrett Leung, Darren Mistica Advisor’S Name: Bryan Mealy
    The Mealy Open Source Custom MIDI Controller Computer Engineering CALIFORNIA POLYTECHNIC STATE UNIVERSITY, SAN LUIS OBISPO Advisor Garrett Leung, EE Bryan Mealy June 2015 Darren Mistica, CPE Page 1 ABSTRACT With the high price of large mixing consoles, aspiring artists are restricted to using a mouse to control digital facsimiles of knobs, faders, switches, and buttons. Though using the software controls is considered a simple task, dedicated hardware allows for tactile, visual, and utility. At a low cost, the heart of the MTech M-1 can be customized and placed into any shell with any combination of controls as possible with the underlying platform. Modern MIDI controllers require significant physical space due to their preset button layout and space consuming setups. Despite their high price, modern MIDI controllers have only one setup. With one setup, music producers or artists have a hard time carrying their MIDI controllers around for concerts or other performances. The M-1 MIDI controller addresses the high cost that physical MIDI controllers currently hold on the market by allowing users to make/create their own specific MIDI control board using any combination of knobs, dials, buttons, and sliders. This customization of the controller allows the user to save space and money, while also accommodating for their style or a specific performance. The M-1 controller is an affordable and fully customizable mechanical system. The fully customizable MIDI controller represents a digital MIDI controller while allowing the user to fully customize the physical layout of the controller. Users can place the buttons for the delay, reverb, compression, distortion, etc.
    [Show full text]
  • Datasheet for Onenand Power Ramp and Stabilization Times and for Onenand Boot Copy Times
    TMS320DM365 www.ti.com SPRS457E–MARCH 2009–REVISED JUNE 2011 TMS320DM365 Digital Media System-on-Chip (DMSoC) Check for Samples: TMS320DM365 1 TMS320DM365 Digital Media System-on-Chip (DMSoC) 1.1 Features 12 • Highlights – Support for 32-Bit and 16-Bit – High-Performance Digital Media (Thumb® Mode) Instruction Sets System-on-Chip (DMSoC) – DSP Instruction Extensions and Single Cycle – Up to 300-MHz ARM926EJ-S Clock Rate MAC – Two Video Image Co-processors – ARM® Jazelle® Technology (HDVICP, MJCP) Engines – Embedded ICE-RT Logic for Real-Time – Supports a Range of Encode, Decode, and Debug Video Quality Operations • ARM9 Memory Architecture – Video Processing Subsystem – 16K-Byte Instruction Cache • HW Face Detect Engine – 8K-Byte Data Cache • Resize Engine from 1/16x to 8x – 32K-Byte RAM • 16-Bit Parallel AFE (Analog Front-End) – 16K-Byte ROM Interface Up to 120 MHz – Little Endian • 4:2:2 (8-/16-bit) Interface • Two Video Image Co-processors • 8-/16-bit YCC and Up to 24-Bit RGB888 (HDVICP, MJCP) Engines Digital Output – Support a Range of Encode and Decode • 3 DACs for HD Analog Video Output Operations, up to D1 on 216-MHz device and • Hardware On-Screen Display (OSD) up to 720p on the 270- and 300-MHz parts – Capable of 720p 30fps H.264 video – H.264, MPEG4, MPEG2, MJPEG, JPEG, processing WMV9/VC1 Note: 216-MHz is only capable of D1 • Video Processing Subsystem processing – Front End Provides: – Peripherals include EMAC, USB 2.0 OTG, • HW Face Detect Engine DDR2/NAND, 5 SPIs, 2 UARTs, 2 • Hardware IPIPE for Real-Time Image MMC/SD/SDIO,
    [Show full text]