DOCSLIB.ORG

Datasheet for Onenand Power Ramp and Stabilization Times and for Onenand Boot Copy Times

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Datasheet for Onenand Power Ramp and Stabilization Times and for Onenand Boot Copy Times TMS320DM365 www.ti.com SPRS457E–MARCH 2009–REVISED JUNE 2011 TMS320DM365 Digital Media System-on-Chip (DMSoC) Check for Samples: TMS320DM365 1 TMS320DM365 Digital Media System-on-Chip (DMSoC) 1.1 Features 12 • Highlights – Support for 32-Bit and 16-Bit – High-Performance Digital Media (Thumb® Mode) Instruction Sets System-on-Chip (DMSoC) – DSP Instruction Extensions and Single Cycle – Up to 300-MHz ARM926EJ-S Clock Rate MAC – Two Video Image Co-processors – ARM® Jazelle® Technology (HDVICP, MJCP) Engines – Embedded ICE-RT Logic for Real-Time – Supports a Range of Encode, Decode, and Debug Video Quality Operations • ARM9 Memory Architecture – Video Processing Subsystem – 16K-Byte Instruction Cache • HW Face Detect Engine – 8K-Byte Data Cache • Resize Engine from 1/16x to 8x – 32K-Byte RAM • 16-Bit Parallel AFE (Analog Front-End) – 16K-Byte ROM Interface Up to 120 MHz – Little Endian • 4:2:2 (8-/16-bit) Interface • Two Video Image Co-processors • 8-/16-bit YCC and Up to 24-Bit RGB888 (HDVICP, MJCP) Engines Digital Output – Support a Range of Encode and Decode • 3 DACs for HD Analog Video Output Operations, up to D1 on 216-MHz device and • Hardware On-Screen Display (OSD) up to 720p on the 270- and 300-MHz parts – Capable of 720p 30fps H.264 video – H.264, MPEG4, MPEG2, MJPEG, JPEG, processing WMV9/VC1 Note: 216-MHz is only capable of D1 • Video Processing Subsystem processing – Front End Provides: – Peripherals include EMAC, USB 2.0 OTG, • HW Face Detect Engine DDR2/NAND, 5 SPIs, 2 UARTs, 2 • Hardware IPIPE for Real-Time Image MMC/SD/SDIO, Key Scan Processing – 8 Different Boot Modes and Configurable – Resize Engine Power-Saving Modes – Resize Images From 1/16x to 8x – Pin-to-pin and software compatible with – Separate Horizontal/Vertical DM368 Control – Extended temperature (-40ºC – 85ºC) – Two Simultaneous Output Paths available for 300-MHz device • IPIPE Interface (IPIPEIF) – 3.3-V and 1.8-V I/O, 1.2-V/1.35-V Core • Image Sensor Interface (ISIF) and CMOS – 338-Pin Ball Grid Array at 65nm Process Imager Interface Technology • 16-Bit Parallel AFE (Analog Front End) • High-Performance Digital Media Interface Up to 120 MHz System-on-Chip (DMSoC) • Glueless Interface to Common Video – 216-, 270-, 300-MHz ARM926EJ-S Clock Rate Decoders – Fully Software-Compatible With ARM9™ • BT.601/BT.656/BT.1120 Digital YCbCr – Extended temperature available for 300-MHz 4:2:2 (8-/16-Bit) Interface device • Histogram Module • ARM926EJ-S™ Core • Lens distortion correction module (LDC) 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2009–2011, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. TMS320DM365 SPRS457E–MARCH 2009–REVISED JUNE 2011 www.ti.com • Hardware 3A statistics collection module • Four 64-Bit General-Purpose Timers (each (H3A) configurable as two 32-bit timers) – Back End Provides: • One 64-Bit Watch Dog Timer • Hardware On-Screen Display (OSD) • Two UARTs (One fast UART with RTS and CTS • Composite NTSC/PAL video encoder Flow Control) output • Five Serial Port Interfaces (SPI) each with two • 8-/16-bit YCC and Up to 24-Bit RGB888 Chip-Selects Digital Output • One Master/Slave Inter-Integrated Circuit • 3 DACs for HD Analog Video Output (I2C) Bus™ • LCD Controller • One Multi-Channel Buffered Serial Port • BT.601/BT.656 Digital YCbCr 4:2:2 (McBSP) (8-/16-Bit) Interface – I2S • Analog-to-Digital Convertor (ADC) – AC97 Audio Codec Interface • Power Management and Real Time Clock – S/PDIF via Software Subsystem (PRTCSS) – Standard Voice Codec Interface (AIC12) – Real Time Clock – SPI Protocol (Master Mode Only) • 16-Bit Host-Port Interface (HPI) – Direct Interface to T1/E1 Framers • 10/100 Mb/s Ethernet Media Access Controller – Time Division Multiplexed Mode (TDM) (EMAC) - Digital Media – 128 Channel Mode – IEEE 802.3 Compliant • Four Pulse Width Modulator (PWM) Outputs – Supports Media Independent Interface (MII) • Four RTO (Real Time Out) Outputs – Management Data I/O (MDIO) Module • Up to 104 General-Purpose I/O (GPIO) Pins • Key Scan (Multiplexed with Other Device Functions) • Voice Codec • Boot Modes • External Memory Interfaces (EMIFs) – On-Chip ARM ROM Bootloader (RBL) to Boot – DDR2 and mDDR SDRAM 16-bit wide EMIF From NAND Flash, MMC/SD, UART, USB, With 256 MByte Address Space (1.8-V I/O) SPI, EMAC, or HPI – Asynchronous16-/8-bit Wide EMIF (AEMIF) – AEMIF (NOR and OneNAND) • Flash Memory Interfaces • Configurable Power-Saving Modes – NAND (8-/16-bit Wide Data) • Crystal or External Clock Input (typically – 16 MB NOR Flash, SRAM 19.2 MHz, 24 MHz, 27 MHz or 36 MHz) – OneNAND(16-bit Wide Data) • Flexible PLL Clock Generators • Flash Card Interfaces • Debug Interface Support – Two Multimedia Card (MMC) / Secure Digital – IEEE-1149.1 (JTAG™) (SD/SDIO) Boundary-Scan-Compatible – SmartMedia/xD – ETB (Embedded Trace Buffer) with 4K-Bytes Trace Buffer memory • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels) – Device Revision ID Readable by ARM • USB Port with Integrated 2.0 High-Speed PHY • 338-Pin Ball Grid Array (BGA) Package that Supports (ZCE Suffix), 0.65-mm Ball Pitch – USB 2.0 High-Speed Device • 65nm Process Technology – USB 2.0 High-Speed Host (mini-host, • 3.3-V and 1.8-V I/O, 1.2-V/ 1.35-V Internal supporting one external device) • Community Resources – USB On The Go (HS-USB OTG) – TI E2E Community – TI Embedded Processors Wiki 2 TMS320DM365 Digital Media System-on-Chip (DMSoC) Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 www.ti.com SPRS457E–MARCH 2009–REVISED JUNE 2011 1.2 Description Developers can now deliver pixel-perfect images at up to 720p H.264 at 30fps in their digital video designs without concerns of video format support, constrained network bandwidth, limited system storage capacity or cost with the new TMS320DM365 digital media processor based on DaVinci technology from Texas Instruments Incorporated (TI). With multi-format HD video, the DM365 also features a suite of peripherals saving developers on system costs. This ARM9-based DM365 device offers speeds up to 300 MHz and supports production-qualified H.264, MPEG-4, MPEG-2, MJPEG and VC1/WMV9 codecs providing customers with the flexibility to select the right video codec for their application. These codecs are driven from video accelerators offloading compression needs from the ARM core so that developers can utilize the most performance from the ARM for their application. Video surveillance designers achieve greater compression efficiency providing more storage without straining the network bandwidth. Developers of media playback and camera-driven applications, such as video doorbells, digital signage, digital video recorders, portable media players and more can ensure interoperability as well as product scalability by taking advantage of the full suite of codecs supported on the DM365. Along with multi-format HD video, the DM365 enables seamless interface to most additional external devices required for video applications. The image sensor interface is flexible enough to support CCD, CMOS, and various other interfaces such as BT.656, BT1120. The DM365 also offers a high level of integration with HD display support including, 3 built-in 10-bit HD Analog Video Digital to Analog Converters (DACs), DDR2/mDDR, Ethernet MAC, USB 2.0, integrated audio, Host Port Interface (HPI), Analog to Digital Converter, and many more features saving developers on overall system costs as well as real estate on their circuit boards allowing for a slimmer, sleeker design. Copyright © 2009–2011, Texas Instruments Incorporated TMS320DM365 Digital Media System-on-Chip (DMSoC) 3 Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E–MARCH 2009–REVISED JUNE 2011 www.ti.com 1.3 Functional Block Diagram Figure 1-1 shows the functional block diagram of the TMS320DM365 device. 16Bit DDR2 16-Bit Camera ISIF IPIPE EDMA DDR2/ AFE Resizer Controller mDDR 3A FaceDet LensDist NAND/ VideoFE Buffer NAND/SM OneNAND/ 8/16Bit NORFlash, SDTV/HDTV 3Ch Memory AnalogVideo I/F SmartMedia/ DAC Video xD OSD 16Bit Digital Encoder RGB/YUV VideoBE HPI HostCPU VPSS DMA/DataandConfigurationBus ARMINTC USB2.0HSw/OTG MMC/SD(x2) ARM926EJ-S SPI(x5) HDVICP MJCP UART(x2) I2C I-Cache RAM 16KB 32KB Timer(x4-64b) WDT(x1-64b) D-Cache ROM System 8KB 16KB GIO I/O PWM(x4) Interface RTO McBSP EMAC ADC KeyScan JTAG CLOCKCtrl PRTCSS VoiceCodec I/F PLL 19.2MHz,24MHz 32.768 PMIC/ 27MHzor36MHz kHz SW Figure 1-1. Functional Block Diagram 4 TMS320DM365 Digital Media System-on-Chip (DMSoC) Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 www.ti.com SPRS457E–MARCH 2009–REVISED JUNE 2011 1 TMS320DM365 Digital Media System-on-Chip 6 Peripheral Information and Electrical (DMSoC) ................................................... 1 Specifications .......................................... 76 1.1 Features .............................................. 1 6.1 Parameter Information Device-Specific Information .....................................................
Load more

Recommended publications
  • PCI20EX PCI Express (Pcie)
    PCI20EX PCI Express (PCIe) Bus ARCNET® Network Interface Modules INSTALLATION GUIDE INTRODUCTION The PCI20EX series of ARCNET network interface modules (NIMs) links PCI Express (PCIe) bus compatible computers with the ARCNET local area network (LAN). Since most PC motherboards have migrated from the legacy PCI and PCI-X Bus, a PCI Express style NIM is required. The PCI20EX series is compliant to the PCI Express Card Electromechanical Specification Revision 2.0 and both standard height and low-profile brackets are provided. The PCI Express interface allows for jumperless configuration and Plug and Play operation. The module operates with either an NDIS driver or a null stack driver in a Windows® environment. The PCI20EX incorporates the COM20022 ARCNET controller chip with enhanced features over the earlier generation ARCNET chips. New features include command chaining, sequential access to internal RAM, duplicate node ID detection and variable data rates up to 10 Mbps. Bus contention problems are minimized since the module’s interrupt and I/O base address are assigned through Plug and Play. The PCI20EX exploits the new features of the COM20022 which includes 10 Mbps communications utilizing the various EIA-485 transceiver options. Each PCI20EX module has two LEDs on the board for monitoring network operation and bus access to the module. It is equipped with an 8 position, general purpose DIP switch typically used to assign the ARCNET node address. Ultimately, the node address is configured via software so the DIP switch can also indicate user-defined functions such as data rate, cable interface, or master/slave status of the system.
    [Show full text]
  • Wishbone Bus Architecture – a Survey and Comparison
    International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.2, April 2012 WISHBONE BUS ARCHITECTURE – A SURVEY AND COMPARISON Mohandeep Sharma 1 and Dilip Kumar 2 1Department of VLSI Design, Center for Development of Advanced Computing, Mohali, India [email protected] 2ACS - Division, Center for Development of Advanced Computing, Mohali, India [email protected] ABSTRACT The performance of an on-chip interconnection architecture used for communication between IP cores depends on the efficiency of its bus architecture. Any bus architecture having advantages of faster bus clock speed, extra data transfer cycle, improved bus width and throughput is highly desirable for a low cost, reduced time-to-market and efficient System-on-Chip (SoC). This paper presents a survey of WISHBONE bus architecture and its comparison with three other on-chip bus architectures viz. Advanced Microcontroller Bus Architecture (AMBA) by ARM, CoreConnect by IBM and Avalon by Altera. The WISHBONE Bus Architecture by Silicore Corporation appears to be gaining an upper edge over the other three bus architecture types because of its special performance parameters like the use of flexible arbitration scheme and additional data transfer cycle (Read-Modify-Write cycle). Moreover, its IP Cores are available free for use requiring neither any registration nor any agreement or license. KEYWORDS SoC buses, WISHBONE Bus, WISHBONE Interface 1. INTRODUCTION The introduction and advancement of multimillion-gate chips technology with new levels of integration in the form of the system-on-chip (SoC) design has brought a revolution in the modern electronics industry. With the evolution of shrinking process technologies and increasing design sizes [1], manufacturers are integrating increasing numbers of components on a chip.
    [Show full text]
  • VICTORIA UNIVERSITY of WELLINGTON Te Whare W
    VICTORIAUNIVERSITYOFWELLINGTON Te Whare Wananga¯ o te UpokooteIkaaM¯ aui¯ School of Engineering and Computer Science Te Kura Matai¯ Pukaha,¯ Purorohiko¯ PO Box 600 Tel: +64 4 463 5341 Wellington Fax: +64 4 463 5045 New Zealand Internet: offi[email protected] Development of an IoT System for Environmental Monitoring Jolon Behrent Supervisor: James Quilty Submitted in partial fulfilment of the requirements for Bachelor of Engineering with Honours. Abstract The Greater Wellington Regional Council currently uses data loggers to mon- itor the environment. These loggers and accompanying software are provided by a single supplier which effectively locks the Council into using them for all monitoring. The Council wants to develop a low-cost, open-source Internet of Things solution with a connection to a cloud platform. This report looks at the development of a successful proof-of-concept device capable of reading from sensors and transmitting the data to Azure. Contents 1 Introduction and Background 1 1.1 Introduction . .1 1.1.1 Objective . .1 1.1.2 Overview . .2 1.2 Background . .2 1.2.1 HyQuest Solutions Data Loggers . .2 1.2.2 SDI-12 . .3 2 Design 5 2.1 Design Constraints . .5 2.1.1 Power Consumption . .5 2.1.2 Size . .6 2.1.3 Cost . .6 2.2 Microcontroller Selection . .6 2.3 Modem Selection . .7 2.4 Capacitor Selection . .8 2.5 Regulator Selection . .9 2.6 PCB Design . .9 2.7 Enabling Local Wireless Connection . 10 2.7.1 Reed Switches . 11 2.7.2 Hall Effect Sensors . 11 2.8 SDI-12 Design .
    [Show full text]
  • GS3 Greenhouse Sensor 2365 NE Hopkins Ct / Pullman, WA 99163 USA Volumetric Water Content, Electrical Conductivity, and Temperature
    GS3 Greenhouse Sensor 2365 NE Hopkins Ct / Pullman, WA 99163 USA Volumetric Water Content, Electrical Conductivity, and Temperature APPLICATIONS DESCRIPTION . Greenhouse substrate monitoring. The Decagon GS3 sensor is an accurate tool for . Volumetric water content measurement. monitoring electrical conductivity, volumetric water . Soil/Substrate water balance. content, and temperature in soil and soilless . Irrigation management. substrates. The GS3 determines volumetric water . Electrical Conductivity measurement. content (VWC) by measuring the dielectric constant . Salt management. (εa) of the medium using capacitance / frequency- . Fertilizer movement. domain technology. The sensor uses a 70 MHz . Soil/Substrate temperature measurement. frequency, which minimizes textural and salinity . Modeling processes that are affected by effects, making the GS3 accurate in most soilless temperature. substrates. The GS3 measures temperature using an onboard thermistor, and electrical conductivity using a stainless steel electrode array. ADVANTAGES For a more detailed description of how this sensor . Digital sensor communicates three makes measurements, refer to the User Manual. measurements over a serial interface. 2-probe EC measurement. Robust thermistor for accurate temperature AUDIENCE measurements. Decagon provides the information in this integrators . Low input voltage requirements. guide to help GS3 customers establish . Low power design supports battery-operated communication between these sensors and their data loggers. data acquisition equipment or field data loggers. Robust epoxy encapsulation and stainless Customers using data loggers that support SDI-12 steel needles to resist corrosive environments. sensor communications should consult the user's . Supports SDI-12 or DDI-Serial 1-wire serial manual for their data logger. These sensors are fully communications protocols. integrated into Decagon's system of plug-and-play .
    [Show full text]
  • Parallel I/O Interface
    從微算機原理到系統 宋開泰教授 國立交通大學電機與控制系 工程五館 EE709 Phone：5731865（校內分機：31865） E-mail：[email protected] URL：http://isci.cn.nctu.edu.tw Microcomputer Systems & Lab Microcomputer bus 1 Digital Signal Waveform 1 0 Single-signal waveform 1 0 Multiple-signal waveform Microcomputer Systems & Lab Microcomputer bus 2 Read Timing for External Code Memory Microcomputer Systems & Lab Microcomputer bus 3 Microcomputer BUS • A bus is a set of conducting wires interconnecting the CPU, memory, and I/O devices. • There are three types of bus: Address bus, Data bus and Control bus. There are also utilities in a bus system, such as Vcc and ground lines. • To drive a bus, a bus driver is needed. To receive data from the bus, a bus receiver is needed. The bus driver and bus receiver can be combined to form a bus transceiver. Microcomputer Systems & Lab Microcomputer bus 4 Connecting to a bus • A bus should be driven by no more than one device at any time. Otherwise, bus contention will occur. When bus contention occurs, the devices that are involved in bus contention could be damaged. • A device is disconnected from the bus when the driver-enable and receiver-enable signals are deasserted. When the enable signal is deasserted, the output of the driver or the receiver is in a high-impedance state in which no current flow into or out the device involved. Microcomputer Systems & Lab Microcomputer bus 5 Interconnecting the CPU, Memory, and I/O Devices Memory unit 8 bits 1,048,575 Clock generator 64 672,356 Address Instruction pointer (IP) System address bus Selector/ z System 6 memory 672 356 decoder 5 4 Instruction register 3 2 64 1 Location 0 INC AX Instruction decoder Internal databus System control bus Arithmetic logic unit Memory read Memory write Accumulator I/O write I/O read I/O write I/O read I/O write 26+1=27 System data bus Video monitor I/O devices: Printer keyboard Floppy disk drive z General-purpose registers I/O port Selector/decoder Central processing unit (CPU) Microcomputer Systems & Lab Microcomputer bus 6 System Bus • Internal data bus is used to classify a microprocessor.
    [Show full text]
  • Teros 21 Gen 1 Integrator Guide
    18204-06 6.30.2020 TEROS 21 GEN 1 INTEGRATOR GUIDE SENSOR DESCRIPTION The TEROS 21 Soil Water Potential Sensor measures a wide range of soil water potentials without user maintenance. This dielectric water potential sensor can be packed into a hole, plugged into a data logger, and left to log water potential data. While the TEROS 21 sensor does not have the accuracy of tensiometers, its extended range makes this sensor ideal for measuring the water potential in natural systems or other drier systems where cavitation of tensiometers is a concern. The added temperature measurements can be used to determine approximate soil water potential in frozen soils. NOTE: The TEROS 21 measures the matric component of water potential. For more information on matric potential and the other components of water potential visit Defining water potential. APPLICATIONS • Deficit irrigation monitoring and control • Water potential monitoring in the vadose zone • Crop stress • Waste water drainage studies • Plant water availability • SDI-12 implementation ADVANTAGES • Three-wire sensor interface: power, ground, and data • Digital sensor communicates multiple measurements over a serial interface • Robust thermistor for accurate temperature measurements • Low-input voltage requirements • Low-power design supports battery-operated data loggers • Robust epoxy encapsulation resists corrosive environments • Supports SDI-12 or DDI serial communications protocols • Modern design optimized for low-cost sensing • Does not require a skilled operator • Can measure drier systems where tensiometer cavitation is a concern • Needs no user maintenance Figure 1 TEROS 21 sensor PURPOSE OF THIS GUIDE METER provides the information in this integrator guide to help TEROS 21 Soil Water Potential Sensor customers establish communication between these sensors and their data acquisition equipment or field data loggers.
    [Show full text]
  • Topic 10 Bus Architecture & Interconnects Introductions & Sources
    Introductions & Sources X We will consider a number of issues related to bus architectures in digital systems. Topic 10 X Useful references: • “Bus Architecture of a System on a Chip with User-Configurable System Bus Architecture & Logic”, Steven Winegarden, IEEE JOURNAL OF SOLID-STATE CIRCUITS, Interconnects VOL. 35, NO. 3, MARCH 2000, p425-433. • “AMBA: ENABLING REUSABLE ON-CHIP DESIGNS”, David Flynn, IEEE Micro, July/August 1997. Peter Cheung • AMBA™ Specification (Rev 2.0), ARM Ltd., 1999 Department of Electrical & Electronic Engineering • The CoreConnect Bus Architecture, IBM, Imperial College London http://www.chips.ibm.com/products/coreconnect • VSI Alliance Architecture Document, version 1.0, 1997. • Draft Chapter, “System-on-Chip”, Flynn & Luk URL: www.ee.imperial.ac.uk/pcheung/ E-mail: [email protected] PYKC 6-Mar-08 E3.05 Digital System Design Topic 10 Slide 1 PYKC 6-Mar-08 E3.05 Digital System Design Topic 10 Slide 2 Basic concepts: Basic concepts: Bus basics: order and broadcast properties Cycles, messages and transactions X Communications on buses must be in strict order: serial nature of bus X Buses operate in units of cycles, Messages and transactions. • Cycles: A message requires a number of clock cycles to be sent from sender to receiver over the bus. • Message: These are logical unit of information. For example, a write message contains an address, control signals and the write data. • Transaction: A transaction consists of a sequence of messages which together form a transaction. For example, a memory read X It can broadcast a transaction – sending to multiple components simultaneously requires a memory read message and a reply with the requested data.
    [Show full text]
  • MACE Xci User Manual - 12 - MACE Xci User Manual - 13 - Product Support
    Table of Contents Using the HydroMACE XCi Manual 12 HydroMACE XCi 12 Product Support 14 About MACE 15 WARNINGS 16 Introduction to FloCom+ 17 Introducing the HydroMACE XCi device 18 Installing an HydroMACE XCi device 20 Opening procedure 20 Sensor and power cables routed inside the pole 21 Sensor and power cables routed through conduit 24 Sensor and power cables routed through conduit 28 Installing XCi power options 29 Solar panel installation on a 2" pole 30 Installing a MACE mains powered trickle charger 37 Powering the XCi device with an external battery 38 Introduction to FloSeries3 cards 39 Installing FloSeries3 Cards 40 About the I/O Card 44 Connecting sensors to the I/O card 46 Frequency input 46 Digital or Counter input 46 Shaft encoder input 47 Two-wire 4-20mA input 48 Three-wire 4-20mA input 48 Voltage input 48 Digital output 49 4-20mA output 50 About the WebComm card 51 Preparing and installing a Webcomm card 52 Add a WebComm site on the web 54 Configure a WebComm card using FloCom+ 57 HTTP Upload 58 FTP Upload to In-Situ HydroVu Data Server 60 FTP Upload 61 Edit HydroVu Headers 62 The "WebComm Utility" 66 Test an HTTP Upload 66 Test an FTP Upload 67 Error messages table: 68 Using "AT+ commands" to troubleshoot a WebComm card 70 Initial upload routine: 71 Common AT+ commands 72 Editing/Viewing a WebComm site on the web 75 Site data 75 Download site data 75 Show latest record 76 Delete site data 76 Site details 77 Site Details 77 Site keys 77 Site alarms 78 Site users 78 Remove site 78 Alarm history 79 All about Webcomm SMS/Email
    [Show full text]
  • I2C Manual INTEGRATED CI RCUITS
    AN10216-01 I2C Manual INTEGRATED CI RCUITS APPLICATION NOTE AN10216-01 I2C MANUAL Abstract – The I2C Manual provides a broad overview of the various serial buses, why the I2C bus should be considered, technical detail of the I2C bus and how it works, previous limitations/solutions, comparison to the SMBus, Intelligent Platform Management Interface implementations, review of the different I2C devices that are available and patent/royalty information. The I2C Manual was presented during the 3 hour TecForum at DesignCon 2003 in San Jose, CA on 27 January 2003. Jean-Marc Irazabal – I2C Technical Marketing Manager Steve Blozis – I2C International Product Manager Specialty Logic Product Line Logic Product Group Philips Semiconductors March 24, 2003 1 AN10216-01 I2C Manual TABLE OF CONTENTS TABLE OF CONTENTS...................................................................................................................................................2 OVERVIEW .......................................................................................................................................................................4 DESCRIPTION.....................................................................................................................................................................4 SERIAL BUS OVERVIEW...............................................................................................................................................4 UART OVERVIEW.............................................................................................................................................................6
    [Show full text]
  • Microprocessor Applications Serial Peripheral Interface (SPI)
    7/15/2020 Microprocessor Applications Serial Peripheral Interface (SPI) Dr. Eric Schwartz Christopher Crary Wesley Piard 1 2 General Description of SPI ❖ Serial Peripheral Interface (SPI) is a synchronous serial communication interface that was originally defined by Motorola. ❖ It is one of the most common serial communication interfaces, and it is typically utilized by components such as sensors, memory, etc. ❖ It is generally chosen for applications where short-distance, full- duplex communication is required. Dr. Eric Schwartz | Christopher Crary | Wesley Piard 2 1 7/15/2020 3 General Description of SPI ❖ A SPI bus consists of a single “master” device that can communicate with at least one “slave” device. ❖ Only the master device can initiate some transfer of data. ❖ The master device can only communicate with a single slave device at any given time. ❖ In some unique cases, a master can transmit data to multiple slaves simultaneously. ❖ In some other serial communication protocols such as I2C, multiple master devices can exist simultaneously on the same bus. ➢ This, however, is one of the reasons SPI generally has higher data transmission rates than I2C. Dr. Eric Schwartz | Christopher Crary | Wesley Piard 3 4 Interface – Signals The standard set of signals for SPI is as follows: ❖ Chip Select (CS) – Indicates when an individual slave device should be “enabled” or should begin accepting data. Also commonly called “slave select” or SS. ❖ Master-out Slave-in (MOSI) – Data that is sent from the “master” device to the “slave” device. ❖ Master-in Slave-out (MISO) – Data that is sent from the “slave” device to the “master” device.
    [Show full text]
  • PCI System Architecture Fourth Edition
    world-class technical training Are your company’s technical training needs being addressed in the most effective manner? MindShare has over 25 years experience in conducting technical training on cutting-edge technologies. We understand the challenges companies have when searching for quality, effective training which reduces the students’ time away from work and provides cost-effective alternatives. MindShare offers many fl exible solutions to meet those needs. Our courses are taught by highly-skilled, enthusiastic, knowledgeable and experienced instructors. We bring life to knowledge through a wide variety of learning methods and delivery options. training that fi ts your needs MindShare recognizes and addresses your company’s technical training issues with: • Scalable cost training • Customizable training options • Reducing time away from work • Just-in-time training • Overview and advanced topic courses • Training delivered effectively globally • Training in a classroom, at your cubicle or home offi ce • Concurrently delivered multiple-site training MindShare training courses expand your technical skillset 2 PCI Express 2.0 ® 2 Serial Attached SCSI (SAS) 2 Intel Core 2 Processor Architecture 2 DDR2/DDR3 DRAM Technology 2 AMD Opteron Processor Architecture 2 PC BIOS Firmware 2 Intel 64 and IA-32 Software Architecture 2 High-Speed Design 2 Intel PC and Chipset Architecture 2 Windows Internals and Drivers 2 PC Virtualization 2 Linux Fundamentals 2 USB 2.0 ... and many more. 2 Wireless USB All courses can be customized to meet your 2 Serial
    [Show full text]
  • RS485 2 Click PID: MIKROE-2700
    RS485 2 click PID: MIKROE-2700 RS485 2 click is an RS422/485 transceiver Click board™, which can be used as an interface between the TTL level UART and the RS422/485 communication bus. It features a half-duplex communication capability, true failsafe receiver input, driver output protection, low power consumption, 3.3V and 5V compatibility, and more. It is well suited for transmitting smaller blocks of data over long distances and noisy areas using the twisted pair bus, allowing for half-duplex communication, especially in low power RS485/422 applications. Reduced slew rate drivers minimize electromagnetic interference radiation and reduce reflections if the RS422/485 bus is not properly terminated. Due to its reliability and robustness, the RS485 2 click can be used in various applications that require reliable data transfer in various noisy environments, or over a substantial distance, when data rate transfer up to 64 kbps is sufficient. Featuring very low power consumption, it can also be used with the battery powered RS485/422 applications. RS485 2 click can be used for controlling various building automation systems, battery-powered differential communicators, remote meter reading applications, and various other battery operated or portable devices, which need to establish a reliable communication over the RS422/485 bus. How the click works RS485 2 click uses the MAX3471, an RS-422/485, half-duplex, differential transceiver for battery-powered systems, from Maxim Integrated. This click is intended to be used as a physical layer device, often referred to as PHY, providing physical interfacing of the MCU TTL level UART lines with the RS422/485 bus.
    [Show full text]