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NS9210 Hardware Reference

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NS9210 Hardware Reference NS9210 Hardware Reference 90000846_K 10/5/2011 ©2010 Digi International Inc. Printed in the United States of America. All rights reserved. Digi, Digi International, the Digi logo, a Digi International Company, ConnectCore, NET+, NET+OS and NET+Works are trademarks or registered trademarks of Digi International, Inc. in the United States and other countries worldwide. All other trademarks are the property of their respective owners. Information in this document is subject to change without notice and does not represent a commitment on the part of Digi International. Digi provides this document “as is,” without warranty of any kind, either expressed or implied, including, but not limited to, the implied warranties of fitness or merchantability for a particular purpose. Digi may make improvements and/or changes in this manual or in the product(s) and/or the program(s) described in this manual at any time. This product could include technical inaccuracies or typographical errors. Changes are made periodically to the information herein; these changes may be incorporated in new editions of the publication. Contents Chapter 1: Contents .......................................................... 3 Chapter 2: Pinout (177) .................................................... 23 The Legend...............................................................................23 Memory bus interface .........................................................................24 Ethernet interface MAC .......................................................................27 General purpose I/O (GPIO)..................................................................27 System clock....................................................................................34 System mode ...................................................................................35 System reset ....................................................................................36 Reset Behavior ..........................................................................36 JTAG Test .......................................................................................37 Power and ground .............................................................................38 Chapter 3: I/O Control Module .......................................... 39 System memory bus I/O control ......................................................39 Control and Status registers..................................................................39 Register address map...................................................................39 GPIO Configuration registers .................................................................41 GPIO configuration options ............................................................41 GPIO Configuration Register #0 .......................................................42 GPIO Configuration Register #1 .......................................................42 GPIO Configuration Register #2 .......................................................43 GPIO Configuration Register #3 .......................................................43 GPIO Configuration Register #4 .......................................................44 GPIO Configuration Register #5 .......................................................44 GPIO Configuration Register #6 .......................................................45 GPIO Configuration Register #7 .......................................................45 GPIO Configuration Register #8 .......................................................46 GPIO Configuration Register #9 .......................................................46 GPIO Configuration Register #10 .....................................................47 GPIO Configuration Register #11 .....................................................47 GPIO Configuration Register #12 .....................................................48 GPIO Configuration Register #13 .....................................................48 GPIO Control registers ........................................................................49 GPIO Control Register #0 ..............................................................49 GPIO Control Register #1 ..............................................................50 GPIO Control Register #2 ..............................................................51 GPIO Status registers ..........................................................................51 GPIO Status Register #0 ................................................................51 www.digiembedded.com 3 CONTENTS GPIO Status Register #1................................................................ 52 GPIO Status Register #2................................................................ 53 Memory Bus Configuration register ......................................................... 54 Chapter 4: Working with the CPU ....................................... 56 About the processor .................................................................... 56 Arm926EJ-S process block diagram .................................................. 57 Instruction sets ................................................................................ 57 ARM instruction set..................................................................... 57 Thumb instruction set.................................................................. 57 Java instruction set .................................................................... 58 System control processor (CP15) registers................................................. 58 ARM926EJ-S system addresses ........................................................ 58 Address manipulation example ....................................................... 58 Accessing CP15 registers............................................................... 58 Terms and abbreviations .............................................................. 59 Register summary....................................................................... 60 R0: ID code and cache type status registers .............................................. 61 R0: ID code .............................................................................. 61 R0: Cache type register................................................................ 61 Cache type register and field description .......................................... 62 Dsize and Isize fields ................................................................... 62 R1: Control register ........................................................................... 64 Control register ......................................................................... 64 Bit functionality......................................................................... 64 ICache and DCache behavior.......................................................... 66 R2: Translation Table Base register ........................................................ 67 Register format ......................................................................... 67 R3: Domain Access Control register ........................................................ 67 Register format ......................................................................... 67 Access permissions and instructions ................................................. 67 R4 register ...................................................................................... 68 R5: Fault Status registers .................................................................... 68 Access instructions ..................................................................... 68 Register format ......................................................................... 68 Register bits ............................................................................. 68 Status and domain fields .............................................................. 69 R6: Fault Address register.................................................................... 69 Access instructions ..................................................................... 69 R7: Cache Operations register............................................................... 70 Write instruction........................................................................ 70 Cache functions ......................................................................... 70 Cache operation functions ............................................................ 71 Modified virtual address format (MVA) .............................................. 72 4 Hardware Reference NS9210 Set/Way format .........................................................................72 Set/Way example .......................................................................72 Test and clean DCache instructions..................................................72 Test, clean, and invalidate DCache instruction ....................................73 R8:TLB Operations register...................................................................73 TLB operations ..........................................................................73 TLB operation instructions ............................................................73 Modified virtual address format (MVA) ..............................................74 R9: Cache Lockdown register ................................................................74 Cache ways...............................................................................74 Instruction or data lockdown register ...............................................75
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