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SCV64™ User Manual

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SCV64™ User Manual SCV64™ User Manual http://www.silicon360.com The information in this document is subject to change without notice and should not be construed as a commitment by Silicon360. While reasonable precautions have been taken, Silicon360 assumes no responsibility for any errors that may appear in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Silicon360. These products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the product could create a situation where personal injury or death may occur. Should Buyer purchase or use these products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon360 and its officers, employees, subsidiaries, affiliates and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Silicon360 was negligent regarding the design or manufacture of the part. The acceptance of this document will be construed as an acceptance of the foregoing conditions. SCV64™ User Manual Copyright 2013, Silicon360 All rights reserved. Table of Contents 1 General Information ............................................................................................ 1-1 1.1 Introduction............................................................................................. 1-1 1.2 Product Overview ................................................................................... 1-1 1.2.1 Flexibility and Features.......................................................... 1-1 1.3 Using This Document ............................................................................. 1-4 1.4 Conventions ............................................................................................ 1-5 1.4.1 Signals.................................................................................... 1-5 1.4.2 Symbols.................................................................................. 1-5 1.4.3 Mathematical Notation........................................................... 1-5 2 Functional Description......................................................................................... 2-1 2.1 Introduction............................................................................................. 2-1 2.1.1 Organization of the Functional Description........................... 2-1 2.1.2 Functional Overview.............................................................. 2-2 2.1.2.1 Data Path ............................................................................... 2-2 2.1.2.2 VMEbus Interface ................................................................. 2-5 2.1.2.3 Local Bus Interface ............................................................... 2-6 2.2 VMEbus Requester ................................................................................. 2-8 2.2.1 Function.................................................................................. 2-8 2.2.2 Bus Request Modes................................................................ 2-9 2.2.2.1 Fair and Demand Modes ....................................................... 2-9 2.2.2.2 VMEbus Request Levels....................................................... 2-9 2.2.3 Bus Release Modes .............................................................. 2-10 2.2.3.1 Bus Clear Enabling ............................................................. 2-10 2.2.3.2 Release On Request and Release When Done.................... 2-10 2.2.3.3 Ownership Timer ................................................................ 2-11 2.2.4 Other Bus Release Mechanisms........................................... 2-11 2.2.4.1 Local Memory Interrupt...................................................... 2-11 2.2.4.2 BI-Mode .............................................................................. 2-12 iii 2.2.4.3 Local and System Reset....................................................... 2-12 2.3 Interrupter .............................................................................................. 2-13 2.3.1 VMEbus Interrupts ...............................................................2-13 2.3.1.1 Interrupt Generation............................................................. 2-13 2.3.1.2 BI-mode Effects................................................................... 2-14 2.3.1.3 Reset Effects ........................................................................ 2-14 2.3.2 Local Bus Interrupts..............................................................2-15 2.4 Interrupt Handler ................................................................................... 2-18 2.4.1 Interrupt Enabling and Status ...............................................2-20 2.4.1.1 Local Interrupt Level Mapping............................................ 2-21 2.4.2 Interrupt Acknowledge Cycles .............................................2-22 2.4.2.1 Auto-Vectored Interrupts..................................................... 2-25 2.4.2.2 Vectored Interrupts .............................................................. 2-26 2.4.2.3 BI-Mode Effects .................................................................. 2-29 2.4.2.4 Reset Effects ........................................................................ 2-29 2.5 System Controller Functions ................................................................. 2-30 2.5.1 Syscon Determination...........................................................2-30 2.5.2 IACK Daisy Chain Driver ....................................................2-31 2.5.3 VMEbus Arbiter ...................................................................2-31 2.5.3.1 Arbitration Modes............................................................... 2-31 2.5.3.2 Arbitration Time-out............................................................ 2-33 2.5.3.3 Reset Effects ........................................................................ 2-33 2.5.4 Bus Timer .............................................................................2-34 2.5.5 System Clock Driver.............................................................2-34 2.5.6 External Inputs......................................................................2-34 2.5.6.1 External Status ..................................................................... 2-34 2.5.6.2 Off-Board Reset Input ......................................................... 2-35 2.5.7 Reset Effects on Syscon Functions.......................................2-35 2.6 Data Path................................................................................................ 2-36 2.6.1 SCV64 as VME Slave...........................................................2-39 2.6.1.1 Coupled Mode...................................................................... 2-39 iv 2.6.1.2 Decoupled Mode ................................................................. 2-39 2.6.2 SCV64 as VME Master........................................................ 2-41 2.6.2.1 Coupled Mode..................................................................... 2-41 2.6.2.2 Decoupled Mode ................................................................. 2-42 2.6.2.3 DMA Transfers ................................................................... 2-43 2.7 Memory Mapping ................................................................................. 2-45 2.7.1 CPU Memory Map............................................................... 2-45 2.7.2 VME Slave Memory Map.................................................... 2-49 2.7.2.1 Automatic Base Address Programming.............................. 2-51 2.7.2.2 Access Protection ................................................................ 2-52 2.8 VMEbus Interface................................................................................. 2-53 2.8.1 SCV64 as VME Master........................................................ 2-53 2.8.1.1 Address Translation ............................................................ 2-53 2.8.1.2 Byte Lane Translation......................................................... 2-54 2.8.1.3 VMEbus Mastership............................................................ 2-56 2.8.1.4 RMW Cycles....................................................................... 2-57 2.8.1.5 Termination of a Master Cycle with RETRY* ................... 2-58 2.8.2 SCV64 as VME Slave.......................................................... 2-58 2.8.2.1 Address Translation ............................................................ 2-58 2.8.2.2 Byte Lane Translation......................................................... 2-59 2.8.2.3 Local Bus Mastership.......................................................... 2-60 2.8.3 DMA Transfers .................................................................... 2-61 2.8.4 Master/Slave Deadlock Resolution...................................... 2-61 2.8.5 Location Monitor Access ..................................................... 2-62 2.8.6 Bus Busy Glitch ................................................................... 2-63 2.8.7 BI-Mode Effects................................................................... 2-63 2.8.8 Bus Error Handling .............................................................
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