I2C-Bus Specification and User Manual Rev
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Humidity & Temperature Sensor
Humidity & Temperature Sensor AM2322 Product Manuals product Features Super Mini Size Easy Protable Ultra-Low Power State Ultra-low voltage work Excellent long-term stability StandardI2C And single bus output 一、 Product Overview AM2322 The digital temperature and humidity sensor is a kind of temperature and humidity composite sensor with the output of calibrated digitalsignal.The special temperature and humidity collection technology is adopted to ensure the high reliability and long-term stability of the product.The sensor includes a capacitive sensing element and a high-precision integrated temperature measurement element, which is connected to a high- performance microprocessor.The product has high quality, super fast response, strong anti-interference ability and high cost performance. AM2322 communication mode adopts single bus, standard I squared C communication mode.Standard single bus interface makes system integration easy and fast.The super small volume, extremely low power consumption, the signal transmission distance can reach up to 20 meters, making it the best choice for all kinds of Two kinds of communication mode is used directly output after applications and even the most demanding applications.The I temperature compensation, humidity, temperature and the CRC squared C communication mode adopts standard communication check and other digital information, users need to secondary timing, and the user can be directly attached to the I squared C calculation of digital output, also need not to compensate the communication bus, with no additional wiring and simple use. temperature humidity, accurate temperature and humidity information can be got.The two modes of communication are free to switch, users are free to choose, easy to use, and should be widely used.The product is 4 lead wire and convenient connection. -
Allgemeines Abkürzungsverzeichnis
Allgemeines Abkürzungsverzeichnis L. -
Dell EMC Poweredge T340 Technical Guide
Dell EMC PowerEdge T340 Technical Guide Regulatory Model: E60S Regulatory Type: E60S001 Dec. 2020 Rev. A07 Notes, cautions, and warnings NOTE: A NOTE indicates important information that helps you make better use of your product. CAUTION: A CAUTION indicates either potential damage to hardware or loss of data and tells you how to avoid the problem. WARNING: A WARNING indicates a potential for property damage, personal injury, or death. © 2018 - 2020 Dell Inc. or its subsidiaries. All rights reserved. Dell, EMC, and other trademarks are trademarks of Dell Inc. or its subsidiaries. Other trademarks may be trademarks of their respective owners. 1 Product Overview Topics: • Introduction • New technologies Introduction The Dell EMC PowerEdge T340 is the reliable, easy to manage, and scalable 1-socket tower server for growing businesses and remote offices/ branch offices. New technologies The PowerEdge T340 equipped with Intel® Xeon® E-2100 and E-2200 product family processors support to help run applications faster and support for full-feature remote management (iDRAC9). The T340 is versatile enough to address many customer segments and workloads. Target workloads include ● Small and medium businesses and organizations: Collaboration/sharing productivity applications, databases, web serving, backup/recovery, and mail and messaging. ● ROBO: Applications and workloads specific to the particular industry, e.g. Retail, Healthcare, Finance, Education, etc. The following table shows the list of new technologies offered by the PowerEdge T340: New Technologies Detailed Descriptions Intel® C246 series chipset Please refer to the chipset section for details. Intel® Xeon® processor E- 2100 and E-2200 Product The Intel® processor that works with Intel® C246 series Family chipset. -
3. System Management Bus
Input/Output Systems and Peripheral Devices 1 3. SYSTEM MANAGEMENT BUS This laboratory work presents the System Management Bus (SMBus). After an over- view of SMBus, bit and data transfers are described, the bus arbitration procedure is present- ed, the differences between SMBus and the I2C bus are highlighted, and several command protocols are detailed. Next, the Intel SMBus controller is presented, including its registers and commands, as well as its use with I2C devices. The applications aim to detect the devices connected to the computer’s SMBus, read the contents of SPD memories present in the sys- tem, and decode the contents of these memories. 3.1. Overview of SMBus System Management Bus (SMBus) is a simple serial bus with only two signal lines. This bus can be used for communication between various system devices and between these devices and the rest of a system. The operating principles of SMBus are similar to those of the I2C bus. There are, however, several differences between the two buses, differences which will be presented later. SMBus represents a control bus for system management and power management op- erations. A system may use the SMBus to transfer messages to and from various devices in- stead of using individual control lines, which allows to reduce pin count and interconnection wires. A device may use the SMBus to provide manufacturer information, provide the device model number, report different types of errors, accept control parameters, and return the de- vice status. SMBus was initially proposed by Intel as a link between an intelligent battery, a charger for the battery and a microcontroller that communicates with the rest of the system. -
Tms320f28004x Microcontrollers Datasheet (Rev. F)
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045, TMS320F280049, TMS320F280049C,TMS320F280041, TMS320F280041C, TMS320F280048, TMS320F280048C,TMS320F280040, TMS320F280040C TMS320F280045, www.ti.com TMS320F280041, TMS320F280041C,SPRS945F –TMS320F280040, JANUARY 2017 – REVISED TMS320F280040C FEBRUARY 2021 SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021 TMS320F28004x Microcontrollers 1 Features – Embedded Real-time Analysis and Diagnostic (ERAD) • TMS320C28x 32-bit CPU • Communications peripherals – 100 MHz – One Power-Management Bus (PMBus) – IEEE 754 single-precision Floating-Point Unit interface (FPU) – One Inter-integrated Circuit (I2C) interface – Trigonometric Math Unit (TMU) (pin-bootable) • 3×-cycle to 4×-cycle improvement for – Two Controller Area Network (CAN) bus ports common trigonometric functions versus (pin-bootable) software libraries – Two Serial Peripheral Interface (SPI) ports • 13-cycle Park transform (pin-bootable) – Viterbi/Complex Math Unit (VCU-I) – Two Serial Communication Interfaces (SCIs) – Ten hardware breakpoints (with ERAD) (pin-bootable) • Programmable Control Law Accelerator (CLA) – One Local Interconnect Network (LIN) – 100 MHz – One Fast Serial Interface (FSI) with a – IEEE 754 single-precision floating-point transmitter and receiver instructions • Analog system – Executes code independently of main CPU – Three 3.45-MSPS, 12-bit Analog-to-Digital • On-chip memory Converters (ADCs) – 256KB (128KW) of flash (ECC-protected) • Up to 21 external channels across two independent banks -
CP2725AC54TE Compact Power Line High Efficiency Rectifier 100-120/200-277VAC Input; Default Outputs: ±54VDC @ 2725W, 5VDC @ 4W
GE Data Sheet CP2725AC54TE Compact Power Line High Efficiency Rectifier 100-120/200-277VAC input; Default Outputs: ±54VDC @ 2725W, 5VDC @ 4W RoHS Compliant Features • Efficiency 96.2% • Compact 1RU form factor with 30 W/in3 density • Constant power from 52 – 58VDC • 2725W from nominal 200 – 277VAC • 1200W from nominal 100 – 120VAC • Output voltage programmable from 42V – 58VDC • PMBus compliant dual I2C and RS485 serial busses • Isolated +5V Aux, signals and I2C communications • Power factor correction (meets EN/IEC 61000-3-2 and EN 60555-2 requirements) Applications • Output overvoltage and overload protection • 48VDC distributed power architectures • AC Input overvoltage and undervoltage protection • Routers/Switches • Over-temperature warning and protection • VoIP/Soft Switches • Redundant, parallel operation with active load sharing • LAN/WAN/MAN applications • Remote ON/OFF • File servers • Internally controlled Variable-speed fan • Indoor wireless • Hot insertion/removal (hot plug) • Telecommunications equipment • Four front panel LED indicators • Enterprise Networks • UL* Recognized to UL60950-1, CAN/ CSA† C22.2 No. • SAN/NAS/iSCSI applications 60950-1, and VDE‡ 0805-1 Licensed to IEC60950-1 § • CE mark meets 2006/95/EC directive • RoHS Directive 2011/65/EU and amended Directive (EU) 2015/863 Description • Conformally coated option The CP2725AC54TE Rectifier provides significant efficiency improvements in the Compact Power Line platform of Rectifiers. High- density front-to-back airflow is designed for minimal space utilization and is highly expandable for future growth. The wide-input standard product is designed to be deployed internationally. It is configured with both RS485 and dual-redundant I2C communications busses that allow it to be used in a broad range of applications. -
EPC612D8A-TB EPC612D8A EPC612D8 User Manual
EPC612D8A-TB EPC612D8A EPC612D8 User Manual Version 1.1 Published August 2016 Copyright©2016 ASRock Rack INC. All rights reserved. Version 1.1 Published October 2016 Copyright©2016 ASRock Rack Inc. All rights reserved. Copyright Notice: No part of this documentation may be reproduced, transcribed, transmitted, or translated in any language, in any form or by any means, except duplication of documentation by the purchaser for backup purpose, without written consent of ASRock Rack Inc. Products and corporate names appearing in this documentation may or may not be registered trademarks or copyrights of their respective companies, and are used only for identification or explanation and to the owners’ benefit, without intent to infringe. Disclaimer: Specifications and information contained in this documentation are furnished for informational use only and subject to change without notice, and should not be constructed as a commitment by ASRock Rack. ASRock Rack assumes no responsibility for any errors or omissions that may appear in this documentation. With respect to the contents of this documentation, ASRock Rack does not provide warranty of any kind, either expressed or implied, including but not limited to the implied warranties or conditions of merchantability or fitness for a particular purpose. In no event shall ASRock Rack, its directors, officers, employees, or agents be liable for any indirect, special, incidental, or consequential damages (including damages for loss of profits, loss of business, loss of data, interruption of business and the like), even if ASRock Rack has been advised of the possibility of such damages arising from any defect or error in the documentation or product. -
PCI20EX PCI Express (Pcie)
PCI20EX PCI Express (PCIe) Bus ARCNET® Network Interface Modules INSTALLATION GUIDE INTRODUCTION The PCI20EX series of ARCNET network interface modules (NIMs) links PCI Express (PCIe) bus compatible computers with the ARCNET local area network (LAN). Since most PC motherboards have migrated from the legacy PCI and PCI-X Bus, a PCI Express style NIM is required. The PCI20EX series is compliant to the PCI Express Card Electromechanical Specification Revision 2.0 and both standard height and low-profile brackets are provided. The PCI Express interface allows for jumperless configuration and Plug and Play operation. The module operates with either an NDIS driver or a null stack driver in a Windows® environment. The PCI20EX incorporates the COM20022 ARCNET controller chip with enhanced features over the earlier generation ARCNET chips. New features include command chaining, sequential access to internal RAM, duplicate node ID detection and variable data rates up to 10 Mbps. Bus contention problems are minimized since the module’s interrupt and I/O base address are assigned through Plug and Play. The PCI20EX exploits the new features of the COM20022 which includes 10 Mbps communications utilizing the various EIA-485 transceiver options. Each PCI20EX module has two LEDs on the board for monitoring network operation and bus access to the module. It is equipped with an 8 position, general purpose DIP switch typically used to assign the ARCNET node address. Ultimately, the node address is configured via software so the DIP switch can also indicate user-defined functions such as data rate, cable interface, or master/slave status of the system. -
Datasheet for Onenand Power Ramp and Stabilization Times and for Onenand Boot Copy Times
TMS320DM365 www.ti.com SPRS457E–MARCH 2009–REVISED JUNE 2011 TMS320DM365 Digital Media System-on-Chip (DMSoC) Check for Samples: TMS320DM365 1 TMS320DM365 Digital Media System-on-Chip (DMSoC) 1.1 Features 12 • Highlights – Support for 32-Bit and 16-Bit – High-Performance Digital Media (Thumb® Mode) Instruction Sets System-on-Chip (DMSoC) – DSP Instruction Extensions and Single Cycle – Up to 300-MHz ARM926EJ-S Clock Rate MAC – Two Video Image Co-processors – ARM® Jazelle® Technology (HDVICP, MJCP) Engines – Embedded ICE-RT Logic for Real-Time – Supports a Range of Encode, Decode, and Debug Video Quality Operations • ARM9 Memory Architecture – Video Processing Subsystem – 16K-Byte Instruction Cache • HW Face Detect Engine – 8K-Byte Data Cache • Resize Engine from 1/16x to 8x – 32K-Byte RAM • 16-Bit Parallel AFE (Analog Front-End) – 16K-Byte ROM Interface Up to 120 MHz – Little Endian • 4:2:2 (8-/16-bit) Interface • Two Video Image Co-processors • 8-/16-bit YCC and Up to 24-Bit RGB888 (HDVICP, MJCP) Engines Digital Output – Support a Range of Encode and Decode • 3 DACs for HD Analog Video Output Operations, up to D1 on 216-MHz device and • Hardware On-Screen Display (OSD) up to 720p on the 270- and 300-MHz parts – Capable of 720p 30fps H.264 video – H.264, MPEG4, MPEG2, MJPEG, JPEG, processing WMV9/VC1 Note: 216-MHz is only capable of D1 • Video Processing Subsystem processing – Front End Provides: – Peripherals include EMAC, USB 2.0 OTG, • HW Face Detect Engine DDR2/NAND, 5 SPIs, 2 UARTs, 2 • Hardware IPIPE for Real-Time Image MMC/SD/SDIO, -
SBIR Program Document
Topic Index and Description A20-101 Continuous Flow Recrystallization of Energetic Nitramines A20-102 Deep Neural Network Learning Based Tools for Embedded Systems Under Side Channel Attacks A20-103 Beyond Li-Ion Batteries in Electric Vehicles (EV) A20-104 Wireless Power transfer A20-105 Direct Wall Shear Stress Measurement for Rotor Blades A20-106 Electronically-Tunable, Low Loss Microwave Thin-film Ferroelectric Phase-Shifter A20-107 Automated Imagery Annotation and Segmentation for Military Tactical Objects A20-108 Multi-Solution Precision Location Determination System to be Operational in a Global Positioning System (GPS) Denied Environment for Static, Dynamic and Autonomous Systems under Test A20-109 Environmentally Adaptive Free-Space Optical Communication A20-110 Localized High Bandwidth Wireless Secure Mesh Network A20-111 Non-Destructive Evaluation of Bonded Interface of Cold Spray Additive Repair A20-112 Compact, High Performance Engines for Air Launched Effects UAS A20-113 Optical Based Health Usage and Monitoring System (HUMS) A20-114 3-D Microfabrication for In-Plane Optical MEMS Inertial Sensors A20-115 Using Artificial Intelligence to Optimize Missile Sustainment Trade-offs A20-116 Distributed Beamforming for Non-Developmental Waveforms A20-117 Lens Antennas for Resilient Satellite Communications (SATCOM) on Ground Tactical Vehicles A20-118 Novel, Low SWaP-C Unattended Ground Sensors for Relevant SA in A2AD Environments A20-119 Efficient Near Field Charge Transfer Mediated Infrared Detectors A20-120 Very Small Pixel Uncooled -
Wishbone Bus Architecture – a Survey and Comparison
International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.2, April 2012 WISHBONE BUS ARCHITECTURE – A SURVEY AND COMPARISON Mohandeep Sharma 1 and Dilip Kumar 2 1Department of VLSI Design, Center for Development of Advanced Computing, Mohali, India [email protected] 2ACS - Division, Center for Development of Advanced Computing, Mohali, India [email protected] ABSTRACT The performance of an on-chip interconnection architecture used for communication between IP cores depends on the efficiency of its bus architecture. Any bus architecture having advantages of faster bus clock speed, extra data transfer cycle, improved bus width and throughput is highly desirable for a low cost, reduced time-to-market and efficient System-on-Chip (SoC). This paper presents a survey of WISHBONE bus architecture and its comparison with three other on-chip bus architectures viz. Advanced Microcontroller Bus Architecture (AMBA) by ARM, CoreConnect by IBM and Avalon by Altera. The WISHBONE Bus Architecture by Silicore Corporation appears to be gaining an upper edge over the other three bus architecture types because of its special performance parameters like the use of flexible arbitration scheme and additional data transfer cycle (Read-Modify-Write cycle). Moreover, its IP Cores are available free for use requiring neither any registration nor any agreement or license. KEYWORDS SoC buses, WISHBONE Bus, WISHBONE Interface 1. INTRODUCTION The introduction and advancement of multimillion-gate chips technology with new levels of integration in the form of the system-on-chip (SoC) design has brought a revolution in the modern electronics industry. With the evolution of shrinking process technologies and increasing design sizes [1], manufacturers are integrating increasing numbers of components on a chip. -
Intel® Agilex™ Device Data Sheet
Intel® Agilex™ Device Data Sheet Subscribe DS-1060 | 2021.06.02 Send Feedback Latest document on the web: PDF | HTML Contents Contents Intel® Agilex™ Device Data Sheet............................................................................................................................................... 3 Electrical Characteristics...................................................................................................................................................... 5 Operating Conditions..................................................................................................................................................5 Switching Characteristics....................................................................................................................................................27 Core Performance Specifications.................................................................................................................................28 Periphery Performance Specifications.......................................................................................................................... 37 E-Tile Transceiver Performance Specifications...............................................................................................................46 P-Tile Transceiver Performance Specifications...............................................................................................................50 R-Tile Transceiver Performance Specifications...............................................................................................................55