SBIR Program Document
Total Page:16
File Type:pdf, Size:1020Kb
Load more
Recommended publications
-
Allgemeines Abkürzungsverzeichnis
Allgemeines Abkürzungsverzeichnis L. -
Dell EMC Poweredge T340 Technical Guide
Dell EMC PowerEdge T340 Technical Guide Regulatory Model: E60S Regulatory Type: E60S001 Dec. 2020 Rev. A07 Notes, cautions, and warnings NOTE: A NOTE indicates important information that helps you make better use of your product. CAUTION: A CAUTION indicates either potential damage to hardware or loss of data and tells you how to avoid the problem. WARNING: A WARNING indicates a potential for property damage, personal injury, or death. © 2018 - 2020 Dell Inc. or its subsidiaries. All rights reserved. Dell, EMC, and other trademarks are trademarks of Dell Inc. or its subsidiaries. Other trademarks may be trademarks of their respective owners. 1 Product Overview Topics: • Introduction • New technologies Introduction The Dell EMC PowerEdge T340 is the reliable, easy to manage, and scalable 1-socket tower server for growing businesses and remote offices/ branch offices. New technologies The PowerEdge T340 equipped with Intel® Xeon® E-2100 and E-2200 product family processors support to help run applications faster and support for full-feature remote management (iDRAC9). The T340 is versatile enough to address many customer segments and workloads. Target workloads include ● Small and medium businesses and organizations: Collaboration/sharing productivity applications, databases, web serving, backup/recovery, and mail and messaging. ● ROBO: Applications and workloads specific to the particular industry, e.g. Retail, Healthcare, Finance, Education, etc. The following table shows the list of new technologies offered by the PowerEdge T340: New Technologies Detailed Descriptions Intel® C246 series chipset Please refer to the chipset section for details. Intel® Xeon® processor E- 2100 and E-2200 Product The Intel® processor that works with Intel® C246 series Family chipset. -
3. System Management Bus
Input/Output Systems and Peripheral Devices 1 3. SYSTEM MANAGEMENT BUS This laboratory work presents the System Management Bus (SMBus). After an over- view of SMBus, bit and data transfers are described, the bus arbitration procedure is present- ed, the differences between SMBus and the I2C bus are highlighted, and several command protocols are detailed. Next, the Intel SMBus controller is presented, including its registers and commands, as well as its use with I2C devices. The applications aim to detect the devices connected to the computer’s SMBus, read the contents of SPD memories present in the sys- tem, and decode the contents of these memories. 3.1. Overview of SMBus System Management Bus (SMBus) is a simple serial bus with only two signal lines. This bus can be used for communication between various system devices and between these devices and the rest of a system. The operating principles of SMBus are similar to those of the I2C bus. There are, however, several differences between the two buses, differences which will be presented later. SMBus represents a control bus for system management and power management op- erations. A system may use the SMBus to transfer messages to and from various devices in- stead of using individual control lines, which allows to reduce pin count and interconnection wires. A device may use the SMBus to provide manufacturer information, provide the device model number, report different types of errors, accept control parameters, and return the de- vice status. SMBus was initially proposed by Intel as a link between an intelligent battery, a charger for the battery and a microcontroller that communicates with the rest of the system. -
EPC612D8A-TB EPC612D8A EPC612D8 User Manual
EPC612D8A-TB EPC612D8A EPC612D8 User Manual Version 1.1 Published August 2016 Copyright©2016 ASRock Rack INC. All rights reserved. Version 1.1 Published October 2016 Copyright©2016 ASRock Rack Inc. All rights reserved. Copyright Notice: No part of this documentation may be reproduced, transcribed, transmitted, or translated in any language, in any form or by any means, except duplication of documentation by the purchaser for backup purpose, without written consent of ASRock Rack Inc. Products and corporate names appearing in this documentation may or may not be registered trademarks or copyrights of their respective companies, and are used only for identification or explanation and to the owners’ benefit, without intent to infringe. Disclaimer: Specifications and information contained in this documentation are furnished for informational use only and subject to change without notice, and should not be constructed as a commitment by ASRock Rack. ASRock Rack assumes no responsibility for any errors or omissions that may appear in this documentation. With respect to the contents of this documentation, ASRock Rack does not provide warranty of any kind, either expressed or implied, including but not limited to the implied warranties or conditions of merchantability or fitness for a particular purpose. In no event shall ASRock Rack, its directors, officers, employees, or agents be liable for any indirect, special, incidental, or consequential damages (including damages for loss of profits, loss of business, loss of data, interruption of business and the like), even if ASRock Rack has been advised of the possibility of such damages arising from any defect or error in the documentation or product. -
Design and Realization of a Humanoid Robot for Fast and Autonomous Bipedal Locomotion
TECHNISCHE UNIVERSITÄT MÜNCHEN Lehrstuhl für Angewandte Mechanik Design and Realization of a Humanoid Robot for Fast and Autonomous Bipedal Locomotion Entwurf und Realisierung eines Humanoiden Roboters für Schnelles und Autonomes Laufen Dipl.-Ing. Univ. Sebastian Lohmeier Vollständiger Abdruck der von der Fakultät für Maschinenwesen der Technischen Universität München zur Erlangung des akademischen Grades eines Doktor-Ingenieurs (Dr.-Ing.) genehmigten Dissertation. Vorsitzender: Univ.-Prof. Dr.-Ing. Udo Lindemann Prüfer der Dissertation: 1. Univ.-Prof. Dr.-Ing. habil. Heinz Ulbrich 2. Univ.-Prof. Dr.-Ing. Horst Baier Die Dissertation wurde am 2. Juni 2010 bei der Technischen Universität München eingereicht und durch die Fakultät für Maschinenwesen am 21. Oktober 2010 angenommen. Colophon The original source for this thesis was edited in GNU Emacs and aucTEX, typeset using pdfLATEX in an automated process using GNU make, and output as PDF. The document was compiled with the LATEX 2" class AMdiss (based on the KOMA-Script class scrreprt). AMdiss is part of the AMclasses bundle that was developed by the author for writing term papers, Diploma theses and dissertations at the Institute of Applied Mechanics, Technische Universität München. Photographs and CAD screenshots were processed and enhanced with THE GIMP. Most vector graphics were drawn with CorelDraw X3, exported as Encapsulated PostScript, and edited with psfrag to obtain high-quality labeling. Some smaller and text-heavy graphics (flowcharts, etc.), as well as diagrams were created using PSTricks. The plot raw data were preprocessed with Matlab. In order to use the PostScript- based LATEX packages with pdfLATEX, a toolchain based on pst-pdf and Ghostscript was used. -
Dell EMC Poweredge C4140 Technical Guide
Dell EMC PowerEdge C4140 Technical Guide Regulatory Model: E53S Series Regulatory Type: E53S001 Notes, cautions, and warnings NOTE: A NOTE indicates important information that helps you make better use of your product. CAUTION: A CAUTION indicates either potential damage to hardware or loss of data and tells you how to avoid the problem. WARNING: A WARNING indicates a potential for property damage, personal injury, or death. © 2017 - 2019 Dell Inc. or its subsidiaries. All rights reserved. Dell, EMC, and other trademarks are trademarks of Dell Inc. or its subsidiaries. Other trademarks may be trademarks of their respective owners. 2019 - 09 Rev. A00 Contents 1 System overview ......................................................................................................................... 5 Introduction............................................................................................................................................................................ 5 New technologies.................................................................................................................................................................. 5 2 System features...........................................................................................................................7 Specifications......................................................................................................................................................................... 7 Product comparison............................................................................................................................................................. -
System Management Bus (Smbus) Specification Version 2.0
System Management Bus (SMBus) Specification Version 2.0 System Management Bus (SMBus) Specification Version 2.0 August 3, 2000 SBS Implementers Forum Copyright 1994, 1995, 1998, 2000 Duracell, Inc., Energizer Power Systems, Inc., Fujitsu, Ltd., Intel Corporation, Linear Technology Inc., Maxim Integrated Products, Mitsubishi Electric Semiconductor Company, PowerSmart, Inc., Toshiba Battery Co. Ltd., Unitrode Corporation, USAR Systems, Inc. All rights reserved. SBS Implementers Forum 1 System Management Bus (SMBus) Specification Version 2.0 THIS SPECIFICATION IS PROVIDED “AS IS” WITH NO WARRANTIES WHATSOEVER, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY OF MERCHANTABILITY, NONINFRINGEMENT OR FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE. IN NO EVENT WILL ANY SPECIFICATION CO-OWNER BE LIABLE TO ANY OTHER PARTY FOR ANY LOSS OF PROFITS, LOSS OF USE, INCIDENTAL, CONSEQUENTIAL, INDIRECT OR SPECIAL DAMAGES ARISING OUT OF THIS SPECIFICATION, WHETHER OR NOT SUCH PARTY HAD ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES. FURTHER, NO WARRANTY OR REPRESENTATION IS MADE OR IMPLIED RELATIVE TO FREEDOM FROM INFRINGEMENT OF ANY THIRD PARTY PATENTS WHEN PRACTICING THE SPECIFICATION. * Other product and corporate names may be trademarks of other companies and are used only for explanation and to the owner’s benefit, without intent to infringe. Revision No. Date Notes 1.0 2/15/95 General Release 1.1 12/11/98 Version 1.1 Release 2.0 8/3/00 Version 2.0 Release Questions and comments regarding this For additional information on Smart specification may be forwarded to: Battery System Specifications, visit the [email protected] SBS Implementer’s Forum (SBS-IF) at: www.sbs-forum.org SBS Implementers Forum 2 System Management Bus (SMBus) Specification Version 2.0 Table of Contents 1. -
Hello, and Welcome to This Presentation of the STM32 I²C Interface
Hello, and welcome to this presentation of the STM32 I²C interface. It covers the main features of this communication interface, which is widely used to connect devices such as microcontrollers, sensors, and serial interface memories. 1 The I²C interface is compliant with the NXP I2C-bus specification and user manual, Revision 3; the SMBus System Management Bus Specification, Revision 2; and the PMBus Power System Management Protocol Specification, Revision 1.1. This peripheral provides an easy-to-use interface, with very simple software programming, and full timing flexibility. Additionally, the I²C peripheral is functional in low-power stop modes. 2 The I²C peripheral supports multi-master and slave modes. The I²C IO pins must be configured in open-drain mode. The logic high level is driven by an external pull-up. The I²C alternate functions are available on IO pins supplied by VDD, which can be from 1.71 to 3.6 volts, and on IO pins supplied by VDDIO2, which can be from 1.08 to 3.6 volts. This allows communication with external chips at voltages different from the STM32L4 main power supply. A typical use case is communication with an application processor in sensor hub applications. The IO pins support the 20 mA output drive required for Fast mode Plus. The peripheral controls all I²C bus-specific sequencing, protocol, arbitration and timing values. 7- and 10-bit addressing modes are supported, and multiple 7-bit addresses can be supported in the same 3 application. The peripheral supports slave clock stretching and clock stretching from slave can be disabled by software. -
System Management Bus(Smbus)Specification
System Management Bus (SMBus) Specification Version 3.1 19 Mar 2018 www.powerSIG.org © 2018 System Management Interface Forum, Inc. – All Rights Reserved Filename: SMBus 3_1_20180319.docx Last Saved: 19 March 2018 09:31 System Management Bus (SMBus) Specification Version 3.1 This specification is provided “as is” with no warranties whatsoever, whether express, implied or statutory, including but not limited to any warranty of merchantability, non-infringement or fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification or sample. In no event will any specification co-owner be liable to any other party for any loss of profits, loss of use, incidental, consequential, indirect or special damages arising out of this specification, whether or not such party had advance notice of the possibility of such damages. Further, no warranty or representation is made or implied relative to freedom from infringement of any third party patents when practicing the specification. Other product and corporate names may be trademarks of other companies and are used only for explanation and to the owner’s benefit, without intent to infringe. Revision No. Date Notes Editor 1.0 15 Feb 1995 General Release Robert Dunstan 1.1 11 Dec 1998 Version 1.1 Release Robert Dunstan 2.0 3 Aug 2000 Version 2.0 Release Robert Dunstan 3.0 20 Dec 2014 Version 3.0 Release Robert V. White Embedded Power Labs 3.1 19 Mar 2018 Version 3.1 Release Robert V. White Embedded Power Labs Questions and comments regarding this For additional information on Smart Battery System specification may be forwarded to: Specifications, visit the SBS Implementer’s Forum [email protected] (SBS-IF) at: www.sbs-forum.org © 2018 System Management Interface Forum, Inc. -
PCI Code and ID Assignment Specification Revision 1.11 24 Jan 2019
PCI Code and ID Assignment Specification Revision 1.11 24 Jan 2019 PCI CODE AND ID ASSIGNMENT SPECIFICATION, REV. 1.11 Revision Revision History Date 1.0 Initial release. 9/9/2010 1.1 Incorporated approved ECNs. 3/15/2012 1.2 Incorporated ECN for Accelerator Class code, added PI for xHCI. 3/15/2012 Updated section 1.2, Base Class 01h, Sub-class 00h by adding 1.3 9/4/2012 Programming Interfaces 11h, 12h, 13h, and 21h. Added Notes 3, 4, and 5. Updated Section 1.2, Base Class 01h, to add Sub-class 09h. Updated Section 1.9, Base Class 08h to add Root Complex Event Collector, Sub-class 07h 1.4 Updated Section 1 and added Section 1.20, to define Base Class 13h. 8/29/2013 Updated Chapter 3 to define Extended Capability IDs 001Dh through 0022h. Reformatted Notes in Sections 1.2 and 1.7 through 1.10. Updated references to NVM Express in Section 1.9, Base Class 08h Updated Section 1.2, to clarify SOP entries in Base Class 01h, add proper reference to NVMHCI, update UFS entries, and address other minor 1.5 3/6/2014 editorial issues. Updated Section 3, Extended Capability ID descriptions 19h, 1Ch, 1Fh. Updated Section 1.3, Class 02h, to add Sub-Class 08h. 1.6 Updated Section 1.14, Base Class 0Dh, to add Sub-Classes 40h and 41h. 12/9/2014 Updated Section 2 to add Capability ID 14h. Added Designated Vendor-Specific Extended Capability ID. 1.7 Updated/Modified Section 1.5, Base Class 04h, for Multimedia devices to 8/13/2015 accurately reflect use of this class for High Definition Audio (HD-A). -
Design and Stiffness Analysis of 12 Dof Poppy-Inspired Humanoid
Design and Stiffness Analysis of 12 DoF Poppy-inspired Humanoid Dmitry Popov, Alexandr Klimchik and Ilya Afanasyev Institute of Robotics, Innopolis University, Universitetskaya Str. 1, Innopolis, Russia Keywords: Stiffness Modeling, Human Mechatronics, Motion Control Systems, Robot Kinematics. Abstract: This paper presents a low-cost anthropomorphic robot, considering its design, simulation, manufacturing and experiments. The robot design was inspired by open source Poppy Humanoid project and enhanced up to 12 DoF lower limb structure, providing additional capability to develop more natural, fast and stable biped robot walking. The current robot design has a non-spherical hip joint, that does not allow to use an analytical solution for the inverse kinematics, therefore another hybrid solution was presented. Problem of robot joint’s compliance was addressed using virtual joint method for stiffness modeling with further compensation of elas- tic deflections caused by the robot links weight. Finally, we modeled robot’s lower-part in V-REP simulator, manufactured its prototype using 3D printing technology, and implemented ZMP preview control, providing experiments with demonstration of stable biped locomotion. 1 INTRODUCTION 5 DoF leg (Lapeyre et al., 2013b). Stiffness modeling in robotics is considered for in- The progress in creation of highly specialized robotic dustrial manipulators, where problem of end-effector systems contributes to automation of different every- precise positioning under external and internal load day life aspects that can partially or fully replace hu- are critical (Pashkevich et al., 2011). In humanoid mans in the future in some routine activities. The robots accurate positioning is not always necessary, development of androids is one of the most relevant but with high compliance in links or joints, deflections solution for successful robot operations in human en- caused by payload or link weights can affect robot sta- vironment with enhanced functionality. -
Increasing User Confidence in Privacy-Sensitive Robots by Raniah
Increasing User Confdence in Privacy-Sensitive Robots by Raniah Abdullah Bamagain Bachelor of Science Information Technology Computing and Information Technology 2012 A thesis submitted to the College of Computer Engineering and Sciences at Florida Institute of Technology in partial fulfllment of the requirements for the degree of Master of Science in Information Assurance and Cybersecurity Melbourne, Florida May, 2019 ⃝c Copyright 2019 Raniah Abdullah Bamagain All Rights Reserved The author grants permission to make single copies. We the undersigned committee hereby approve the attached thesis Increasing User Confdence in Privacy-Sensitive Robots by Raniah Abdullah Bamagain Marius Silaghi, Ph.D. Associate Professor Department of Computer Engineering and Sciences Committee Chair Hector Gutierrez, Ph.D. Professor Department of Mechanical and Civil Engineering Outside Committee Member Lucas Stephane, Ph.D. Assistant Professor Department of Computer Engineering and Sciences Committee Member Philip Bernhard, Ph.D Associate Professor and Head Department of Computer Engineering and Sciences ABSTRACT Title: Increasing User Confdence in Privacy-Sensitive Robots Author: Raniah Abdullah Bamagain Major Advisor: Marius Silaghi, Ph.D. As the deployment and availability of robots grow rapidly, and spreads everywhere to reach places where they can communicate with humans, and they can constantly sense, watch, hear, process, and record all the environment around them, numerous new benefts and services can be provided, but at the same time, various types of privacy issues appear. Indeed, the use of robots that process data remotely causes privacy concerns. There are some main factors that could increase the capabil- ity of violating the users' privacy, such as the robots' appearance, perception, or navigation capability, as well as the lack of authentication, the lack of warning sys- tem, and the characteristics of the application.