DOCSLIB.ORG

Quick Reference Guide for A1SA7-2750F

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Quick Reference Guide for A1SA7-2750F ONTACT NFORMATION FOR YOUR SYSTEM TO WORK PROPERLY, PLEASE DOWNLOAD APPROPRIATE R C I SUPERMICR • Website: www.supermicro.com DRIVERS/IMAGES/USER'S MANUAL FROM THE LINKS BELOW: A1SA7-2750/2550F • General Information: [email protected] • Manuals: http://www.supermicro.com/support/manuals • Technical Support: [email protected] • Drivers & Utilities: ftp://ftp.supermicro.com/CDR_Images/CDR-A1-UP/ MNL-1616-QRG QUicK REFERENCE GUIDE REV. 1.00 • Phone: +1 (408) 503-8000, Fax: +1 (408) 503-8008 • Safety: http://www.supermicro.com/about/policies/safety_information.cfm Motherboard Layout and Features Jumpers, Connectors and LED Indicators Memory Support Jumpers The A1SA7-2750/2550F motherboard supports up to 64GB of DDR3 ECC or Non- Jumper Item # Description Default ECC Unbuffered (UDIMM) 1600/1333 MHz in x8 data width only, in 4 memory slots. 19 1 JBT1 30 CMOS Clear Open: Normal Operation, Short: Clear CMOS 110 18 17 6 Populating these DIMM modules with a pair of memory modules of the same type 1 14 13 5 12 11 JI2C1/JI2C2 40, 41 SMB to PCI-Exp. Slots Off (Disabled) 461 and same size will result in better memory performance. 451 2 LED8 LED7 JPG1 11 VGA Enable Pins 1-2 (Enabled) JUIDB1 VGA UID-LE DIMM Memory Installation J28 JPG1 JPL1 36 Ethernet LAN Ports Enable Pins 1-2 (Enabled) UID-SW SW1 USB1 J27 USB2 111 D USB1/0 JWD1 43 Watch Dog Enable Pins 1-2 (Reset) Towards the edge of motherboard BMC IPMI_LAN LAN2 LAN1 L-SAS1 L-SAS1 AST2400 Connectors 1 DIMMA1 (Blue Slot) JPL1 I-SATA0 35 Connector Item # Description 4 5 411 JI2C JI2C 401 361 DIMMA2 L-SAS1 L-SAS1 Battery (JBAT1) 18 Onboard Battery 2 1 139 138 LED2 LED3 LED9 134 DIMMB1 (Blue Slot) 2 3 137 COM1 32 COM1 Header CPU JSD1 USB3 SLOT1 PCI-E 2.0 X4(IN x8 FAN1-FAN7 23, 22, 21, 20 CPU/System Cooling Fans DIMMB2 1 1 33 L-SAS1 L-SAS1 42 19, 14, 15 BAR CODE 1 0 IPMI_LAN 5 IPMI Dedicated LAN Memory Population Guidelines MNL-1616-QRG 1.00 L-SAS9 L-SAS8 J3 27 Motherboard 5V Standby Power Input 321 When installing memory modules, the DIMM slots should be populated in the fol- 1 12 ) JF1 24 Front Panel Control Header LSI 2116 COM1 lowing order: DIMMA1, DIMMB1, then DIMMA2, DIMMB2. JF1: 2 PWR JIPMB1 13 4-pin External SMbus I C Header (for an IPMI Card) ON • Always use DDR3 DIMM modules of the same size, type and speed. L-SAS7 L-SAS6 RST X OH/FF NIC2 JL1 16 Chassis Intrusion Header NIC1 HDD LED 131 • The motherboard will support one DIMM module or three DIMM modules in- PWR LED J7 NMI JOH1 17 Overheat/Fan Fail LED Header stalled. However for best memory performance, install DIMM modules in pairs. 1 130 JTPM1 L-SAS5 L-SAS4 MAC CODE JBT1 JP1 25 HDD Backplane Power Control header A1SA7-2550F BAR CODE • Be sure to use memory modules of the same type, same speed, and same REV:1.01 BIOS LICENS JPWR1 2 2 DESIGNED IN USA JPI C1 28 Power Supply System Management Bus (SMBus) I C frequency on the same motherboard. Mixing of memory modules of different 129 JWD1 JRT3 types and speeds is not allowed. L-SAS3 L-SAS2 431 JBAT1 Header 181 E JF1 1 JIPMB1 44 JPWR1 29 +12V 8-pin Motherboard Power connector 1 JP1 JR JPI2C1 JOH1 171 Recommended Population (Balanced) T4 SP1 128 L-SAS0 L-SAS1 1 JSD1 34 SATA DOM (Device_On_Module) Power Connector DIMMA1 Slot DIMMB1 Slot DIMMA2 Slot DIMMB2 Slot Total System Memory JL1 16 FA FAN7 FA FA FA FA FA N5 N6 N4 N3 N2 N1 J3 JTPM1 31 Trusted Platform Module (TPM)/Port 80 Connector 4GB 4GB 8GB DIMMA1 DIMMA2 DIMMB1 DIMMB2 LED4 JUIDB1 8 Unit Identifier (UID) Button 4GB 4GB 4GB 4GB 16GB 1 1 1 191 120 121 122 231 1 125 127 13 14 15 24 LAN1/LAN2 3, 4 Gigabit Ethernet (RJ45) Ports 8GB 8GB 16GB 261 L-SAS0 - L-SAS15 12 LSI 2116 SAS Ports 0-15 8GB 8GB 8GB 8GB 32GB I-SATA0 35 Intel Serial ATA Port 0 PCI-E Slot 42 PCI-E Slot 2.0 x4 (x8) 1 Module Key Module Notches = mounting hole 2 Note: Item numbers are in counterclockwise order SP1 44 Internal Speaker/Buzzer SW1 7 Power Button Front Panel Control (JF1) Back Panel I/O Connectors USB1/USB2 1, 2 Backpanel USB 2.0 Ports 1/2 USB 3 33 USB 2.0 Front Access Support/Type A Connector) VGA 6 Backpanel VGA Port Socket Key 20 19 J27 45 NC-SI header for AOC-STGN-i1SF 10GbE card Ground NMI A B J28 46 Power to AOC-STGN-i1SF 10GbE card X X C D E F LED Indicators FP PWR LED 3.3 V 3 4 G H LED Item # Description Color/State Status HDD LED 3.3V Stby LED2 37 BMC Heartbeat LED Green: Blinking BMC: Normal NIC2 Link LED 3.3V Stby LED3 39 LSISAS2116 Heartbeat LED Green: Blinking SAS Controller: Normal 3.3V Stby NIC1 Link LED LED4 26 Power LED Green: On System Power On 5 OH/Fan Fail UID LED Backplane I/O Panel LED7 9 UID Switch LED Blue: On Unit Identified 3.3V A. USB Port 1 E. IPMI LAN PWR Fail LED8 10 Overheat/PWR Fail/Fan Fail Red: Solid on/Blinking Solid On: Overheat, B. USB Port 2 F. VGA Ground Reset Reset Button LED Blinking: PWR Fail or C. LAN Port 1 G. Power Button Fan Fail Ground PWR Power Button 2 1 D. LAN Port 2 H. UID Switch LED9 38 LSISA2116 Error LED Red: On LSISAS2116 Error Status © 2014 Supermicro Computer Inc. All rights reserved. Reproduction of this document whether in part or in whole is strictly prohibited without Supermicro's written All rights reserved. Reproduction of this document whether in part or whole is strictly prohibited without Supermicro's written © 2014 Supermicro Computer Inc. it is not guaranteed. All information provided is deemed accurate at the time of printing; however, are property of their respective entities. All Trademarks consent. Note: Graphics shown in this quick reference guide are for illustration only. Your components may or may not look exactly the same as drawings shown in this guide. Note: Refer to Chapter 1 of the User Manual for detailed information on jumpers, connectors, Note: Refer to Chapter 2 of the User Manual for detailed information on memory support and CPU/ and LED indicators. motherboard installation instructions. .
Load more

Recommended publications
  • Allgemeines Abkürzungsverzeichnis
    Allgemeines Abkürzungsverzeichnis L.
    [Show full text]
  • Dell EMC Poweredge T340 Technical Guide
    Dell EMC PowerEdge T340 Technical Guide Regulatory Model: E60S Regulatory Type: E60S001 Dec. 2020 Rev. A07 Notes, cautions, and warnings NOTE: A NOTE indicates important information that helps you make better use of your product. CAUTION: A CAUTION indicates either potential damage to hardware or loss of data and tells you how to avoid the problem. WARNING: A WARNING indicates a potential for property damage, personal injury, or death. © 2018 - 2020 Dell Inc. or its subsidiaries. All rights reserved. Dell, EMC, and other trademarks are trademarks of Dell Inc. or its subsidiaries. Other trademarks may be trademarks of their respective owners. 1 Product Overview Topics: • Introduction • New technologies Introduction The Dell EMC PowerEdge T340 is the reliable, easy to manage, and scalable 1-socket tower server for growing businesses and remote offices/ branch offices. New technologies The PowerEdge T340 equipped with Intel® Xeon® E-2100 and E-2200 product family processors support to help run applications faster and support for full-feature remote management (iDRAC9). The T340 is versatile enough to address many customer segments and workloads. Target workloads include ● Small and medium businesses and organizations: Collaboration/sharing productivity applications, databases, web serving, backup/recovery, and mail and messaging. ● ROBO: Applications and workloads specific to the particular industry, e.g. Retail, Healthcare, Finance, Education, etc. The following table shows the list of new technologies offered by the PowerEdge T340: New Technologies Detailed Descriptions Intel® C246 series chipset Please refer to the chipset section for details. Intel® Xeon® processor E- 2100 and E-2200 Product The Intel® processor that works with Intel® C246 series Family chipset.
    [Show full text]
  • 3. System Management Bus
    Input/Output Systems and Peripheral Devices 1 3. SYSTEM MANAGEMENT BUS This laboratory work presents the System Management Bus (SMBus). After an over- view of SMBus, bit and data transfers are described, the bus arbitration procedure is present- ed, the differences between SMBus and the I2C bus are highlighted, and several command protocols are detailed. Next, the Intel SMBus controller is presented, including its registers and commands, as well as its use with I2C devices. The applications aim to detect the devices connected to the computer’s SMBus, read the contents of SPD memories present in the sys- tem, and decode the contents of these memories. 3.1. Overview of SMBus System Management Bus (SMBus) is a simple serial bus with only two signal lines. This bus can be used for communication between various system devices and between these devices and the rest of a system. The operating principles of SMBus are similar to those of the I2C bus. There are, however, several differences between the two buses, differences which will be presented later. SMBus represents a control bus for system management and power management op- erations. A system may use the SMBus to transfer messages to and from various devices in- stead of using individual control lines, which allows to reduce pin count and interconnection wires. A device may use the SMBus to provide manufacturer information, provide the device model number, report different types of errors, accept control parameters, and return the de- vice status. SMBus was initially proposed by Intel as a link between an intelligent battery, a charger for the battery and a microcontroller that communicates with the rest of the system.
    [Show full text]
  • EPC612D8A-TB EPC612D8A EPC612D8 User Manual
    EPC612D8A-TB EPC612D8A EPC612D8 User Manual Version 1.1 Published August 2016 Copyright©2016 ASRock Rack INC. All rights reserved. Version 1.1 Published October 2016 Copyright©2016 ASRock Rack Inc. All rights reserved. Copyright Notice: No part of this documentation may be reproduced, transcribed, transmitted, or translated in any language, in any form or by any means, except duplication of documentation by the purchaser for backup purpose, without written consent of ASRock Rack Inc. Products and corporate names appearing in this documentation may or may not be registered trademarks or copyrights of their respective companies, and are used only for identification or explanation and to the owners’ benefit, without intent to infringe. Disclaimer: Specifications and information contained in this documentation are furnished for informational use only and subject to change without notice, and should not be constructed as a commitment by ASRock Rack. ASRock Rack assumes no responsibility for any errors or omissions that may appear in this documentation. With respect to the contents of this documentation, ASRock Rack does not provide warranty of any kind, either expressed or implied, including but not limited to the implied warranties or conditions of merchantability or fitness for a particular purpose. In no event shall ASRock Rack, its directors, officers, employees, or agents be liable for any indirect, special, incidental, or consequential damages (including damages for loss of profits, loss of business, loss of data, interruption of business and the like), even if ASRock Rack has been advised of the possibility of such damages arising from any defect or error in the documentation or product.
    [Show full text]
  • SBIR Program Document
    Topic Index and Description A20-101 Continuous Flow Recrystallization of Energetic Nitramines A20-102 Deep Neural Network Learning Based Tools for Embedded Systems Under Side Channel Attacks A20-103 Beyond Li-Ion Batteries in Electric Vehicles (EV) A20-104 Wireless Power transfer A20-105 Direct Wall Shear Stress Measurement for Rotor Blades A20-106 Electronically-Tunable, Low Loss Microwave Thin-film Ferroelectric Phase-Shifter A20-107 Automated Imagery Annotation and Segmentation for Military Tactical Objects A20-108 Multi-Solution Precision Location Determination System to be Operational in a Global Positioning System (GPS) Denied Environment for Static, Dynamic and Autonomous Systems under Test A20-109 Environmentally Adaptive Free-Space Optical Communication A20-110 Localized High Bandwidth Wireless Secure Mesh Network A20-111 Non-Destructive Evaluation of Bonded Interface of Cold Spray Additive Repair A20-112 Compact, High Performance Engines for Air Launched Effects UAS A20-113 Optical Based Health Usage and Monitoring System (HUMS) A20-114 3-D Microfabrication for In-Plane Optical MEMS Inertial Sensors A20-115 Using Artificial Intelligence to Optimize Missile Sustainment Trade-offs A20-116 Distributed Beamforming for Non-Developmental Waveforms A20-117 Lens Antennas for Resilient Satellite Communications (SATCOM) on Ground Tactical Vehicles A20-118 Novel, Low SWaP-C Unattended Ground Sensors for Relevant SA in A2AD Environments A20-119 Efficient Near Field Charge Transfer Mediated Infrared Detectors A20-120 Very Small Pixel Uncooled
    [Show full text]
  • Dell EMC Poweredge C4140 Technical Guide
    Dell EMC PowerEdge C4140 Technical Guide Regulatory Model: E53S Series Regulatory Type: E53S001 Notes, cautions, and warnings NOTE: A NOTE indicates important information that helps you make better use of your product. CAUTION: A CAUTION indicates either potential damage to hardware or loss of data and tells you how to avoid the problem. WARNING: A WARNING indicates a potential for property damage, personal injury, or death. © 2017 - 2019 Dell Inc. or its subsidiaries. All rights reserved. Dell, EMC, and other trademarks are trademarks of Dell Inc. or its subsidiaries. Other trademarks may be trademarks of their respective owners. 2019 - 09 Rev. A00 Contents 1 System overview ......................................................................................................................... 5 Introduction............................................................................................................................................................................ 5 New technologies.................................................................................................................................................................. 5 2 System features...........................................................................................................................7 Specifications......................................................................................................................................................................... 7 Product comparison.............................................................................................................................................................
    [Show full text]
  • System Management Bus (Smbus) Specification Version 2.0
    System Management Bus (SMBus) Specification Version 2.0 System Management Bus (SMBus) Specification Version 2.0 August 3, 2000 SBS Implementers Forum Copyright 1994, 1995, 1998, 2000 Duracell, Inc., Energizer Power Systems, Inc., Fujitsu, Ltd., Intel Corporation, Linear Technology Inc., Maxim Integrated Products, Mitsubishi Electric Semiconductor Company, PowerSmart, Inc., Toshiba Battery Co. Ltd., Unitrode Corporation, USAR Systems, Inc. All rights reserved. SBS Implementers Forum 1 System Management Bus (SMBus) Specification Version 2.0 THIS SPECIFICATION IS PROVIDED “AS IS” WITH NO WARRANTIES WHATSOEVER, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY OF MERCHANTABILITY, NONINFRINGEMENT OR FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE. IN NO EVENT WILL ANY SPECIFICATION CO-OWNER BE LIABLE TO ANY OTHER PARTY FOR ANY LOSS OF PROFITS, LOSS OF USE, INCIDENTAL, CONSEQUENTIAL, INDIRECT OR SPECIAL DAMAGES ARISING OUT OF THIS SPECIFICATION, WHETHER OR NOT SUCH PARTY HAD ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES. FURTHER, NO WARRANTY OR REPRESENTATION IS MADE OR IMPLIED RELATIVE TO FREEDOM FROM INFRINGEMENT OF ANY THIRD PARTY PATENTS WHEN PRACTICING THE SPECIFICATION. * Other product and corporate names may be trademarks of other companies and are used only for explanation and to the owner’s benefit, without intent to infringe. Revision No. Date Notes 1.0 2/15/95 General Release 1.1 12/11/98 Version 1.1 Release 2.0 8/3/00 Version 2.0 Release Questions and comments regarding this For additional information on Smart specification may be forwarded to: Battery System Specifications, visit the [email protected] SBS Implementer’s Forum (SBS-IF) at: www.sbs-forum.org SBS Implementers Forum 2 System Management Bus (SMBus) Specification Version 2.0 Table of Contents 1.
    [Show full text]
  • Hello, and Welcome to This Presentation of the STM32 I²C Interface
    Hello, and welcome to this presentation of the STM32 I²C interface. It covers the main features of this communication interface, which is widely used to connect devices such as microcontrollers, sensors, and serial interface memories. 1 The I²C interface is compliant with the NXP I2C-bus specification and user manual, Revision 3; the SMBus System Management Bus Specification, Revision 2; and the PMBus Power System Management Protocol Specification, Revision 1.1. This peripheral provides an easy-to-use interface, with very simple software programming, and full timing flexibility. Additionally, the I²C peripheral is functional in low-power stop modes. 2 The I²C peripheral supports multi-master and slave modes. The I²C IO pins must be configured in open-drain mode. The logic high level is driven by an external pull-up. The I²C alternate functions are available on IO pins supplied by VDD, which can be from 1.71 to 3.6 volts, and on IO pins supplied by VDDIO2, which can be from 1.08 to 3.6 volts. This allows communication with external chips at voltages different from the STM32L4 main power supply. A typical use case is communication with an application processor in sensor hub applications. The IO pins support the 20 mA output drive required for Fast mode Plus. The peripheral controls all I²C bus-specific sequencing, protocol, arbitration and timing values. 7- and 10-bit addressing modes are supported, and multiple 7-bit addresses can be supported in the same 3 application. The peripheral supports slave clock stretching and clock stretching from slave can be disabled by software.
    [Show full text]
  • System Management Bus(Smbus)Specification
    System Management Bus (SMBus) Specification Version 3.1 19 Mar 2018 www.powerSIG.org © 2018 System Management Interface Forum, Inc. – All Rights Reserved Filename: SMBus 3_1_20180319.docx Last Saved: 19 March 2018 09:31 System Management Bus (SMBus) Specification Version 3.1 This specification is provided “as is” with no warranties whatsoever, whether express, implied or statutory, including but not limited to any warranty of merchantability, non-infringement or fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification or sample. In no event will any specification co-owner be liable to any other party for any loss of profits, loss of use, incidental, consequential, indirect or special damages arising out of this specification, whether or not such party had advance notice of the possibility of such damages. Further, no warranty or representation is made or implied relative to freedom from infringement of any third party patents when practicing the specification. Other product and corporate names may be trademarks of other companies and are used only for explanation and to the owner’s benefit, without intent to infringe. Revision No. Date Notes Editor 1.0 15 Feb 1995 General Release Robert Dunstan 1.1 11 Dec 1998 Version 1.1 Release Robert Dunstan 2.0 3 Aug 2000 Version 2.0 Release Robert Dunstan 3.0 20 Dec 2014 Version 3.0 Release Robert V. White Embedded Power Labs 3.1 19 Mar 2018 Version 3.1 Release Robert V. White Embedded Power Labs Questions and comments regarding this For additional information on Smart Battery System specification may be forwarded to: Specifications, visit the SBS Implementer’s Forum [email protected] (SBS-IF) at: www.sbs-forum.org © 2018 System Management Interface Forum, Inc.
    [Show full text]
  • PCI Code and ID Assignment Specification Revision 1.11 24 Jan 2019
    PCI Code and ID Assignment Specification Revision 1.11 24 Jan 2019 PCI CODE AND ID ASSIGNMENT SPECIFICATION, REV. 1.11 Revision Revision History Date 1.0 Initial release. 9/9/2010 1.1 Incorporated approved ECNs. 3/15/2012 1.2 Incorporated ECN for Accelerator Class code, added PI for xHCI. 3/15/2012 Updated section 1.2, Base Class 01h, Sub-class 00h by adding 1.3 9/4/2012 Programming Interfaces 11h, 12h, 13h, and 21h. Added Notes 3, 4, and 5. Updated Section 1.2, Base Class 01h, to add Sub-class 09h. Updated Section 1.9, Base Class 08h to add Root Complex Event Collector, Sub-class 07h 1.4 Updated Section 1 and added Section 1.20, to define Base Class 13h. 8/29/2013 Updated Chapter 3 to define Extended Capability IDs 001Dh through 0022h. Reformatted Notes in Sections 1.2 and 1.7 through 1.10. Updated references to NVM Express in Section 1.9, Base Class 08h Updated Section 1.2, to clarify SOP entries in Base Class 01h, add proper reference to NVMHCI, update UFS entries, and address other minor 1.5 3/6/2014 editorial issues. Updated Section 3, Extended Capability ID descriptions 19h, 1Ch, 1Fh. Updated Section 1.3, Class 02h, to add Sub-Class 08h. 1.6 Updated Section 1.14, Base Class 0Dh, to add Sub-Classes 40h and 41h. 12/9/2014 Updated Section 2 to add Capability ID 14h. Added Designated Vendor-Specific Extended Capability ID. 1.7 Updated/Modified Section 1.5, Base Class 04h, for Multimedia devices to 8/13/2015 accurately reflect use of this class for High Definition Audio (HD-A).
    [Show full text]
  • Intel® Omni-Path Software — Release Notes for V10.8.0.2
    Intel® Omni-Path Software Release Notes for V10.8.0.2 Rev. 1.0 January 2019 Doc. No.: K48500, Rev.: 1.0 You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein. No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest Intel product specifications and roadmaps. The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software or service activation. Performance varies depending on system configuration. No computer system can be absolutely secure. Check with your system manufacturer or retailer or learn more at intel.com. Intel, the Intel logo, Intel Xeon Phi, and Xeon are trademarks of Intel Corporation in the U.S. and/or other countries. *Other names and brands may be claimed as the property of others. Copyright © 2019, Intel Corporation. All rights reserved. Intel® Omni-Path Software Release Notes for V10.8.0.2 January 2019 2 Doc. No.: K48500, Rev.: 1.0 Contents—Intel® Omni-Path Fabric Contents 1.0 Overview of the Release............................................................................................... 5 1.1 Important Information...........................................................................................
    [Show full text]
  • Intel® Solid-State Drive Data Center P3700 Series Product Specification
    Intel® Solid-State Drive DC P3700 Series Product Specification Capacities: 400GB, 800GB, 1.6TB, 2TB Power Components – 2.5-inch: 3.3V and 12V Supply Rail – Intel® 20nm MLC NAND Flash Memory – AIC: 3.3V and 12V Supply Rail Form Factors – Enhanced power-loss data protection – 2.5-inch Form Factor – Active/Idle (TYP): Up to 25W/4W (TYP) 15mm Z-height Endurance Rating 8639-compatible connector – Up to 62.05 PBW (Petabytes Written)5 – AIC Form Factor – Up to 17 Drive Writes/day (JESD219 workload) Half-height, Half-length Temperature Specification Single slot x4 connector – Operating: PCIe* Gen3 X4 AIC: 0 to 55° C ambient with Performance1,2 specified airflow – Seq R/W: Up to 2800/2000MB/s3 2.5-inch: 0 to 35° C ambient, – IOPS Rnd 4KB4 70/30 R/W: Up to 265K 0 to 70° C case with specified airflow – IOPS Rnd 4KB4 R/W: Up to 460/175K – Non-Operating6: -55 to 95° C – Seq Latency (typ) R/W: 20/20µs – Temperature monitoring (In-band and by Operating System Support: way of SMBUS) – Windows* Server 2012 R2, 2012, – Thermal throttling when approaching 2008 R2 x64 maximum operating temperature – Windows* 7, Windows* 8, Airflow Windows* 8.1, 10 (32/64bit) – AIC (55° C airflow towards IO bracket7) – RHEL* 6.5, 6.6, 6.7,7.0, 7.1 400GB: 200 LFM – SLES11 SP3*, SP4, SLES12 800GB, 1.6TB, 2.0TB: 300 LFM – Citrix* XenServer* 6.5 – 2.5-inch (Airflow towards the connector) – VMWare* ESXi 5.5 400GB: 250/300 LFM (25/35° C) – CentOS* 6.5 800GB: 350/500 LFM (25/35° C) – UEFI 2.3.1* 1.6TB, 2TB: 450/600 LFM (25/35° C) Reliability Weight – Uncorrectable Bit
    [Show full text]