從微算機原理到系統

宋開泰教授 國立交通大學電機與控制系 工程五館 EE709 Phone：5731865（校內分機：31865） E-mail：[email protected] URL：http://isci.cn.nctu.edu.tw

Microcomputer Systems & Lab Microcomputer bus 1 Digital Signal Waveform

1 0 Single-signal waveform

1 0

Multiple-signal waveform

Microcomputer Systems & Lab Microcomputer bus 2 Read Timing for External Code Memory

Microcomputer Systems & Lab Microcomputer bus 3 Microcomputer BUS

• A bus is a set of conducting wires interconnecting the CPU, memory, and I/O devices. • There are three types of bus: Address bus, Data bus and Control bus. There are also utilities in a bus system, such as Vcc and ground lines. • To drive a bus, a bus driver is needed. To receive data from the bus, a bus receiver is needed. The bus driver and bus receiver can be combined to form a bus transceiver.

Microcomputer Systems & Lab Microcomputer bus 4 Connecting to a bus

• A bus should be driven by no more than one device at any time. Otherwise, bus contention will occur. When bus contention occurs, the devices that are involved in bus contention could be damaged. • A device is disconnected from the bus when the driver-enable and receiver-enable signals are deasserted. When the enable signal is deasserted, the output of the driver or the receiver is in a high-impedance state in which no current flow into or out the device involved.

Microcomputer Systems & Lab Microcomputer bus 5 Interconnecting the CPU, Memory, and I/O Devices Memory unit 8 bits 1,048,575 Clock generator 64 672,356

Address Instruction pointer (IP) System address bus Selector/ z System 6 memory 672 356 decoder 5 4 Instruction register 3 2 64 1 Location 0 INC AX Instruction decoder

Internal databus System control bus Arithmetic logic unit Memory read Memory write

Accumulator I/O write I/O read I/O write I/O read I/O write 26+1=27 System data bus

Video monitor I/O devices: Printer keyboard Floppy disk drive z General-purpose registers I/O port Selector/decoder Central processing unit (CPU) Microcomputer Systems & Lab Microcomputer bus 6 System Bus • Internal data bus is used to classify a microprocessor. • External data bus is not the same as the Internal data bus. Normally it is part if a standardized system bus. • System bus is used for system expansion, for example, ISA Bus, EISA Bus, VMEbus, PCI Bus, Nubus, IEEE488 Bus. • A microcomputer system can be constructed by interconnecting several devices through system bus.

Microcomputer Systems & Lab Microcomputer bus 7 PCI Bus and a Personal Computer Architecture

Small Computer Systems Interface (SCSI) 10Mbytes/s

Microcomputer Systems & Lab Microcomputer bus 8 Bus Bandwidth and Signal Transfer Rates

ISA Bus: 8.33 Mbytes per second EISA Bus: 33 Mbytes per second PCI Bus: 132 Mbytes per second (32-bit), 264Mbytes per second (64-bit) VMEbus: 40 Mbytes per second

Microcomputer Systems & Lab Microcomputer bus 9 VMEbus Chassis

Microcomputer Systems & Lab Microcomputer bus 10 VMEbus Backplane

Microcomputer Systems & Lab Microcomputer bus 11 Totem pole output of a NAND gate

TTL gates come in three types of output configurations: 1. Totem-pole output 2. Open-collector output 3. Three-state (or Tristate output)

From: Design with Microprocessors for Mechanical Engineers, A. K. Stiffler Microcomputer Systems & Lab Microcomputer bus 12 Open-collector output

1. External pull-up resistor is required to have output high. 2. Outputs can be bussed together. 3. If any one is asserted low, then the output is low. From: Design with Microprocessors for Mechanical Engineers, A. K. Stiffler

Microcomputer Systems & Lab Microcomputer bus 13 Connecting two Open collector outputs

From: Design with Microprocessors for Mechanical Engineers, A. K. Stiffler

Microcomputer Systems & Lab Microcomputer bus 14 Three-State TTL Output

From: An Introduction to Microcomputer Systems, J. Fulcher

Microcomputer Systems & Lab Microcomputer bus 15 Types of Three-state outputs

From: Design with Microprocessors for Mechanical Engineers, A. K. Stiffler

Microcomputer Systems & Lab Microcomputer bus 16 74LS75 Transparent latch

From: Design with Microprocessors for Mechanical Engineers, A. K. Stiffler

1. Outputs are controlled by the enable C, as long as the enable is LOW, output Q holds its last value. 2. When the enable goes HIGH, the output follows the data presented at input D.

Microcomputer Systems & Lab Microcomputer bus 17 74LS374 Edge- 74LS373 triggered flip- Transparent flop latch

Data should be latched on the trailing edge of the enable pulse.

From: Design with Microprocessors for Mechanical Engineers, A. K. Stiffler Microcomputer Systems & Lab Microcomputer bus 18 Output port using 74LS373

From: Design with Microprocessors for Mechanical Engineers, A. K. Stiffler

Microcomputer Systems & Lab Microcomputer bus 19 Input port using 74LS244

From: Design with Microprocessors for Mechanical Engineers, A. K. Stiffler

Microcomputer Systems & Lab Microcomputer bus 20 Bus Transactions

• A bus transaction includes two parts: sending the address and receiving or sending the data. • Read transaction: a read transaction transfers a byte or bytes of data from memory or I/O devices to CPU. • Write transaction: a write transaction writes a byte or bytes of data to memory or I/O devices.

Microcomputer Systems & Lab Microcomputer bus 21 Bus control

• In a read transaction, the address is first sent out to the bus and down to the memory, together with an appropriate control signals indicating a read. • A device that initiate a read or write transaction is called a bus master. • A device such as a memory chip that can not initiate a bus transaction is called a bus slave. • In a bus transaction, some kind of signal is needed to synchronize the data transfer.

Microcomputer Systems & Lab Microcomputer bus 22 Typical Slave Internal Structure

Clock Data Address

Address Bus Master Decoder

Buffer

Bus Slave

Microcomputer Systems & Lab Microcomputer bus 23 Parallel I/O Interface

Direct memory access(DMA) Memory Output Actuator Device

CPU I/O Transducer Input Device Microprocessor / Parallel Microcontroller Interface

Parallel I/O is suitable for high-speed applications.

Microcomputer Systems & Lab Microcomputer bus 24 Success and enjoy the microcomputer systems!

Microcomputer Systems & Lab Microcomputer bus 25