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Topic 10 Bus Architecture & Interconnects Introductions & Sources Introductions & Sources X We will consider a number of issues related to bus architectures in digital systems. Topic 10 X Useful references: • “Bus Architecture of a System on a Chip with User-Configurable System Bus Architecture & Logic”, Steven Winegarden, IEEE JOURNAL OF SOLID-STATE CIRCUITS, Interconnects VOL. 35, NO. 3, MARCH 2000, p425-433. • “AMBA: ENABLING REUSABLE ON-CHIP DESIGNS”, David Flynn, IEEE Micro, July/August 1997. Peter Cheung • AMBA™ Specification (Rev 2.0), ARM Ltd., 1999 Department of Electrical & Electronic Engineering • The CoreConnect Bus Architecture, IBM, Imperial College London http://www.chips.ibm.com/products/coreconnect • VSI Alliance Architecture Document, version 1.0, 1997. • Draft Chapter, “System-on-Chip”, Flynn & Luk URL: www.ee.imperial.ac.uk/pcheung/ E-mail: [email protected] PYKC 6-Mar-08 E3.05 Digital System Design Topic 10 Slide 1 PYKC 6-Mar-08 E3.05 Digital System Design Topic 10 Slide 2 Basic concepts: Basic concepts: Bus basics: order and broadcast properties Cycles, messages and transactions X Communications on buses must be in strict order: serial nature of bus X Buses operate in units of cycles, Messages and transactions. • Cycles: A message requires a number of clock cycles to be sent from sender to receiver over the bus. • Message: These are logical unit of information. For example, a write message contains an address, control signals and the write data. • Transaction: A transaction consists of a sequence of messages which together form a transaction. For example, a memory read X It can broadcast a transaction – sending to multiple components simultaneously requires a memory read message and a reply with the requested data. PYKC 6-Mar-08 E3.05 Digital System Design Topic 10 Slide 3 PYKC 6-Mar-08 E3.05 Digital System Design Topic 10 Slide 4 Basic concepts: Synchronous vs Asynchronous Typical Source Synchronous Data Transfer PYKC 6-Mar-08 E3.05 Digital System Design Topic 10 Slide 5 PYKC 6-Mar-08 E3.05 Digital System Design Topic 10 Slide 6 Basic concepts: Basic concepts: Bus arbitration Bus pipelining X Only one bus master can control the us. X A transaction may take multiple cycles X Need some way of deciding who is master – may use a bus arbiter: X Overlap multiple transaction through pipelining: PYKC 6-Mar-08 E3.05 Digital System Design Topic 10 Slide 7 PYKC 6-Mar-08 E3.05 Digital System Design Topic 10 Slide 8 Basic concepts: Basic concepts: Split-transaction bus Split-transaction bus X A bus transaction can be divided into two or more phases, e.g. • “Request” phase • “Reply” phase X These can be split into two separate sub-transactions, which may or may not happen consecutively. If split, these must compete for the bus by arbitration. PYKC 6-Mar-08 E3.05 Digital System Design Topic 10 Slide 9 PYKC 6-Mar-08 E3.05 Digital System Design Topic 10 Slide 10 Basic concepts: Basic concepts: Pipelined only bus vs split-transaction bus Burst transfer mode PYKC 6-Mar-08 E3.05 Digital System Design Topic 10 Slide 11 PYKC 6-Mar-08 E3.05 Digital System Design Topic 10 Slide 12 Bus bandwidth Bus hierarchy PYKC 6-Mar-08 E3.05 Digital System Design Topic 10 Slide 13 PYKC 6-Mar-08 E3.05 Digital System Design Topic 10 Slide 14 AMBA bus AMBA Bus Design Goals X Based around ARM processor X Encourages modular design and design reuse • AHB – Advanced High-Performance Bus ³ Pipelining of Address / Data X Well defined interface protocol, clocking and reset ³ Split Transactions X Low-power support (helped by two-level partitioning) ³ Multiple Masters • APB – Advanced Peripheral Bus X On-chip test access – built-in structure for testing modules connected on ³ Low Power / Bandwidth Peripheral Bus the bus X Transactions on AHB • Bus master obtain access to the bus • Bus master initiates transfer • Bus slave provides response PYKC 6-Mar-08 E3.05 Digital System Design Topic 10 Slide 15 PYKC 6-Mar-08 E3.05 Digital System Design Topic 10 Slide 16 AMBA bus arbitration Simple AHB Transfer PYKC 6-Mar-08 E3.05 Digital System Design Topic 10 Slide 17 PYKC 6-Mar-08 E3.05 Digital System Design Topic 10 Slide 18 AHB Transfer with wait states Multiple transfers with Pipelining PYKC 6-Mar-08 E3.05 Digital System Design Topic 10 Slide 19 PYKC 6-Mar-08 E3.05 Digital System Design Topic 10 Slide 20 Burst mode transfer (undefined length) Slave Transfer Responses X 1. Complete transfer immediately (single cycle transfer) X 2. Insert one or more wait states to allow completion X 3. Signal error to indicate transfer failed X 4. Back of from the bus, try later (RE-TRY or SPLIT responses) PYKC 6-Mar-08 E3.05 Digital System Design Topic 10 Slide 21 PYKC 6-Mar-08 E3.05 Digital System Design Topic 10 Slide 22 Retry Respnses on the AHB bus Advanced Peripheral Bus (APB) PYKC 6-Mar-08 E3.05 Digital System Design Topic 10 Slide 23 PYKC 6-Mar-08 E3.05 Digital System Design Topic 10 Slide 24 IBM CoreConnect Bus CoreConnect vs AMBA PYKC 6-Mar-08 E3.05 Digital System Design Topic 10 Slide 25 PYKC 6-Mar-08 E3.05 Digital System Design Topic 10 Slide 26 Crossbar Switch Approach Network-on-chip approach X Uses asynchronous channels X Array of tiles X Different modules can run at X Each tile contains client logic and router different clock frequency logic X Globally Asychronous, Locally X 2-D mesh topology Synchronous (GALS) system X Uses data packets, not wires, for communication X Predictable delay, and noise PYKC 6-Mar-08 E3.05 Digital System Design Topic 10 Slide 27 PYKC 6-Mar-08 E3.05 Digital System Design Topic 10 Slide 28 2 Chapter 5 Interconnect Architectures are various types of on-chip memory serving as cache, data or instruction storage. Other IP blocks serving application-specific functions, such as graphics processors, video codecs and network control units, are integrated in the SOC. The IP blocks in the SOC module need to communicate with each other. External to the SOC module are off-chip memories, off-chip peripheral devices and mass storage devices. The cost and performance of the system therefore depends on both on-chip Chapter 5 and off-chip interconnect structure. On-chip interconnect architecture Interconnect Architecturesturesture Off-chip interconnect architecture On-chip Processor Memory Off-chipO Memory Off-chip 5.1 Introduction IP Block interface SOC designs usually involve the integrationtegrationn of intellectuaintellectuall property (IP) ccores, each Off-chipO separately designed and verified. System integratorsators can maximizemaximize the rere-use of design peripheralp efforts by providing a commonon backbone for SOC modules,mod to rereduced costs and to lower risks. Frequently themost important issue confrontingconfronting an SOCS integrator is the IP Block IP Block method by which the IP cores are connected together.toget FTF SOC interconnect alternativeslternatives extendxtend well beyond convenconventconventional computer buses. This Off-chipOff-c ASIC chapter provides an overview of three SOC interconnectinterconne architectures: bus, switch, On-chip Processor and Network-on-Chip.on-Chip. A number of bus architecturesarchitecturea developed specifically for SOC MemoryM technologyy are then described and compared.comp Switch-basedSw alternatives to bus based interconnectsnnects are considered, especially recenrrecent trends in SOC interconnects such as Network-on-Chipwork-on-Chipork-on-Chip technology. AAFTAF As we shallhall see, Network-on-Chip (NO(NOC) is more than an alternative to bus or switch Figure 5.1 Asimplified block diagram of an SOC module in a system context. technology.. It is often described at a higher level of abstraction, hiding the underlying physical interconnectinterconnects from the dedesigner. It is usually implemented by switch technol- ogy,, although in principleprincipl it canca also be a bus. To avoid confusion, we follow current Choosinghoosing a suitable interconnect architecarchitecture requires the understanding of a number SOC usageage and refer to interinterconnectint as a bus (usually no confusion), as a switch when of system level issues and specificatiocations.cat These are: there is acrossbar visibvisibleRAFT to the designer, and as a NOC when implemented by a RAR switch. In thehe NNOC caseca the switch is often more than a crossbar and could consist of 1. Communicationon bandwidth:bandwb the rate of information transfer between a mod- a distributeddinte intercinterconnect or a multistage switching network. ule and the surroundingsurroundisurroun environment in which it operates. Usually measured There is a greatgre deal of bus and computer interconnect literature. The units being in bytes/second, ththe bandwidth requirement of a module dictates to a large ex- connected aare sometimes referred to as agents (in buses) or nodes (in general intercon- tentent the type of interconnection required in order to achieve the overall system nectctDRD literature);liter we simply use the term units. Given that, at least at the current time, throughputughputDRAFTD specisp fication. SOCs only require a small number of units to be interconnected, the chapter provides 2. Communication latency: the time delay between a module requesting data asimplified view of the interconnect alternatives. and receiving a response to the request. Latency may or may not be impor- tant in terms of overall system performance. For example, long latency in a video streaming application usually has little or no effect on the user’s experi- 5.2 Overview: Interconnect Architectures ence. Watching a movie that is a couple of seconds later than when it is actually broadcast is of no consequence. In contrast, even a short latency in a two-way Figure 5.1 depicts a system which includes a SOC module. The SOC module typically mobile communication system can make it almost impossible to carry out a con- contains a number of IP blocks, one or more of which are processors.
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