DOCSLIB.ORG

Synopsys Powerpc for Developerworks

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Synopsys Powerpc for Developerworks Synthesizable “Power” – Using Process Portability to Embed PowerPC Cores in Your Chip Lonn Fiance Director, Strategic Alliances Synopsys Agenda • Synopsys overview • PowerPC embedded core overview • Synopsys’ Synthesizable PowerPC 405/440 offering • Questions and answers © 2005 Synopsys, Inc. Pg. 2; Global leader in EDA and IP 1400 1200 $1.1B revenue in FY04 1000 800 600 400 200 0 FY96 FY97 FY98 FY99 FY00 FY01 FY02 FY03 FY04 350 •• StrongStrong globalglobal presence:presence: 300 $285M on R&D in FY04 ~~ 4,4004,400 employees,employees, 60+60+ officesoffices 250 •• StrongStrong technicaltechnical innovation:innovation: 200 150 1600+1600+ R&DR&D eng.eng. (~26%(~26% ofof rev.)rev.) 100 •• StrongStrong customercustomer support:support: 50 1450+ applications engineers 0 1450+ applications engineers FY96 FY97 FY98 FY99 FY00 FY01 FY02 FY03 FY04 © 2005 Synopsys, Inc. Pg. 3; Synopsys in China Since 1995 Synopsys Offices National IC Design Chinese Harrbin University Incubation Centers Academy University Programs P of Sciences 35 locations PP Datang Beijing 200+ R&D Engineers Telecom P Tsinghua University PP Beijing PoPollytechnical University Wuxi Northern JiaoTong University Xian Jiaotong Partnerships Xian Jiaotong Peking University PP University SMIC Beijing College of Aeronautics Xi’an PP Shanghai Chengdu Hangzhou Zhejiang University Shanghai Jiao Tong University Tongji University Fudan University University of Electronics Science and Technology of China Shenzhen HKUST, HKUC, SCUST Hong Kong © 2005 Synopsys, Inc. Pg. 4; Most Trusted in EDA Industry Attribute in selecting vendor SNPS Rank Importance Best after-sales support 1 61% Offers competitive prices 3 59% Technology leader today 1 46% Technology leader in 3 years 1 39% Best support of open standards 2 37% Best integration w/other tools 2 36% Best integration with foundries & IP suppliers 1 35% Clear vision of future 1 33% Most ethical company 1 32% Best documentation 1 28% Knowledgeable sales reps 1 24% Well-managed company 1 23% Best training services 1 23% Best before-sales system support 2 12% Best Web site 1 7% Offers consulting design services 2 7% Source: 2004 EE Times Reader EDA Survey © 2005 Synopsys, Inc. Pg. 5; TTRTTR QQOORR R R O O C C Yield Yield Test Test Power Need Convergent Optimization SolutionPower Signal Integrity Signal Signal Integrity Signal Area Area © 2005 Synopsys, Inc. Pg. 6; Complete, Correlated And Concurrent IP Reuse Design Verification DFM Flows & Services © 2005 Synopsys, Inc. Pg. 7; Industry Leading Alliances Foundries ASIC Vendors PLD Vendors IP Vendors Library Vendors Synopsys strategic partnerships assure our customers meet their performance, cost, and schedule goals. © 2005 Synopsys, Inc. Pg. 8; Power Architecture Application Areas 970 970 970 750 Server WAN 750 Switch/Router 750 970 750 440 440 Games Workstations 440 440 3G Access / IP PDA Set-Top Box Gateway GPS, In-cabin, & Telematics 405 440 Personal 405 Communicator 405 405 Networked Digital Wireless LAN Storage Imaging In Auto In Hand In Home Networking IT/Storage Pervasive Computing © 2005 Synopsys, Inc. Pg. 9; IBM PowerPC® Licensable Cores PowerPC 440 Key Features 1.5mW/MHz 2.5mW/MHz 440-S •32-bit PowerPC Book E 440 •Superscalar, 2 inst/cycle 440 32K/32K 32K/32K •MMU, 1KB-256MB pages 32K/32K Fully 0.18um 130nm •128-bit PLB, 64GB addr 2 Synthesizable 15.5mm2 9.8mm PowerPC 405 1.9mW/MHz 0.9mW/MHz Key Features 405-S 405 405 •32-bit PowerPC Embedded 16K/16K 16K/16K •Scalar, 1 inst/cycle 16K/16K 130nm Fully •MMU, 1KB-16MB pages 0.18um 3.8mm2 Synthesizable 8.0mm2 •64-bit PLB, 4GB addr © 2005 Synopsys, Inc. Pg. 10; PowerPC 405 Features Architecture 32-bit PowerPC Embedded Application code compatible with all PowerPC 64b Processor Local Bus microprocessors 64b Processor Local Bus Special Hardware multiply / divide 16K 16K 16K 16K I-cache D-cache Features 24 DSP instructions (16x16+32) I-cache D-cache 32-bit x 32 general purpose registers I-cache D-cache I-cache D-cache CPU 5 Stage Pipeline control MMU control control MMU control Pipeline Single instruction per cycle Instruction Branch Instruction Branch Caches 16KB, 2-way set associative, 32-byte line, no Unit Unit Unit Unit locking, parity Execution MMU 64 entry UTLB – full associativity Execution GPRs Unit GPRs 4 entry ITLB, 8 entry DTLB Unit MAC 5 cycle miss penalty MAC Variable pages – 1KB to 16MB Timers Power Management Timers Power Management Branch Static Debug / Trace Interrupts Pred. Debug / Trace Interrupts Physical 32-bit (4GB physical address) Address 64- or 128-bit interface to Processor Local Bus (PLB) On-chip memory supported via PLB Debug JTAG and Trace FIFO ports Real-time, non-invasive trace supported © 2005 Synopsys, Inc. Pg. 11; PowerPC 440 Features Architecture 32-bit PowerPC Book E Application code compatible with all 128b Processor Local Bus 128b Processor Local Bus PowerPC microprocessors 32K 32K 32K 32K CPU Pipeline Two-way superscalar I-cache D-cache 7 Stages, out of order issue, execution and I-cache D-cache completion I-cache D-cache I-cache MMU D-cache control MMU control L1 Caches 32KB, 64-way set associative, transient and control control locked cache region mechanism, software Branch Instruction Unit Branch Instruction Unit Unit managed coherency, parity Unit MMU 64 entry UTLB – full associativity 4 entry ITLB, 8 entry DTLB Complex Complex 3 cycle ITLB/DTLB miss penalty Integer Simple Load / Integer Simple Load / Pipe Integer Store Pipe Integer Store Branch Pred. Dynamic Pipe Pipe Pipe Pipe MAC 16-entry BTAC, 4K-entry BHT MAC Timers Power Management Physical Addr 36-bit (64GB physical address) Timers Power Management Debug / Trace Interrupts Core Interfaces Three independent 128-bit PLB4 master Debug / Trace Interrupts ports (instruction read, data read, data write), each with separate address bus Debug JTAG and Trace FIFO ports Real-time, non-invasive trace supported © 2005 Synopsys, Inc. Pg. 12; The Power of Flexibility • Each application has unique requirements Business: cost, delivery time, existing supplier relationships, design services, etc. Technical: process technology, integration, packaging, performance, other IP, etc. Life cycle: process migration, multi- sourcing, cost reductions, strategic options • Process portability provides flexibility to address these requirements • Flexibility is key to proliferation © 2005 Synopsys, Inc. Pg. 13; Flexibility Creates Value • Design Value is a Example Trade-Offs complicated function Value = f(Area, Performance, Power, Yield, IP, Packaging, Process, Delivery Time, Reliability, Risk, Location) Performance • Complex interaction between the parameters • Intelligent tradeoffs Area or increase value Power Design specific © 2005 Synopsys, Inc. Pg. 14; PowerPC 405-S & 440-S Overview 1.5mW/MHz • Macro Objective: 2.5mW/MHz 440 440-S 440 32K/32K 32K/32K Technology independent, reusable 32K/32K 130nm Fully 180nm 9.8mm2 Synthesizable and fully synthesizable PowerPC 15.5mm2 cores 1.9mW/MHz 0.9mW/MHz 405 405-S • Design Objectives 405 16K/16K 16K/16K Fully 16K/16K 130nm Standard SRAM’s and Register Files Synthesizable 180nm 3.8mm2 for Caches and UTLB’s 8.0mm2 Maintain cycle compatibility with the existing PowerPC 4xx Target performance of 300 MHz (440-S) and 250 MHz (405-S) for Artisan TSMC 13 LVFSG Fault coverage goal of >98% Use a complete Synopsys tool flow • Verification Objectives Create a portable verification environment Create tests to verify the major architectural capabilities • Easy delivery and use via Synopsys DesignWare® © 2005 Synopsys, Inc. Pg. 15; Synopsys Power Solution - Design Flexibility and Portability • System C models System-level SystemC models Instrumented for System Studio • SoC Design Design View Implementation View CPU, SoC testbenches with test suites • Documentation Implementation scripts with README’s User Guide, Data Book, App Notes, etc. • Support Award-winning customer support Qualified design services and complimentary IP © 2005 Synopsys, Inc. Pg. 16; SystemC Models • C++ class library to model SoC hardware and processes • Used for system-level design Architectural analysis of processors, buses, custom logic, and IP • Explore hardware/software tradeoffs • SystemC is an open industry standard Tool and IP support from multiple companies • C++ basis allows concurrent development of hardware and software © 2005 Synopsys, Inc. Pg. 17; Synopsys SystemC Deliverables • Original models, SystemC Model List • PowerPC 405 Processor Core testing and • PowerPC 440 Processor Core • PLB4 (Processor Local Bus v4.x) validation from IBM • DMA Controller (PLB4) • DCR (Device Control Register) • Synopsys • UIC (Universal Interrupt Controller) distributes and • UART (Universal Asynchronous Receiver Transmitter) supports • MCMAL PLB4 (Multi-channel Memory Access Layer) • Instrumented for • Memory (DDR) Controller (PLB4) • EBC (External Bus Controller) System Studio • OPB (On Chip Peripheral Bus) • PLB4 to OPB Bridge • OPB to PLB4 Bridge • PCI-X to PLB4 • PCI-Express © 2005 Synopsys, Inc. Pg. 18; Design View coreKit Overview • “Black Box” Verilog Models for the PowerPC 4xx-S Fixed configuration to determine feasibility Cycle compatible VMC model of the 4xx-S VERA based CPU testbench Verilog Toplevel Timing model for WC operating conditions Testbench for Artisan TSMC 13 LVFSG Backend Interface PLB Slave/ IB M P L B Backend Slave Model All appropriate documentation (databook, Control (m em ory) IB M PLB Processor Local Bus (PLB) PLB Monitor Processor Local Bus (PLB) Arbiter datasheet, etc.) ICU Rd DCU Rd DCU Wr Interrupt Inte rru
Load more

Recommended publications
  • An Architecture and Compiler for Scalable On-Chip Communication
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. XX, NO. Y, MONTH 2004 1 An Architecture and Compiler for Scalable On-Chip Communication Jian Liang, Student Member, IEEE, Andrew Laffely, Sriram Srinivasan, and Russell Tessier, Member, IEEE Abstract— tion of communication resources. Significant amounts of arbi- A dramatic increase in single chip capacity has led to a tration across even a small number of components can quickly revolution in on-chip integration. Design reuse and ease-of- form a performance bottleneck, especially for data-intensive, implementation have became important aspects of the design pro- cess. This paper describes a new scalable single-chip communi- stream-based computation. This issue is made more complex cation architecture for heterogeneous resources, adaptive System- by the need to compile high-level representations of applica- On-a-Chip (aSOC), and supporting software for application map- tions to SoC environments. The heterogeneous nature of cores ping. This architecture exhibits hardware simplicity and opti- in terms of clock speed, resources, and processing capability mized support for compile-time scheduled communication. To il- makes cost modeling difficult. Additionally, communication lustrate the benefits of the architecture, four high-bandwidth sig- nal processing applications including an MPEG-2 video encoder modeling for interconnection with long wires and variable arbi- and a Doppler radar processor have been mapped to a prototype tration protocols limits performance predictability required by aSOC device using our design mapping technology. Through ex- computation scheduling. perimentation it is shown that aSOC communication outperforms Our platform for on-chip interconnect, adaptive System-On- a hierarchical bus-based system-on-chip (SoC) approach by up to a-Chip (aSOC), is a modular communications architecture.
    [Show full text]
  • On-Chip Interconnect Schemes for Reconfigurable System-On-Chip
    On-chip Interconnect Schemes for Reconfigurable System-on-Chip Andy S. Lee, Neil W. Bergmann. School of ITEE, The University of Queensland, Brisbane Australia {andy, n.bergmann} @itee.uq.edu.au ABSTRACT On-chip communication architectures can have a great influence on the speed and area of System-on-Chip designs, and this influence is expected to be even more pronounced on reconfigurable System-on-Chip (rSoC) designs. To date, little research has been conducted on the performance implications of different on-chip communication architectures for rSoC designs. This paper motivates the need for such research and analyses current and proposed interconnect technologies for rSoC design. The paper also describes work in progress on implementation of a simple serial bus and a packet-switched network, as well as a methodology for quantitatively evaluating the performance of these interconnection structures in comparison to conventional buses. Keywords: FPGAs, Reconfigurable Logic, System-on-Chip 1. INTRODUCTION System-on-chip (SoC) technology has evolved as the predominant circuit design methodology for custom ASICs. SoC technology moves design from the circuit level to the system level, concentrating on the selection of appropriate pre-designed IP Blocks, and their interconnection into a complete system. However, modern ASIC design and fabrication are expensive. Design tools may cost many hundreds of thousands of dollars, while tooling and mask costs for large SoC designs now approach $1million. For low volume applications, and especially for research and development projects in universities, reconfigurable System-on-Chip (rSoC) technology is more cost effective. Like conventional SoC design, rSoC involves the assembly of predefined IP blocks (such as processors and peripherals) and their interconnection.
    [Show full text]
  • AXI Reference Guide
    AXI Reference Guide [Guide Subtitle] [optional] UG761 (v13.4) January 18, 2012 [optional] Xilinx is providing this product documentation, hereinafter “Information,” to you “AS IS” with no warranty of any kind, express or implied. Xilinx makes no representation that the Information, or any particular implementation thereof, is free from any claims of infringement. You are responsible for obtaining any rights you may require for any implementation based on the Information. All specifications are subject to change without notice. XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE INFORMATION OR ANY IMPLEMENTATION BASED THEREON, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF INFRINGEMENT AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Except as stated herein, none of the Information may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. © Copyright 2012 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, Kintex, Artix, ISE, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. ARM® and AMBA® are registered trademarks of ARM in the EU and other countries. All other trademarks are the property of their respective owners. Revision History The following table shows the revision history for this document: . Date Version Description of Revisions 03/01/2011 13.1 Second Xilinx release.
    [Show full text]
  • Wishbone Bus Architecture – a Survey and Comparison
    International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.2, April 2012 WISHBONE BUS ARCHITECTURE – A SURVEY AND COMPARISON Mohandeep Sharma 1 and Dilip Kumar 2 1Department of VLSI Design, Center for Development of Advanced Computing, Mohali, India [email protected] 2ACS - Division, Center for Development of Advanced Computing, Mohali, India [email protected] ABSTRACT The performance of an on-chip interconnection architecture used for communication between IP cores depends on the efficiency of its bus architecture. Any bus architecture having advantages of faster bus clock speed, extra data transfer cycle, improved bus width and throughput is highly desirable for a low cost, reduced time-to-market and efficient System-on-Chip (SoC). This paper presents a survey of WISHBONE bus architecture and its comparison with three other on-chip bus architectures viz. Advanced Microcontroller Bus Architecture (AMBA) by ARM, CoreConnect by IBM and Avalon by Altera. The WISHBONE Bus Architecture by Silicore Corporation appears to be gaining an upper edge over the other three bus architecture types because of its special performance parameters like the use of flexible arbitration scheme and additional data transfer cycle (Read-Modify-Write cycle). Moreover, its IP Cores are available free for use requiring neither any registration nor any agreement or license. KEYWORDS SoC buses, WISHBONE Bus, WISHBONE Interface 1. INTRODUCTION The introduction and advancement of multimillion-gate chips technology with new levels of integration in the form of the system-on-chip (SoC) design has brought a revolution in the modern electronics industry. With the evolution of shrinking process technologies and increasing design sizes [1], manufacturers are integrating increasing numbers of components on a chip.
    [Show full text]
  • An Overview of Soc Buses
    Vojin Oklobdzija/Digital Systems and Applications 6195_C007 Page Proof page 1 11.7.2007 2:16am Compositor Name: JGanesan 7 An Overview of SoC Buses 7.1 Introduction....................................................................... 7-1 7.2 On-Chip Communication Architectures ........................ 7-2 Background . Topologies . On-Chip Communication Protocols . Other Interconnect Issues . Advantages and M. Mitic´ Disadvantages of On-Chip Buses M. Stojcˇev 7.3 System-On-Chip Buses ..................................................... 7-4 AMBA Bus . Avalon . CoreConnect . STBus . Wishbone . University of Nisˇ CoreFrame . Manchester Asynchronous Bus for Low Energy . Z. Stamenkovic´ PI Bus . Open Core Protocol . Virtual Component Interface . m IHP GmbH—Innovations for High SiliconBackplane Network Performance Microelectronics 7.4 Summary.......................................................................... 7-15 7.1 Introduction The electronics industry has entered the era of multimillion-gate chips, and there is no turning back. This technology promises new levels of integration on a single chip, called the system-on-a-chip (SoC) design, but also presents significant challenges to the chip designers. Processing cores on a single chip may number well into the high tens within the next decade, given the current rate of advancements [1]. Interconnection networks in such an environment are, therefore, becoming more and more important [2]. Currently, on-chip interconnection networks are mostly implemented using buses. For SoC applications, design reuse becomes easier if standard internal connection buses are used for interconnecting components of the design. Design teams developing modules intended for future reuse can design interfaces for the standard bus around their particular modules. This allows future designers to slot the reuse module into their new design simply, which is also based around the same standard bus [3].
    [Show full text]
  • Vitex-II Pro: the Platfom for Programmable Systems
    The Platform for Programmable Systems Developing high-performance systems with embedded pro- cessors and fast I/O is quite a challenge. To be successful, you Industry’s Fastest must solve the difficult technical FPGA Fabric problems of hardware and Up to 4 IBM PowerPC™ Processors immersed in FPGA Fabric software development, I/O Up to 24 Embedded Rocket I/O™ Multi-Gigabit Transceivers interfacing, and third-party IP Up to 12 Digital Clock Managers integration; you must rigorously XCITE Digitally Controlled Impedance Technology simulate, test, and verify your Up to 556 18x18 Multipliers design; and you must meet Over 10 Mb Embedded Block RAM increasingly difficult deadlines with a cost-effective product that can adapt as industry standards Virtex-II Pro Platform FPGA Family quickly evolve. Benefits are Overwhelming The revolutionary Virtex-II Pro™ Because all of the critical system components (such as microprocessors, memory, IP peripherals, programmable logic, and high-performance I/O) are located on one family, based on the highly successful programmable logic device, you gain a significant performance and productivity Virtex-II architecture, provides a advantage. The Virtex-II Pro FPGA family, along with the Wind River Systems embedded tools and Xilinx ISE development environment, is the fastest, easiest, and unique platform for developing most cost effective method for developing your next generation high-performance high-performance microprocessor- programmable systems. and I/O-intensive applications. With Virtex-II Pro FPGAs, you get: Virtex-II Pro FPGAs provide up to • On-Chip IBM PowerPC Processors – You get maximum performance and ease of use because these are hard cores, operating at peak efficiency, tightly coupled with ™ four embedded 32-bit IBM PowerPC all memory and programmable logic resources.
    [Show full text]
  • Computing Platforms Chapter 4
    Computing Platforms Chapter 4 COE 306: Introduction to Embedded Systems Dr. Abdulaziz Tabbakh Computer Engineering Department College of Computer Sciences and Engineering King Fahd University of Petroleum and Minerals [Adapted from slides of Dr. A. El-Maleh, COE 306, KFUPM] Next . Basic Computing Platforms The CPU bus Direct Memory Access (DMA) System Bus Configurations ARM Bus: AMBA 2.0 Memory Components Embedded Platforms Platform-Level Performance Computing Platforms COE 306– Introduction to Embedded System– KFUPM slide 2 Embedded Systems Overview Actuator Output Analog/Digital Sensor Input Analog/Digital CPU Memory Embedded Computer Computing Platforms COE 306– Introduction to Embedded System– KFUPM slide 3 Computing Platforms Computing platforms are created using microprocessors, I/O devices, and memory components A CPU bus is required to connect the CPU to other devices Software is required to implement an application Embedded system software is closely tied to the hardware Computing Platform: hardware and software Computing Platforms COE 306– Introduction to Embedded System– KFUPM slide 4 Computing Platform A typical computing platform includes several major hardware components: The CPU provides basic computational facilities. RAM is used for program and data storage. ROM holds the boot program and some permanent data. A DMA controller provides direct memory access capabilities. Timers are used by the operating system A high-speed bus, connected to the CPU bus through a bridge, allows fast devices to communicate efficiently with the rest of the system. A low-speed bus provides an inexpensive way to connect simpler devices and may be necessary for backward compatibility as well. Computing Platforms COE 306– Introduction to Embedded System– KFUPM slide 5 Platform Hardware Components Computer systems may have one or more bus Buses are classified by their overall performance: lows peed, high- speed.
    [Show full text]
  • Xilinx XAPP1000: Reference System : Plbv46 PCI Express in a ML555
    Application Note: Embedded Processing Reference System: PLBv46 Endpoint Bridge R for PCI Express in a ML555 PCI/PCI Express Development Platform XAPP1000 (v1.0.1) May 6, 2008 Author: Lester Sanders Abstract This reference system demonstrates the functionality of the PLBv46 Endpoint Bridge for PCI Express® used in the Xilinx ML555 PCI/PCI Express Development Platform. The PLBv46 Endpoint Bridge is used in x1 and x4 PCIe® lane configurations. The PLBv46 Endpoint Bridge uses the Xilinx Endpoint core for PCI Express in the Virtex®-5 XC5VLX50T FPGA. The PLBv46 Bus is an IBM CoreConnect bus used for connecting the IBM PPC405 or PPC440 microprocessors, which are implemented as hard blocks on Xilinx Virtex FPGAs, and the Xilinx Microblaze microprocessor to Xilinx IP. A variety of tests generate and analyze PCIe traffic for hardware validation of the PLBv46 Endpoint Bridge. PCIe transactions are generated and analyzed by Catalyst and LeCroy test equipment. For endpoint to root complex transactions, the pcie_dma software application generates DMA transactions which move data over the PCIe link(s). For root complex to endpoint transactions, Catalyst and LeCroy scripts generate PCIe traffic. A Catalyst script which configures the PLBv46 Endpoint Bridge and performs memory write/read transactions is discussed. The steps to use Catalyst to measure PCIe performance are given, and performance results are provided.The principal intent of the performance testing is to illustrate how performance measurements can be done. Two stand-alone tools, PCItree and Memory Endpoint Test, are used to write and read PLBv46 Endpoint Bridge configuration space and memory in a PC environment.
    [Show full text]
  • Design and Implementation of Clocked Open Core Protocol Interfaces for Intellectual Property Cores and On-Chip Network Fabric
    DESIGN AND IMPLEMENTATION OF CLOCKED OPEN CORE PROTOCOL INTERFACES FOR INTELLECTUAL PROPERTY CORES AND ON-CHIP NETWORK FABRIC by Raghu Prasad Gudla A thesis submitted to the faculty of The University of Utah in partial fulfillment of the requirements for the degree of Master of Science Department of Electrical and Computer Engineering The University of Utah May 2011 Copyright c Raghu Prasad Gudla 2011 All Rights Reserved The University of Utah Graduate School STATEMENT OF THESIS APPROVAL This thesis of Raghu Prasad Gudla has been approved by the following supervisory committee members: Kenneth S. Stevens , Chair 01/14/2011 Date Approved Alan L. Davis , Member 01/14/2011 Date Approved Erik L. Brunvand , Member 01/14/2011 Date Approved and by Gianluca Lazzi , Chair of the Department of Electrical and Computer Engineering and by Charles A. Wight, Dean of the Graduate School. ABSTRACT This thesis designs, implements, and evaluates modular Open Core Protocol (OCP) interfaces for Intellectual Property (IP) cores and Network-on-Chip (NoC) that re- duces System-On-Chip (SoC) design time and enables research on different archi- tectural sequencing control methods. To utilize the NoCs design time optimization feature at the boundaries, a standardized industry socket was required, which can address the SoC shorter time-to-market requirements, design issues, and also the subsequent reuse of developed IP cores. OCP is an open industry standard socket interface specification used in this research to enable the IP cores reusability across multiple SoC designs. This research work designs and implements clocked OCP interfaces between IP cores and On-Chip Network Fabric (NoC), in single- and multi- frequency clocked domains.
    [Show full text]
  • New Virtex™-II Pro Family Extends Platform FPGA Capability with Multi
    Virtex-II Pro Platform FPGA Family Product Backgrounder The Virtex-II Pro Platform FPGA solution is arguably the most technically sophisticated silicon and software product in the programmable logic industry. The goal in developing the Virtex-II Pro FPGA was to revolutionize system architecture “from the ground up.” To achieve that objective, circuit engineers and system architects from IBM, Mindspeed, and Xilinx co- developed this advanced Platform FPGA. Engineering teams from top embedded systems companies, including Wind River Systems and Celoxica, worked together with Xilinx software teams to develop the systems software and IP solutions that enable new system architecture. The result is the first Platform FPGA solution capable of implementing ultra-high bandwidth SoC (system-on-a-chip) designs that were previously the exclusive domain of custom ASICs, yet with the flexibility and low development cost of programmable logic. This new solution is expected to usher a new era of leading-edge system architectures in networking applications, embedded systems, and digital signal processing systems. Virtex-II Pro Family Features • Five family members with 3,168 to 50,832 logic cells and 216 to 3,888 Kbits of Block RAM • Based upon Virtex-II IP-Immersion architecture • Multi-gigabit (3.125 Gb/s) serial transceiver blocks, up to 16 per device • PowerPC embedded processor cores, up to four per device Virtex-II Pro Family Key Value Proposition • Platform for Programmable Systems • Enables architectural synthesis • Delivers next generation connectivity standards • Enables a new development paradigm • Delivers leading edge price/performance value Virtex-II Pro Family Highlights The Virtex-II Pro family consists of five members, each with four to 16 RocketIO™ multi- gigabit transceivers based on the Mindspeed SkyRail™ technology.
    [Show full text]
  • View of the Thesis
    UNIVERSITY OF CINCINNATI Date:___________________ I, _________________________________________________________, hereby submit this work as part of the requirements for the degree of: in: It is entitled: This work and its defense approved by: Chair: _______________________________ _______________________________ _______________________________ _______________________________ _______________________________ Novel Methodologies for Efficient Networks-on-Chip implementation on Reconfigurable Devices A Dissertation submitted to the Division of Research and Advanced Studies of the University of Cincinnati in partial fulfillment of the requirements for the degree of DOCTOR OF PHILOSOPHY in the Department of Electrical and Computer Engineering of the College of Engineering November 2007 by Balasubramanian Sethuraman Bachelor of Engineering (B.E.) in Computer Science & Engineering Sri Venkateswara College of Engineering University of Madras, Chennai, Tamil Nadu, India 2002 Thesis Advisor and Committee Chair: Dr. Ranga Vemuri Abstract International Technology Roadmap for Semiconductors (ITRS) project the latest trend moving towards a system-level and platform-based design, involving large percent- age of design reuse. Different Intellectual Property (IP) cores, including processor and memory, are interconnected to build a typical System-on-Chip (SoC) architectures. Larger SoC designs dictate the data communication to happen over the global interconnects. At 45 nm and below, interconnects have profound impact on the performance (and power), due to
    [Show full text]
  • Automated Bus Generation for Multi-Processor Soc Design
    AUTOMATED BUS GENERATION FOR MULTI-PROCESSOR SOC DESIGN A Dissertation Presented to The Academic Faculty by Kyeong Keol Ryu In Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy School of Electrical and Computer Engineering Georgia Institute of Technology June 2004 AUTOMATED BUS GENERATION FOR MULTI-PROCESSOR SOC DESIGN Approved by: Dr. Vincent J. Mooney III, Adviser Dr. Jeffrey A. Davis Dr. Sudhakar Yalamanchili Dr. Paul Benkeser Dr. Thad Starner Date Approved: June 11, 2004 Dedicated to my wife, Hyejung Hyeon, my parents, and my parents-in-law iii ACKNOWLEDGMENTS This work could have not been finished without the support and sacrifice of many people I had to express my gratitude. First of all, I would like to deeply thank my adviser Vincent J. Mooney III. He has supported and encouraged me to develop my dissertation with his enthusiasm and professionalism throughout all stages of my Ph.D. program. He has been a great source of ideas and provided me with invaluable feedback. In addition, Dr. Mooney has been helping me improve my English skills with his consideration. I would also like to extend my appreciation to Dr. Jeffrey Davis, Dr. Sudhakar Yalamanchili, Dr. Paul Benkeser, and Dr. Thad Starner for serving on the committee and offering constructive comments. I have to thank all Hardware/Software Codesign group members for their helps and friendship. It is obvious that, without many helps by them, my long journey at Georgia Tech would have been much harder and lonelier. Also, I wish to thank my friends, Dr. Chang-ho Lee, Dr.
    [Show full text]