Synopsys Powerpc for Developerworks

Synthesizable “Power” – Using Process Portability to Embed PowerPC Cores in Your Chip

Lonn Fiance Director, Strategic Alliances Synopsys Agenda

• Synopsys overview • PowerPC embedded core overview • Synopsys’ Synthesizable PowerPC 405/440 offering • Questions and answers

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0 FY96 FY97 FY98 FY99 FY00 FY01 FY02 FY03 FY04

350 •• StrongStrong globalglobal presence:presence: 300 $285M on R&D in FY04

~~ 4,4004,400 employees,employees, 60+60+ officesoffices 250 •• StrongStrong technicaltechnical innovation:innovation: 200 150 1600+1600+ R&DR&D eng.eng. (~26%(~26% ofof rev.)rev.) 100

•• StrongStrong customercustomer support:support: 50 1450+ applications engineers 0 1450+ applications engineers FY96 FY97 FY98 FY99 FY00 FY01 FY02 FY03 FY04

Synopsys Offices National IC Design Chinese Harrbin University Incubation Centers Academy University Programs P of Sciences 35 locations PP Datang Beijing 200+ R&D Engineers Telecom P Tsinghua University PP Beijing PoPollytechnical University Wuxi Northern JiaoTong University Xian Jiaotong Partnerships Xian Jiaotong Peking University PP University SMIC Beijing College of Aeronautics Xi’an PP Shanghai Chengdu Hangzhou Zhejiang University Shanghai Jiao Tong University Tongji University Fudan University University of Electronics Science and Technology of China Shenzhen HKUST, HKUC, SCUST Hong Kong

Attribute in selecting vendor SNPS Rank Importance Best after-sales support 1 61% Offers competitive prices 3 59% Technology leader today 1 46% Technology leader in 3 years 1 39% Best support of open standards 2 37% Best integration w/other tools 2 36% Best integration with foundries & IP suppliers 1 35% Clear vision of future 1 33% Most ethical company 1 32% Best documentation 1 28% Knowledgeable sales reps 1 24% Well-managed company 1 23% Best training services 1 23% Best before-sales system support 2 12% Best Web site 1 7% Offers consulting design services 2 7%

QQQ OOO RRR

TTRTTRTTR Test Test Yield Area Yield Area Power Power Signal Integrity Signal Integrity

RR OO CC

IP Reuse

Design Verification

DFM Flows & Services

Foundries ASIC Vendors PLD Vendors

IP Vendors Library Vendors Synopsys strategic partnerships assure our customers meet their performance, cost, and schedule goals.

970 970 970

750 Server WAN 750 Switch/Router 750 970

750 440 440 Games Workstations 440 440

3G Access / IP PDA Set-Top Box Gateway GPS, In-cabin, & Telematics

405 440 Personal 405 Communicator 405 405 Networked Digital Wireless LAN Storage Imaging In Auto In Hand In Home Networking IT/Storage Pervasive Computing

PowerPC 440

Key Features 1.5mW/MHz 2.5mW/MHz 440-S •32-bit PowerPC Book E 440 •Superscalar, 2 inst/cycle 440 32K/32K 32K/32K •MMU, 1KB-256MB pages 32K/32K Fully 0.18um 130nm •128-bit PLB, 64GB addr 2 Synthesizable 15.5mm2 9.8mm

PowerPC 405

1.9mW/MHz 0.9mW/MHz Key Features 405-S 405 405 •32-bit PowerPC Embedded 16K/16K 16K/16K •Scalar, 1 inst/cycle 16K/16K 130nm Fully •MMU, 1KB-16MB pages 0.18um 3.8mm2 Synthesizable 8.0mm2 •64-bit PLB, 4GB addr

Architecture 32-bit PowerPC Embedded Application code compatible with all PowerPC 64b Processor Local Bus microprocessors 64b Processor Local Bus

Special Hardware multiply / divide 16K 16K 16K 16K I-cache D-cache Features 24 DSP instructions (16x16+32) I-cache D-cache 32-bit x 32 general purpose registers I-cache D-cache I-cache D-cache CPU 5 Stage Pipeline control MMU control control MMU control Pipeline Single instruction per cycle Instruction Branch Instruction Branch Caches 16KB, 2-way set associative, 32-byte line, no Unit Unit Unit Unit locking, parity Execution MMU 64 entry UTLB – full associativity Execution GPRs Unit GPRs 4 entry ITLB, 8 entry DTLB Unit MAC 5 cycle miss penalty MAC Variable pages – 1KB to 16MB Timers Power Management Timers Power Management Branch Static Debug / Trace Interrupts Pred. Debug / Trace Interrupts Physical 32-bit (4GB physical address) Address 64- or 128-bit interface to Processor Local Bus (PLB) On-chip memory supported via PLB Debug JTAG and Trace FIFO ports Real-time, non-invasive trace supported © 2005 Synopsys, Inc. Pg. 11; PowerPC 440 Features

Architecture 32-bit PowerPC Book E Application code compatible with all 128b Processor Local Bus 128b Processor Local Bus PowerPC microprocessors 32K 32K 32K 32K CPU Pipeline Two-way superscalar I-cache D-cache 7 Stages, out of order issue, execution and I-cache D-cache completion I-cache D-cache I-cache MMU D-cache control MMU control L1 Caches 32KB, 64-way set associative, transient and control control locked cache region mechanism, software Branch Instruction Unit Branch Instruction Unit Unit managed coherency, parity Unit MMU 64 entry UTLB – full associativity 4 entry ITLB, 8 entry DTLB Complex Complex 3 cycle ITLB/DTLB miss penalty Integer Simple Load / Integer Simple Load / Pipe Integer Store Pipe Integer Store Branch Pred. Dynamic Pipe Pipe Pipe Pipe MAC 16-entry BTAC, 4K-entry BHT MAC Timers Power Management Physical Addr 36-bit (64GB physical address) Timers Power Management Debug / Trace Interrupts Core Interfaces Three independent 128-bit PLB4 master Debug / Trace Interrupts ports (instruction read, data read, data write), each with separate address bus Debug JTAG and Trace FIFO ports Real-time, non-invasive trace supported

• Each application has unique requirements Business: cost, delivery time, existing supplier relationships, design services, etc. Technical: process technology, integration, packaging, performance, other IP, etc. Life cycle: process migration, multi- sourcing, cost reductions, strategic options • Process portability provides flexibility to address these requirements • Flexibility is key to proliferation

• Design Value is a Example Trade-Offs complicated function Value = f(Area, Performance, Power, Yield, IP, Packaging, Process, Delivery Time, Reliability, Risk, Location) Performance • Complex interaction between the parameters • Intelligent tradeoffs Area or increase value Power Design specific

1.5mW/MHz • Macro Objective: 2.5mW/MHz 440 440-S 440 32K/32K 32K/32K Technology independent, reusable 32K/32K 130nm Fully 180nm 9.8mm2 Synthesizable and fully synthesizable PowerPC 15.5mm2 cores 1.9mW/MHz 0.9mW/MHz 405 405-S • Design Objectives 405 16K/16K 16K/16K Fully 16K/16K 130nm Standard SRAM’s and Register Files Synthesizable 180nm 3.8mm2 for Caches and UTLB’s 8.0mm2 Maintain cycle compatibility with the existing PowerPC 4xx Target performance of 300 MHz (440-S) and 250 MHz (405-S) for Artisan TSMC 13 LVFSG Fault coverage goal of >98% Use a complete Synopsys tool flow • Verification Objectives Create a portable verification environment Create tests to verify the major architectural capabilities • Easy delivery and use via Synopsys DesignWare®

© 2005 Synopsys, Inc. Pg. 15; Synopsys Power Solution - Design Flexibility and Portability • System C models System-level SystemC models Instrumented for System Studio • SoC Design Design View Implementation View CPU, SoC testbenches with test suites • Documentation Implementation scripts with README’s User Guide, Data Book, App Notes, etc. • Support Award-winning customer support Qualified design services and complimentary IP

• C++ class library to model SoC hardware and processes • Used for system-level design Architectural analysis of processors, buses, custom logic, and IP • Explore hardware/software tradeoffs • SystemC is an open industry standard Tool and IP support from multiple companies • C++ basis allows concurrent development of hardware and software

• Original models, SystemC Model List • PowerPC 405 Processor Core testing and • PowerPC 440 Processor Core • PLB4 (Processor Local Bus v4.x) validation from IBM • DMA Controller (PLB4) • DCR (Device Control Register) • Synopsys • UIC (Universal Interrupt Controller) distributes and • UART (Universal Asynchronous Receiver Transmitter) supports • MCMAL PLB4 (Multi-channel Memory Access Layer) • Instrumented for • Memory (DDR) Controller (PLB4) • EBC (External Bus Controller) System Studio • OPB (On Chip Peripheral Bus) • PLB4 to OPB Bridge • OPB to PLB4 Bridge • PCI-X to PLB4 • PCI-Express

© 2005 Synopsys, Inc. Pg. 18; Design View coreKit Overview • “Black Box” Verilog Models for the PowerPC 4xx-S Fixed configuration to determine feasibility Cycle compatible VMC model of the 4xx-S VERA based CPU testbench Verilog Toplevel Timing model for WC operating conditions Testbench for Artisan TSMC 13 LVFSG Backend Interface PLB Slave/ IB M P L B Backend Slave Model All appropriate documentation (databook, Control (m em ory) IB M PLB Processor Local Bus (PLB) PLB Monitor Processor Local Bus (PLB) Arbiter

datasheet, etc.) ICU Rd DCU Rd DCU Wr Interrupt Inte rru p t pin s Ctrl Model

JTAG JT A G Interface 440 Core • PLB-to-AHB Bridge Verilog Model Model DCR DCR Bus Model

DCR Cycle compatible VMC model of the Monitor Clock and Reset Logic VERA Models IBM PLB Model Toolkit PLB PLB2AHB Bridge PLB PLB PLB PLB M aster Monitor M aster Slave1 Slave2 (PPC440)

r DCR e t B i PLB (128-bits) b PL

VERA based SOC testbench for the Ar DCR DCR Monitor

hclk PLB2AHB Bridge DCR PLB2AHB Bridge SYS_plbClk (PLB Slave 3) Slave (AHB M aster 2) dcr_clk DCR DCR Slave

DW AMBA VIP r e

Application note t i AHB (32/64/128-bits) b AHB Ar

AHB AHB AHB AHB Master1 Master3 Slave1 Slave3

AHB • Available to DesignWare licensees AHB Slave2 Monitor DW AMBA VIP

at no additional charge These IP's are not delivered as a part of the corekit, but has to be installed separately. However the testbench will be instantiating these com ponents.

Verilog Toplevel Testbench

Backend Interface

PLB Slave/ IB M P L B Backend Slave Model Control (m em ory)

IB M PLB ProcessorP rLococessoalr L oBcaul Bsu s( (PLLB)B) PLB Monitor Arbiter

ICU Rd DCU Rd DCU Wr Interrupt In te rru p t p in s Ctrl Model

JTAG JT A G Interface Model 440 Core

DCR DCR Bus Model

DCR Monitor Clock and Reset Logic VERA Models

IBM PLB Model Toolkit PLB Monitor PLB PLB PLB PLB M aster Master Slave1 Slave2 (PPC440)

r DCR te B PLB (128-bits) PL

Arbi DCR DCR Monitor

hclk PLB2AHB Bridge DCR SYS_plbClk (PLB Slave 3) Slave (AHB M aster 2) dcr_clk DCR DCR Slave

DW AMBA VIP r B te AHB (32/64/128-bits) AH Arbi

AHB AHB AHB AHB Master1 Master3 Slave1 Slave3

AHB AHB Slave2 Monitor DW AMBA VIP

These IP's are not delivered as a part of the corekit, but has to be installed separately. However the testbench will be instantiating these com ponents.

© 2005 Synopsys, Inc. Pg. 21; Implementation View coreKit Overview • RTL source for PowerPC core and PLB-to-AHB Bridge Configurable via coreAssembler Portable RTL validated by both IBM and Synopsys 128-bit Processor Local Bus 32KB 32KB I-cache D-cache • Implementation scripts with documentation w/parity w/parity

RTL simulation in an automated verification environment I-cache D-cache MMU Default floor plans Control Control Instruction Branch Integration of technology specific RAMs Unit Unit Logical and physical synthesis with clock tree synthesis Complex Simple Load / Scan insertion and ATPG Integer Integer Store Pipe Pipe Pipe Formal verification MAC

Power optimization and analysis Timers Power Management ¾ Complete RTL-to-GDSII capability Debug/Trace Interrupts PowerPC 440 Core • Documentation for SoC integration User Guide, Data Book App Notes • Licensing PowerPC license from IBM DesignWare license from Synopsys

© 2005 Synopsys, Inc. Pg. 22; Design View Flow Implementation View Flow Install Implementation Install Design View coreKit View coreKit Create coreConsultant workspace Create coreConsultant workspace Configure RTL

Install VMC Model Simulate configured RTL in Integrate technology standalone verification specific RAMs environment Simulate VMC Model Synthesize (RTL-to- in standalone verification environment Simulate configured RTL in gates) application verification environment Simulate VMC Model Insert scan in application verification environment Run STA Create floorplan Synthesize application logic using Formally verify gate- PowerPC 4xx Star IP CPU’s timing level netlist model to check approximate timing Run physical synthesis Simulate gate-level netlist

Get Implementation Create test vectors View coreKit Perform power analysis

Product Capability VCS® RTL simulation Vera Verification Testbench Design Compiler® Logic synthesis Physical Compiler® Physical synthesis JupiterXT™ Design planning Astro™ CTS scripts for detailed placement and routing DFT Compiler Design-for-test insertion TetraMAX® Test pattern generation DesignWare BIST Built-In-Self-Test capability Power Compiler™ Power optimization PrimePower Full-chip power analysis

32KB 32KB I-cache D-cache w/parity w/parity

DCA DCA I-cache D-cache MMU top array bottom array Control Control

Instruction Branch Unit Unit UTLB

Complex Simple Load / Integer Integer Store ICA ICA Pipe Pipe Pipe top array bottom array MAC BHT SRAM Timers Power Management Debug/Trace Interrupts PowerPC 440 Core

64-bit Processor Local Bus

16K 16K I Cache I Cache I-cache D-cache

I-cache D-cache MMU control control

Instruction Branch Unit Unit

D Cache D Cache Execution GPRs Unit MAC

Timers Power Mgmt Debug/Trace Interrupts

DesignWare Star IP DesignWare Cores DesignWare PCI Express, PCI-X, Verification DesignWare Library USB 2.0, USB OTG, IBM PowerPC 440 IEEE 1394, etc. AMBA PCI Express PCI On-Chip Bus PCI-X Serial I/O Datapath, AMBA IP, Memory, USB 2.0 Verification IP, Building IEEE 1394 Block IP, 8051, 6811, etc. Ethernet Memory DesignWare Library etc.

DesignWare Star IP Microprocessor cores from leading Star IP providers DesignWare Library Infrastructure IP, including high-speed datapath generators DesignWare Cores Portfolio of digital and analog connectivity IP DesignWare Verification Library Simulation models of buses & I/O standards

DesignWare Star IP DesignWare Cores DesignWare Verification PCI Express, PCI -X, DesignWare Library USB 2.0, USB OTG, IBM PowerPC440/405 • Broad Availability IEEE 1394, etc. AMBA PCI Express PCI 25,000+ DesignWare users On-Chip Bus PCI-X Serial I/O USB 2.0 worldwide Datapath, AMBA IP, Memory, Verification IP, Building IEEE 1394 Ethernet Block IP, 8051, 6811, etc. • Availability of supporting Memory IP components DesignWare Library etc. Fully Integrated with AMBA™ peripherals • AMBA AHB/APB w/ automated subsystem assembly • All DesignWare peripherals supported Native CoreConnect™ interface retained and supported • Industry recognized first-tier customer support Experienced technical support infrastructure • Tested with complete design flow

• All program objectives achieved Cycle compatibility with existing 440 and 405 cores Single cycle cache access Target performance of 300 MHz (440-S) and 250 MHz (405-S) achieved Portable verification environment and critical test cases packaged in core delivery • Synopsys is a “one-stop shop” for synthesizable PowerPC 440 and 405 cores Complete tool flow from RTL to CTS Knowledge of CoreConnect and AMBA peripherals Supported through DesignWare Synopsys Professional Services are experts in PowerPC core and system implementations

© 2005 Synopsys, Inc. Pg. 29; Synopsys and Power A Complete and Flexible Solution C o Partners IBM m Power.org p Foundries le te PowerPC experience S Services y Low power, SoC design n Complete Flow Expertise o p s y IP Distribution & support (DesignWare) s Proven Reusability Methodology S #1 Connectivity IP provider o Core Connect and AMBA IP lu t io Tools System-Level Design Capability n Complete Functional Verification Complete PowerPC and SoC Implementation Flow Post GDS Solution (OPC, PSM, fracturing)