PCI System Architecture Fourth Edition

Total Page:16

File Type:pdf, Size:1020Kb

PCI System Architecture Fourth Edition world-class technical training Are your company’s technical training needs being addressed in the most effective manner? MindShare has over 25 years experience in conducting technical training on cutting-edge technologies. We understand the challenges companies have when searching for quality, effective training which reduces the students’ time away from work and provides cost-effective alternatives. MindShare offers many fl exible solutions to meet those needs. Our courses are taught by highly-skilled, enthusiastic, knowledgeable and experienced instructors. We bring life to knowledge through a wide variety of learning methods and delivery options. training that fi ts your needs MindShare recognizes and addresses your company’s technical training issues with: • Scalable cost training • Customizable training options • Reducing time away from work • Just-in-time training • Overview and advanced topic courses • Training delivered effectively globally • Training in a classroom, at your cubicle or home offi ce • Concurrently delivered multiple-site training MindShare training courses expand your technical skillset 2 PCI Express 2.0 ® 2 Serial Attached SCSI (SAS) 2 Intel Core 2 Processor Architecture 2 DDR2/DDR3 DRAM Technology 2 AMD Opteron Processor Architecture 2 PC BIOS Firmware 2 Intel 64 and IA-32 Software Architecture 2 High-Speed Design 2 Intel PC and Chipset Architecture 2 Windows Internals and Drivers 2 PC Virtualization 2 Linux Fundamentals 2 USB 2.0 ... and many more. 2 Wireless USB All courses can be customized to meet your 2 Serial ATA (SATA) group’s needs. Detailed course outlines can be found at www.mindshare.com bringing life to knowledge. real-world tech training put into practice worldwide *PCI Express ® is a registered trademark of the PCISIG MindShare Learning Options MindShare MindShare MindShare MindShare Classroom Virtual Classroom eLearning Press Intro eLearning In-House Training Virtual In-House Training Books Modules Comprehensive Public Training Virtual Public Training eLearning Modules eBooks Classroom Training Virtual Classroom Training eLearning Module Training MindShare Press Invite MindShare to train The majority of our courses MindShare is also an eLearning Purchase our books and you in-house, or sign-up to live over the web in an inter- company. Our growing list of eBooks or publish your attend one of our many public active environment with WebEx interactive eLearning modules own content through us. classes held throughout the and a phone bridge. We deliver include: MindShare has authored year and around the world. training cost-effectively across • Intro to Virtualization over 25 books and the list No more boring classes, the multiple sites and time zones. Technology is growing. Let us help ‘MindShare Experience‘ is Imagine being trained in your • Intro to IO Virtualization make your book project sure to keep you engaged. cubicle or home offi ce and • Intro to PCI Express 2.0 a successful one. avoiding the hassle of travel. Updates Contact us to attend one of • PCI Express 2.0 our public virtual classes. • USB 2.0 • AMD Opteron Processor Architecture • Virtualization Technology ...and more Engage MindShare Have knowledge that you want to bring to life? MindShare will work with you to “Bring Your Knowledge to Life.” Engage us to transform your knowledge and design courses that can be delivered in classroom or virtual class- room settings, create online eLearning modules, or publish a book that you author. We are proud to be the preferred training provider at an extensive list of clients that include: ADAPTEC • AMD • AGILENT TECHNOLOGIES • APPLE • BROADCOM • CADENCE • CRAY • CISCO • DELL • FREESCALE GENERAL DYNAMICS • HP • IBM • KODAK • LSI LOGIC • MOTOROLA • MICROSOFT • NASA • NATIONAL SEMICONDUCTOR NETAPP • NOKIA • NVIDIA • PLX TECHNOLOGY • QLOGIC • SIEMENS • SUN MICROSYSTEMS SYNOPSYS • TI • UNISYS 4285 SLASH PINE DRIVE COLORADO SPRINGS, CO 80908 USA M 1.602.617.1123 O 1.800.633.1440 [email protected] www.mindshare.com PCI System Architecture Fourth Edition MINDSHARE, INC. TOM SHANLEY AND DON ANDERSON ▲ ▼▼ ADDISON-WESLEY DEVELOPER’S PRESS Reading, Massachusetts • Harlow, England • Menlo Park, California New York • Don Mills, Ontario • Sydney Bonn • Tokyo • Amsterdam • Mexico City • Seoul San Juan • Madrid • Singapore • Paris • Taipei • Milan Many of the designations used by manufacturers and sellers to distinguish their prod- ucts are claimed as trademarks. Where those designators appear in this book, and Addi- son-Wesley was aware of the trademark claim, the designations have been printed in initial capital letters or all capital letters. The authors and publishers have taken care in preparation of this book, but make no expressed or implied warranty of any kind and assume no responsibility for errors or omissions. No liability is assumed for incidental or consequential damages in connec- tion with or arising out of the use of the information or programs contained herein. Library of Congress Cataloging-in-Publication Data ISBN: 0-201-30974-2 Copyright ©1999 by MindShare, Inc. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopy- ing, recording, or otherwise, without the prior written permission of the publisher. Printed in the United States of America. Published simultaneously in Canada. Sponsoring Editor: Project Manager: Cover Design: Set in 10 point Palatino by MindShare, Inc. 1 2 3 4 5 6 7 8 9-MA-999897 First Printing, May 1999 Addison-Wesley books available for bulk purchases by corporations, institutions, and other organizations. For more information please contact the Corporate, Government, and Special Sales Department at (800) 238-9682. Find A-W Developers Press on the World-Wide Web at: http://www/aw.com/devpress/ Contents About This Book The MindShare Architecture Series ....................................................................................... 1 Organization of This Book.......................................................................................................2 Designation of Specification Changes................................................................................... 3 Cautionary Note ......................................................................................................................... 3 Who this Book is For ................................................................................................................. 4 Prerequisite Knowledge ........................................................................................................... 4 Object Size Designations ......................................................................................................... 4 Documentation Conventions................................................................................................... 5 Hex Notation ........................................................................................................................ 5 Binary Notation.................................................................................................................... 5 Decimal Notation ................................................................................................................. 5 Signal Name Representation.............................................................................................. 5 Identification of Bit Fields (logical groups of bits or signals)........................................ 6 We Want Your Feedback...........................................................................................................6 Chapter 1: Intro To PCI PCI Bus History .......................................................................................................................... 7 PCI Bus Features......................................................................................................................... 8 PCI Device vs. Function.......................................................................................................... 12 Specifications Book is Based On........................................................................................... 13 Obtaining PCI Bus Specification(s)...................................................................................... 13 Chapter 2: Intro to PCI Bus Operation Burst Transfer ........................................................................................................................... 15 Initiator, Target and Agents ................................................................................................... 17 Single- Vs. Multi-Function PCI Devices ............................................................................. 17 PCI Bus Clock ........................................................................................................................... 17 Address Phase........................................................................................................................... 18 Claiming the Transaction ....................................................................................................... 19 Data Phase(s)............................................................................................................................. 19 Transaction Duration .............................................................................................................. 20 Transaction Completion and Return of Bus to Idle State ...............................................
Recommended publications
  • Adaptec SAS RAID.Indd
    Adaptec SAS RAID Confi guration and the Windows OS Installation Instructions Adaptec SAS RAID Confi guration and the Windows OS Installation Instructions After all the hardware has been installed, you must fi rst confi gure the SAS RAID before you install the Windows Operating System and other software drivers. 1 The Adaptec SAS RAID Controller Driver If you do not wish to confi gure Adaptec SAS RAID functions, please go directly to Section 2 for the Windows OS Installation instructions. Introduction to SAS (Serial Attached SCSI) In addition to SATA (Serial ATA) which is supported by the Intel ESB2 South Bridge, your motherboard has an Adaptec SAS (Serial Attached SCSI) 9410W Controller built in. SAS supports serial link data transfer rates up to 3Gbps. With the dynamic SAS infrastructure built in, your motherboard supports both SATA and SAS, providing the user with unparalleled data storage expansion and inter-con- nectivity capability. Using the Adaptec RAID Confi guration Utility The onboard SAS Controller is enabled by default. To disable it, please set the SAS Enable Jumper to Pins 2-3 (See the Jumper Section in Chapter 2 of your motherboard manual for details.) When the system is detecting the SAS Controller BIOS, make sure that the 16-digit Adapter WWN address displays. If this number is not shown, you will not be able to use the controller. *Once the WWN address appears, press the <Ctrl> and <A> keys simultaneously when prompted to access the Adaptec SAS RAID BIOS. (Note: Use the arrow keys to highlight an item and then press <Enter> to select an option.
    [Show full text]
  • Adaptec Storage Manager User’S Guide for Direct Attached Storage ● 2
    Adaptec Storage Manager User’s Guide For Direct Attached Storage ● 2 Copyright ©2009 Adaptec, Inc. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording or otherwise, without the prior written consent of Adaptec, Inc., 691 South Milpitas Blvd., Milpitas, CA 95035. Trademarks Adaptec, Adaptec Storage Manager, MaxIQ, and the Adaptec logo are trademarks of Adaptec, Inc., which may be registered in some jurisdictions. Microsoft and Windows are trademarks of Microsoft Corporation in the US and other countries, used under license. Red Hat is a trademark of Red Hat, Inc. in the US and other countries, used under license. SCO and OpenServer are trademarks of The SCO Group, Inc. in the US and other countries, used under license. UnixWare is a registered trademark of The Open Group in the US and other countries, used under license. VMWare is a registered trademark of VMWare, Inc. in the US and other countries, used under license. All other trademarks are the property of their respective owners. Changes The material in this document is for information only and is subject to change without notice. While reasonable efforts have been made in the preparation of this document to assure its accuracy, Adaptec, Inc. assumes no liability resulting from errors or omissions in this document, or from the use of the information contained herein. Adaptec reserves the right to make changes in the product design without reservation and without notification to its users. Disclaimer IF THIS PRODUCT DIRECTS YOU TO COPY MATERIALS, YOU MUST HAVE PERMISSION FROM THE COPYRIGHT OWNER OF THE MATERIALS TO AVOID VIOLATING THE LAW WHICH COULD RESULT IN DAMAGES OR OTHER REMEDIES.
    [Show full text]
  • PPC7A10 at Our Website: Click HERE Powerx Product Manual PPC7A
    Full-service, independent repair center -~ ARTISAN® with experienced engineers and technicians on staff. TECHNOLOGY GROUP ~I We buy your excess, underutilized, and idle equipment along with credit for buybacks and trade-ins. Custom engineering Your definitive source so your equipment works exactly as you specify. for quality pre-owned • Critical and expedited services • Leasing / Rentals/ Demos equipment. • In stock/ Ready-to-ship • !TAR-certified secure asset solutions Expert team I Trust guarantee I 100% satisfaction Artisan Technology Group (217) 352-9330 | [email protected] | artisantg.com All trademarks, brand names, and brands appearing herein are the property o f their respective owners. Find the Abaco Systems / Radstone PPC7A10 at our website: Click HERE PowerX Product Manual PPC7A Appendix C - PPC7A This appendix contains hardware information for PPC7A boards. The information contained in this document must be used in conjunction with PowerX Quick Start, PowerX User Guides and/or the PowerX product Manual. Link Settings...................................................................................................................................... C-3 Default Link Settings............................................................................................................................... C-3 RTC Standby Supply Voltage Link (E1)................................................................................................. C-4 FLASH Write Enable Links (E3 and E9)...............................................................................................
    [Show full text]
  • PCI-X & PCI Core User's Guide
    PCI-X & PCI Core User's Guide Version 7.1.0 27-Feb-2007 © PLD Applications, 1996-2007 PLD Applications Web: http://www.plda.com Europarc Pichaury A2 Email: [email protected] 1330, rue Guillibert USA : 1 866 513 0362 (toll free) 13856 Aix-en-Provence Intl : + 33 442 393 600 CEDEX 3 - France Fax : + 33 442 394 902 Associate Member PCI-X & PCI Core User's Guide Features General ° 32-bit/64-bit PCI-X & PCI master/target interface ° Supports bus speed up to 133 MHz ° Multi-function core can implement up to 2 independent functions ° Full support for 64-bit addressing ° PCI-X Specification 2.0a mode 1 compliant ° PCI Specification 3.0 compliant ° Supports PCI power management ° Built-in support for in-site programming through JTAG interface ° Supports Message Signalled Interrupts Customization ° Easy customization with the PCI Wizard's user interface and on-line help. ° PCI Wizard has built-in support for VHDL and Verilog. ° All features can be parameterized, removing all unused logic ° Full plug-and-play support Configuration ° Supports all required and optional type 0 configuration registers ° Up to 6 BARs plus expansion ROM can be implemented ° Up to 32 user defined configuration registers Data transfer ° Supports up to 4KB burst transfers with zero wait-state insertion. ° Supports all memory and I/O commands ° Supports interrupt acknowledge cycles in target mode ° Can insert wait-states and generate all types of terminations ° Up to two split channels and 32 outstanding split transactions DMA ° Up to 4 independent DMA channels with rotating priority ° Flexible backend interface can directly control FIFO devices.
    [Show full text]
  • PCI20EX PCI Express (Pcie)
    PCI20EX PCI Express (PCIe) Bus ARCNET® Network Interface Modules INSTALLATION GUIDE INTRODUCTION The PCI20EX series of ARCNET network interface modules (NIMs) links PCI Express (PCIe) bus compatible computers with the ARCNET local area network (LAN). Since most PC motherboards have migrated from the legacy PCI and PCI-X Bus, a PCI Express style NIM is required. The PCI20EX series is compliant to the PCI Express Card Electromechanical Specification Revision 2.0 and both standard height and low-profile brackets are provided. The PCI Express interface allows for jumperless configuration and Plug and Play operation. The module operates with either an NDIS driver or a null stack driver in a Windows® environment. The PCI20EX incorporates the COM20022 ARCNET controller chip with enhanced features over the earlier generation ARCNET chips. New features include command chaining, sequential access to internal RAM, duplicate node ID detection and variable data rates up to 10 Mbps. Bus contention problems are minimized since the module’s interrupt and I/O base address are assigned through Plug and Play. The PCI20EX exploits the new features of the COM20022 which includes 10 Mbps communications utilizing the various EIA-485 transceiver options. Each PCI20EX module has two LEDs on the board for monitoring network operation and bus access to the module. It is equipped with an 8 position, general purpose DIP switch typically used to assign the ARCNET node address. Ultimately, the node address is configured via software so the DIP switch can also indicate user-defined functions such as data rate, cable interface, or master/slave status of the system.
    [Show full text]
  • A Not So Short Introduction to Pcie
    Practical introduction to PCI Express with FPGAs Michal HUSEJKO, John EVANS [email protected] IT-PES-ES v 1.0 Agenda • What is PCIe ? o System Level View o PCIe data transfer protocol • PCIe system architecture • PCIe with FPGAs o Hard IP with Altera/Xilinx FPGAs o Soft IP (PLDA) o External PCIe PHY (Gennum) v 1.0 System Level View • Interconnection • Top-down tree hierarchy • PCI/PCIe configuration space • Protocol v 1.0 Interconnection • Serial interconnection • Dual uni-directional • Lane, Link, Port • Scalable o Gen1 2.5/ Gen2 5.0/ Gen3 8.0 GT/s o Number of lanes in FPGAs: x1, x2, x4, x8 • Gen1/2 8b10b • Gen3 128b/130b v 1.0 Image taken from “Introduction to PCI Express” Tree hierarchy • Top-down tree hierarchy with single host • 3 types of devices: Root Complex, Endpoint, Switch • Point-to-point connection between devices without sideband signalling • 2 types of ports: downstream/upstream • Configuration space Image taken from “Introduction to PCI Express” v 1.0 PCIe Configuration space • Similar to PCI conf space – binary compatible for first 256 bytes • Defines device(system) capabilities • Clearly identifies device in the system o Device ID o Vendor ID o Function ID o All above • and defines memory space allocated to device. v 1.0 PCIe transfer protocol • Transaction categories • Protocol • Implementation of the protocol v 1.0 Transaction categories • Configuration – move downstream • Memory – address based routing • IO – address based routing • Message – ID based routing v 1.0 Transaction Types v 1.0 Table taken from “PCI
    [Show full text]
  • Datasheet for Onenand Power Ramp and Stabilization Times and for Onenand Boot Copy Times
    TMS320DM365 www.ti.com SPRS457E–MARCH 2009–REVISED JUNE 2011 TMS320DM365 Digital Media System-on-Chip (DMSoC) Check for Samples: TMS320DM365 1 TMS320DM365 Digital Media System-on-Chip (DMSoC) 1.1 Features 12 • Highlights – Support for 32-Bit and 16-Bit – High-Performance Digital Media (Thumb® Mode) Instruction Sets System-on-Chip (DMSoC) – DSP Instruction Extensions and Single Cycle – Up to 300-MHz ARM926EJ-S Clock Rate MAC – Two Video Image Co-processors – ARM® Jazelle® Technology (HDVICP, MJCP) Engines – Embedded ICE-RT Logic for Real-Time – Supports a Range of Encode, Decode, and Debug Video Quality Operations • ARM9 Memory Architecture – Video Processing Subsystem – 16K-Byte Instruction Cache • HW Face Detect Engine – 8K-Byte Data Cache • Resize Engine from 1/16x to 8x – 32K-Byte RAM • 16-Bit Parallel AFE (Analog Front-End) – 16K-Byte ROM Interface Up to 120 MHz – Little Endian • 4:2:2 (8-/16-bit) Interface • Two Video Image Co-processors • 8-/16-bit YCC and Up to 24-Bit RGB888 (HDVICP, MJCP) Engines Digital Output – Support a Range of Encode and Decode • 3 DACs for HD Analog Video Output Operations, up to D1 on 216-MHz device and • Hardware On-Screen Display (OSD) up to 720p on the 270- and 300-MHz parts – Capable of 720p 30fps H.264 video – H.264, MPEG4, MPEG2, MJPEG, JPEG, processing WMV9/VC1 Note: 216-MHz is only capable of D1 • Video Processing Subsystem processing – Front End Provides: – Peripherals include EMAC, USB 2.0 OTG, • HW Face Detect Engine DDR2/NAND, 5 SPIs, 2 UARTs, 2 • Hardware IPIPE for Real-Time Image MMC/SD/SDIO,
    [Show full text]
  • Hypertransport?
    HT.book Page 99 Monday, January 13, 2003 12:12 PM 5 Flow Control The Previous Chapter The previous chapter described the use of HyperTransport control and data packets to construct HyperTransport link transactions. Control packet types include Information, Request, and Response variants; data packets contain a payload of 0-64 valid bytes. The transmission, structure, and use of each packet type is presented. This Chapter This chapter describes HyperTransport flow control, used to throttle the move- ment of packets across each link interface. On a high-performance connection such as HyperTransport, efficient management of transaction flow is nearly as important as the raw bandwidth made possible by clock speed and data bus width. Topics covered here include background information on bus flow control and the initialization and use of the HyperTransport virtual channel flow con- trol buffer mechanism defined for each transmitter-receiver pair. The Next Chapter The next chapter describes the rules governing acceptance, forwarding, and rejection of packets seen by HyperTransport devices. Several factors come into play in routing, including the packet type, the direction it is moving, and the device type which sees it. A related topic also covered in this chapter is the fair- ness algorithm used by a tunnel device as it inserts its own packets into the traf- fic it forwards upstream on behalf of devices below it. The HyperTransport specification provides a fairness algorithm and a hardware method for tunnel management packet insertion. The Problem On any bus where an agent initiates the exchange of information (commands, data, status, etc.) with a target, a number of things can cause a delay (or even end) the normal completion of the intended transfer.
    [Show full text]
  • Volume 12: PCIE Configuration Registers (Haswell)
    © 2013 Intel Corporation Intel Open Source Graphics Programmer’s Reference Manual (PRM) for the 2013 Intel® Core™ Processor Family, including Intel HD Graphics, Intel Iris™ Graphics and Intel Iris Pro Graphics Volume 12: PCIE Configuration Registers (Haswell) 12/18/2013 1 Copyright INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. A "Mission Critical Application" is any application in which failure of the Intel Product could result, directly or indirectly, in personal injury or death. SHOULD YOU PURCHASE OR USE INTEL'S PRODUCTS FOR ANY SUCH MISSION CRITICAL APPLICATION, YOU SHALL INDEMNIFY AND HOLD INTEL AND ITS SUBSIDIARIES, SUBCONTRACTORS AND AFFILIATES, AND THE DIRECTORS, OFFICERS, AND EMPLOYEES OF EACH, HARMLESS AGAINST ALL CLAIMS COSTS, DAMAGES, AND EXPENSES AND REASONABLE ATTORNEYS' FEES ARISING OUT OF, DIRECTLY OR INDIRECTLY, ANY CLAIM OF PRODUCT LIABILITY, PERSONAL INJURY, OR DEATH ARISING IN ANY WAY OUT OF SUCH MISSION CRITICAL APPLICATION, WHETHER OR NOT INTEL OR ITS SUBCONTRACTOR WAS NEGLIGENT IN THE DESIGN, MANUFACTURE, OR WARNING OF THE INTEL PRODUCT OR ANY OF ITS PARTS. Intel may make changes to specifications and product descriptions at any time, without notice.
    [Show full text]
  • The Benefits of Serial Attached SCSI (SAS) for External Subsystems
    SERVER STORAGE SOLUTIONS WHITE PAPER The Benefits of Serial Attached SCSI (SAS) for External Subsystems Serial Attached SCSI (SAS), the follow-on to parallel The first SAS prototypes were announced in 2003 and SCSI, is designed for high-performance enterprise were a major step to achieving mass market requirements and offers both the benefits of backward availability. Those prototypes allowed development of compatibility with SCSI and interoperability with the first generation of technologies and products that Serial ATA (SATA), bringing enterprises a flexibility bring the benefits of SAS into the enterprise. These and cost savings previously not possible. SAS provides products have been developed and tested, and enable a significant benefits to external storage subsystems and wide variety of integrated solutions. offers users “one-stop-shopping” to satisfy their Interoperability testing was a key component of SAS, requirements for the following three main data types; because it increases the architecture’s flexibility by Throughput Data Transaction Data Reference Data supporting both SAS and SATA disk drives and components. Interoperability allows one vendor’s SAS • High MB/s and large • Maximum IOPs for OLTP, • Fixed content, archival data data-intensive files calculation intensive files for secondary/nearline products to be compatible with another’s, and it also • Large block, random • Small block, random storage ensures products developed today will work with all read/writes read/writes • Large block, sequential existing and next-generation
    [Show full text]
  • Wishbone Bus Architecture – a Survey and Comparison
    International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.2, April 2012 WISHBONE BUS ARCHITECTURE – A SURVEY AND COMPARISON Mohandeep Sharma 1 and Dilip Kumar 2 1Department of VLSI Design, Center for Development of Advanced Computing, Mohali, India [email protected] 2ACS - Division, Center for Development of Advanced Computing, Mohali, India [email protected] ABSTRACT The performance of an on-chip interconnection architecture used for communication between IP cores depends on the efficiency of its bus architecture. Any bus architecture having advantages of faster bus clock speed, extra data transfer cycle, improved bus width and throughput is highly desirable for a low cost, reduced time-to-market and efficient System-on-Chip (SoC). This paper presents a survey of WISHBONE bus architecture and its comparison with three other on-chip bus architectures viz. Advanced Microcontroller Bus Architecture (AMBA) by ARM, CoreConnect by IBM and Avalon by Altera. The WISHBONE Bus Architecture by Silicore Corporation appears to be gaining an upper edge over the other three bus architecture types because of its special performance parameters like the use of flexible arbitration scheme and additional data transfer cycle (Read-Modify-Write cycle). Moreover, its IP Cores are available free for use requiring neither any registration nor any agreement or license. KEYWORDS SoC buses, WISHBONE Bus, WISHBONE Interface 1. INTRODUCTION The introduction and advancement of multimillion-gate chips technology with new levels of integration in the form of the system-on-chip (SoC) design has brought a revolution in the modern electronics industry. With the evolution of shrinking process technologies and increasing design sizes [1], manufacturers are integrating increasing numbers of components on a chip.
    [Show full text]
  • Comparison of High Performance Northbridge Architectures in Multiprocessor Servers
    Comparison of High Performance Northbridge Architectures in Multiprocessor Servers Michael Koontz MS CpE Scholarly Paper Advisor: Dr. Jens-Peter Kaps Co-Advisor: Dr. Daniel Tabak - 1 - Table of Contents 1. Introduction ...............................................................................................................3 2. The x86-64 Instruction Set Architecture (ISA) ...................................................... 3 3. Memory Coherency ...................................................................................................4 4. The MOESI and MESI Cache Coherency Models.................................................8 5. Scalable Coherent Interface (SCI) and HyperTransport ....................................14 6. Fully-Buffered DIMMS ..........................................................................................16 7. The AMD Opteron Northbridge ............................................................................19 8. The Intel Blackford Northbridge Architecture .................................................... 27 9. Performance and Power Consumption .................................................................32 10. Additional Considerations ..................................................................................34 11. Conclusion ............................................................................................................ 36 - 2 - 1. Introduction With the continuing growth of today’s multi-media, Internet based culture, businesses are becoming more dependent
    [Show full text]