Anr018 Gnss I2c Communication

Total Page:16

File Type:pdf, Size:1020Kb

Anr018 Gnss I2c Communication ANR018 GNSS I2C COMMUNICATION VERSION 1.2 JUNE 2, 2021 Revision history Manual Notes Date version 1.0 • Initial version June 2020 1.1 • Figure 7 and 8 updated July 2020 1.2 • Updated Chapter 3 June 2021 ANR018 GNSS I2C Communication version 1.2 © June 2021 www.we-online.com/wireless-connectivity 1 Abbreviations and abstract Abbreviation Description ASCII American Standard Code for Information Interchange CTS Clear to send I2C Inter-IC bus GND Ground GNSS Global Navigation Satellite System HIGH Digital (logic) high level IC Integrated Circuit IDC Insulation Displacement Contact LOW Digital (logic) low level µC Microcontroller NMEA National Marine Electronics Association OSP One Socket Protocol PC Personal Computer RTS Request to send SCL Serial Clock SDA Serial Data USB Universal Serial Bus ANR018 GNSS I2C Communication version 1.2 © June 2021 www.we-online.com/wireless-connectivity 2 Contents 1 Introduction5 2 I2C Digital interface6 2.1 General characteristics..............................6 2.2 SDA and SCL logic levels............................6 2.3 Communication phase..............................6 2.3.1 Idle state.................................6 2.3.2 START(S) and STOP(P) condition...................7 2.3.3 Data validity...............................7 2.3.4 Data format...............................8 2.3.5 Acknowledge and No-Acknowledge..................8 2.3.6 Addressing the GNSS module.....................8 2.3.7 GNSS communication protocol....................9 2.4 I2C timing parameters..............................9 3 Hardware Setup 10 3.1 Hardware Setup - 1.8V.............................. 10 3.2 Evaluation Board Modification - 1.8V...................... 11 3.3 Hardware Setup - Erinome-I........................... 13 3.4 Evaluation Board Modification - Erinome-I................... 14 4 Application Example 16 4.1 Total Phase Aardvark host adapter....................... 16 4.2 Generic Microcontroller............................. 23 5 Troubleshooting 25 6 Important notes 26 6.1 General customer responsibility......................... 26 6.2 Customer responsibility related to specific, in particular safety-relevant ap- plications..................................... 26 6.3 Best care and attention............................. 26 6.4 Customer support for product specifications.................. 26 6.5 Product improvements.............................. 27 6.6 Product life cycle................................. 27 6.7 Property rights.................................. 27 6.8 General terms and conditions.......................... 27 7 Legal notice 28 7.1 Exclusion of liability................................ 28 7.2 Suitability in customer applications....................... 28 7.3 Trademarks.................................... 28 7.4 Usage restriction................................. 28 8 License terms 30 8.1 Limited license.................................. 30 8.2 Usage and obligations.............................. 30 8.3 Ownership..................................... 31 8.4 Firmware update(s)................................ 31 8.5 Disclaimer of warranty.............................. 31 ANR018 GNSS I2C Communication version 1.2 © June 2021 www.we-online.com/wireless-connectivity 3 8.6 Limitation of liability................................ 31 8.7 Applicable law and jurisdiction.......................... 32 8.8 Severability clause................................ 32 8.9 Miscellaneous................................... 32 ANR018 GNSS I2C Communication version 1.2 © June 2021 www.we-online.com/wireless-connectivity 4 1 Introduction This application note aims to support the use of the I2C interface on Elara and Erinome GNSS modules. I2C interface is available in these modules as an alternative to UART. The GNSS module functions as Multi-Master. The first part of the document describes the basics of I2C communication. This technical background information helps to understand the rest of the document. It includes under- standing the different roles and phases in the communication, addressing of the bus sub- scriber and data structure. The recommended I2C communication hardware setup is described in detail in Chapter ??. The same setup can be used for Elara-I, Elara-II, and Erinome-II modules, operating with 1.8 V power supply. A slightly different setup is required for Erinome-I, operating with 3.3 V power supply. After some simple modifications, the evaluation board can be used to test I2C communica- tion with the GNSS module. The modifications are also explained in detail in chapter ??. Chapter 4 presents a specific application example, where the GNSS evaluation board com- municates via I2C with the Aardvark I2C/SPI host adapter from Total Phase 1. This chapter guides the user through the software and hardware configuration to successfully establish I2C communication with the GNSS module. The application note is concluded by a trou- bleshooting section which helps the user to debug the process. Module Article number Power supply Input logic level Output logic level Elara-I 2613011037000 1.8V 3.3V 1.8V Elara-II 2613021137000 1.8V 3.3V 1.8V Erinome-I 2614011037000 3.3V 3.3V 1.8V Erinome-II 2614021137000 1.8V 3.3V 1.8V Table 1: GNSS module power supply and logic levels 1 https://www.totalphase.com/products/aardvark-i2cspi/ . ANR018 GNSS I2C Communication version 1.2 © June 2021 www.we-online.com/wireless-connectivity 5 2 I2C Digital interface The GNSS module supports standard I2C (Inter-IC) bus interface as an alternative to the recommended UART interface. Further information of the I2C interface can be found at https://www.nxp.com/docs/en/user-guide/UM10204.pdf .I2C is a serial 8-bit protocol with two-wire interface, which supports communication between different ICs. For example be- tween the µC and other peripheral devices such as a GNSS module or sensors. 2.1 General characteristics A serial data line (SDA) and a serial clock line (SCL) are required for the communication between the devices connected via I2C bus. Both SDA and SCL lines are bidirectional. The output stages of devices connected to the bus must have an open-drain or open-collector. Hence, the SDA and SCL lines shall be connected to a positive supply voltage using pull-up resistors. In the I2C protocol, the communication is realized through master-slave principle. The mas- ter device generates the clock pulses, a start command and a stop command for the data transfer. Each connected device on the bus is addressable via a unique address. Master and slave can act as a transmitter or a receiver depending upon whether the data needs to be transmitted or received. The GNSS module supports the role of I2C multi-master which means it will act as a I2C master and send data to a specific slave address whenever it has data available and the bus is idle. In case the GNSS module has no data to send, it will switch into the I2C slave role to be able to receive data from another master that addresses the GNSS module via the bus. 2.2 SDA and SCL logic levels Logic level is the positive supply voltage to which SDA and SCL lines are to be pulled up (through internal or external pull-up resistors). The GNSS modules support specified logic levels (product specific, e.g. 1.8V) which must be either used by every device on the I2C bus or a logic level conversion must be implement- ed in-between the GNSS module and the other bus participants. This conversion IC must be selected in a manner that it supports the requirements of I2C set by the GNSS module, i.e. open-drain / open-collector and at least 400kHz clock speed. 2.3 Communication phase 2.3.1 Idle state During the idle state, the bus is free and both SDA and SCL lines are in logic high ’1’ state. No master has requested the bus by sending START(S). ANR018 GNSS I2C Communication version 1.2 © June 2021 www.we-online.com/wireless-connectivity 6 2.3.2 START(S) and STOP(P) condition Data transfer on the bus starts with a START command, which is generated by the active master. A start condition is defined as a high-to-low transition on the SDA line while the SCL line is held high. The bus is considered busy after the start condition, so no other master may access it. Slaves are not allowed to perform any bus activity unless addressed by a read access from a master. START STOP Condition Condition SDA SCL 1...7 8 9 1...8 9 1...8 9 7-bit Read/ ACK Data ACK Data NACK Address Write Figure 1: Data transfer from GNSS to slave Data transfer on the bus is terminated with a STOP command, which is also generated by the active master. A low-to-high transition on the SDA line, while the SCL line being high is defined as a STOP condition. After the stop condition, the bus is again considered free and is in idle state. Figure2 shows the I2C bus START and STOP conditions. 2.3.3 Data validity After the START condition, one data bit is transmitted with each clock pulse. The transmitted data is only valid when the SDA line data is stable (HIGH or LOW) during the high period of the clock pulse. HIGH or LOW state of the data line can only change when the clock pulse is in low state. ANR018 GNSS I2C Communication version 1.2 © June 2021 www.we-online.com/wireless-connectivity 7 START Valid Valid change STOP Condition data of data Condition SDA SCL Figure 2: Data validity, START and STOP condition 2.3.4 Data format Data transmission on the SDA line is always done in bytes, with each byte being 8-bits long. Data is transmitted with the most significant bit (MSB) first. If the slave cannot receive or transmit another complete byte of data, it can force the master into a wait state by holding SCL LOW. Data transfer continues when the slave is ready which is indicated by releasing the SCL pin. 2.3.5 Acknowledge and No-Acknowledge Each byte transmitted on the data line must be followed by an acknowledge bit (ACK). The receiver of the data (master or slave) generates an acknowledge signal to indicate that the data byte was received successfully and the receiver is ready to receive next data byte.
Recommended publications
  • 48-Bit, High Current, Logic Level Digital I/O Board for PCI
    User's Guide http://www.omega.com e-mail: [email protected] CIO-DIO48 CIO-DIO48H CIO-DIO96 CIO-DIO192 INTRODUCTION ................................... 1 Cable from DIO board QUICK START ..................................... 2 plugs into connector TM labeled IN Cable to second ERB or INSTALL THE INSTACAL SOFTWARE .................... 2 TM SSR board plugs into RUN INSTACAL ..................................... 2 connector labeled OUT OPERATION ....................................... 4 INSTALLATION ...................................... 4 BASE ADDRESS ...................................... 4 WAIT STATE JUMPER .................................. 6 INSTALLING THE CIO-DIO IN THE COMPUTER ............... 6 CABLING TO THE DIO CONNECTOR ....................... 7 SIGNAL CONNECTION - CIO-DIO48 ........................ 7 UNCONNECTED INPUTS FLOAT .......................... 8 CONNECTOR DIAGRAM ................................ 8 Cable from DIO board Cable to second ERB or ARCHITECTURE ................................... 9 plugs into connector SSR board plugs into labeled IN connector labeled OUT 82C55 CONTROL & DATA REGISTERS ...................... 9 82C55 DIGITAL I/O REGISTERS .......................... 11 SPECIFICATIONS ................................. 14 POWER CONSUMPTION ............................... 14 DIGITAL I/O ........................................ 15 ELECTRONICS AND INTERFACING ................. 16 PULL UP & PULL DOWN RESISTORS ...................... 16 UNCONNECTED INPUTS FLOAT ......................... 18 CIO-ERB-24 and SSR-RACK24 provide
    [Show full text]
  • Voltage Translation How to Manage Mixed-Voltage Designs with NXP Level Translators SECTION 1.0 Why Voltage Translation Matters
    Voltage translation How to manage mixed-voltage designs with NXP level translators SECTION 1.0 Why voltage translation matters Table of contents In recent years, voltage translation has become an important part of electronic design, especially in portable 1.0 Why voltage translation matters 3 applications. That’s because the latest data and application processors for mobile applications are typically 2.0 Unidirectional level translators 7 produced in advanced, low-power CMOS process technologies that use a supply voltage of 1.8 V or lower, but the peripherals they connect to, including memories, image sensors, relays, and RF transceivers, are more 2.1 Low-to-high level translation 7 likely to use older, lower-cost process technologies that operate at higher levels, at or above 3 or 5 V. Voltage- 2.2 High-to-low level translation 10 level translators (Figure 1-1) enable these different devices to work together, without producing damaging current flow or signal loss, so the system operates more efficiently and saves power. 3.0 Bidirectional level translators with direction pin 12 4.0 Bidirectional level translators with auto direction sensing 14 AC/DC Battery 4.1 Active devices for bidirectional translation with auto direction 14 charger 4.2 Passive devices for bidirectional translation with auto direction 19 5.0 Application-specific level translators 28 Memory Charger PMU SIM card 5.1 Translators for use with SIM cards 28 card 5.2 I2C muxes and switches that also perform bidirectional translation 30 Audio Cellular & RF, GPS, connectity Voltage-level translators WLAN, BT radio Blinker black light Voltage- Voltage- level Processor level translators translators Flash MCU, special I2C, MIPI, NFC/RFID function µC SPI UART Camera Voltage-level translators Display USB Keypad Sensor HDMI Figure 1-1.
    [Show full text]
  • Logic Families
    Logic Families PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Mon, 11 Aug 2014 22:42:35 UTC Contents Articles Logic family 1 Resistor–transistor logic 7 Diode–transistor logic 10 Emitter-coupled logic 11 Gunning transceiver logic 16 Transistor–transistor logic 16 PMOS logic 23 NMOS logic 24 CMOS 25 BiCMOS 33 Integrated injection logic 34 7400 series 35 List of 7400 series integrated circuits 41 4000 series 62 List of 4000 series integrated circuits 69 References Article Sources and Contributors 75 Image Sources, Licenses and Contributors 76 Article Licenses License 77 Logic family 1 Logic family In computer engineering, a logic family may refer to one of two related concepts. A logic family of monolithic digital integrated circuit devices is a group of electronic logic gates constructed using one of several different designs, usually with compatible logic levels and power supply characteristics within a family. Many logic families were produced as individual components, each containing one or a few related basic logical functions, which could be used as "building-blocks" to create systems or as so-called "glue" to interconnect more complex integrated circuits. A "logic family" may also refer to a set of techniques used to implement logic within VLSI integrated circuits such as central processors, memories, or other complex functions. Some such logic families use static techniques to minimize design complexity. Other such logic families, such as domino logic, use clocked dynamic techniques to minimize size, power consumption, and delay. Before the widespread use of integrated circuits, various solid-state and vacuum-tube logic systems were used but these were never as standardized and interoperable as the integrated-circuit devices.
    [Show full text]
  • Voltage-Level Translation Guide (Rev. H)
    Voltage Level Translation Guide Auto-Direction Sensing Direction Controlled Application-Specific ti.com/voltageleveltranslation 2014 Translation Guide Single-Supply Translators Table of Contents Single-Supply Translation Logic Introduction Single-Power Supply Translator Table of Contents In today’s complex and high-performance SN74AUP1Txx system environment, higher levels of Overview AUP technology is the industry’s lowest-power logic technology designed . The Key Features functional integration have led to lower Introduction . 2 SN74AUP1Txx is designed for logic-level translation applications with input switching • Low power consumption: ICC 0 .5 μA power consumption CMOS process levels that accept 1 .8-V LVCMOS signals, while operating from either a single 3 .3-V or • Schmitt-Trigger input: ΔVT = 210 mV, technologies operating at lower supply Single-Supply Translators 2 .5-V VCC supply . reject input noise voltage levels . The ability to mix, match Single-Supply Translation Logic . 3 The SN74AUP1Txx with configurable logic function (‘57,’58,’97,’98) can be easily • Nine configurable gate logic functions and support the simultaneous use of configured to perform a required gate function by connecting A, B, and C inputs to • ESD performance tested per JESD 22 different operating supply voltage levels Dual-Supply Translators V or ground (see datasheet) .Up to nine commonly used logic gate functions can be 2000-V human-body model on the same circuit board has led to the Five Classes of Voltage Translators . 4 CC performed . (A114-B, Class II) need for voltage-level translation . Bidirectional Voltage Translators . 5 1000-V charged-device model (C101) To remedy this problem of logic-threshold Single supply translators Auto-Direction Sensing Translators .
    [Show full text]
  • PCI System Architecture Fourth Edition
    world-class technical training Are your company’s technical training needs being addressed in the most effective manner? MindShare has over 25 years experience in conducting technical training on cutting-edge technologies. We understand the challenges companies have when searching for quality, effective training which reduces the students’ time away from work and provides cost-effective alternatives. MindShare offers many fl exible solutions to meet those needs. Our courses are taught by highly-skilled, enthusiastic, knowledgeable and experienced instructors. We bring life to knowledge through a wide variety of learning methods and delivery options. training that fi ts your needs MindShare recognizes and addresses your company’s technical training issues with: • Scalable cost training • Customizable training options • Reducing time away from work • Just-in-time training • Overview and advanced topic courses • Training delivered effectively globally • Training in a classroom, at your cubicle or home offi ce • Concurrently delivered multiple-site training MindShare training courses expand your technical skillset 2 PCI Express 2.0 ® 2 Serial Attached SCSI (SAS) 2 Intel Core 2 Processor Architecture 2 DDR2/DDR3 DRAM Technology 2 AMD Opteron Processor Architecture 2 PC BIOS Firmware 2 Intel 64 and IA-32 Software Architecture 2 High-Speed Design 2 Intel PC and Chipset Architecture 2 Windows Internals and Drivers 2 PC Virtualization 2 Linux Fundamentals 2 USB 2.0 ... and many more. 2 Wireless USB All courses can be customized to meet your 2 Serial
    [Show full text]
  • Multi-Valued Logic and Standard IEEE 1164
    Multi-valued logic and standard IEEE 1164 Jian-Jia Chen (Slides are based on Peter Marwedel) TU Dortmund, Informatik 12 2010 © Springer, 2015年 11 月 10 日 These slides use Microsoft clip arts. Microsoft copyright restrictions apply. technische universität fakultät für © JJ Chen and P.Marwedel, dortmund informatik Informatik 12, 2014 - 1 - Abstraction of electrical signals § Complete analog simulation at the circuit level would be time-consuming F We try to use digital values and DE simulation as long as possible F However, using just 2 digital values would be too restrictive (as we will see) technische universität fakultät für © JJ Chen and P.Marwedel, dortmund informatik Informatik 12, 2014 - 2 - How many logic values for modeling ? Two ('0' and '1') or more? If real circuits have to be described, some abstraction of the driving strength is required. F We introduce the distinction between: § the logic level (as an abstraction of the voltage) and § the strength (as an abstraction of the current drive capability) of a signal. The two are encoded in logic values. F CSA (connector, switch, attenuator) - theory [Hayes] technische universität fakultät für © JJ Chen and P.Marwedel, dortmund informatik Informatik 12, 2014 - 3 - 1 signal strength Logic values '0' and '1'. Both of the same strength. Encoding false and true, respectively. technische universität fakultät für © JJ Chen and P.Marwedel, dortmund informatik Informatik 12, 2014 - 4 - 2 signal strengths Many subcircuits can effectively disconnect themselves from the rest of the circuit (they provide “high impedance“ values to the rest of the circuit). Example: subcircuits with open collector or tri-state outputs.
    [Show full text]
  • MT-098: Low Voltage Logic Interfacing
    MT-098 TUTORIAL Low Voltage Logic Interfacing INTRODUCTION For nearly 20 years, the standard VDD for digital circuits was 5 V. This voltage level was used because bipolar transistor technology required 5 V to allow headroom for proper operation. However, in the late 1980s, Complimentary Metal Oxide Semiconductor (CMOS) became the standard for digital IC design. This process did not necessarily require the same voltage levels as TTL circuits, but the industry adopted the 5 V TTL standard logic threshold levels to maintain backward compatibility with older systems (Reference 1). The current revolution in supply voltage reduction has been driven by demand for faster and smaller products at lower costs. This push has caused silicon geometries to drop from 2 µm in the early 1980s to 0.90 nm and 45 nm that is used in many of today's latest FPGA, microprocessor, and DSP designs. As feature sizes have become increasingly smaller, the voltage for optimum device performance has also dropped below the 5 V level. This is illustrated in the current FPGAs, microprocessors, and DSPs, where the optimum core operating voltage can be as low as 1 V or less. The strong interest in lower voltage DSPs is clearly visible in the shifting sales percentages for 5 V and 3.3 V parts. Sales growth for 3.3 V DSPs has increased at more than twice the rate of the rest of the DSP market (30% for all DSPs versus more than 70% for 3.3 V devices). This trend will continue as the high volume/high growth portable markets demand signal processors that contain all of the traits of the lower voltage DSPs.
    [Show full text]
  • Logic-Level Translation 3.3V 1.8V
    Logic-level translation 3.3V 1.8V Electronic design has changed considerably since the R INPUT days when TTL and 5V CMOS were the dominant OUTPUT standards for logic circuits. The increasing complexity of 4.7kΩ CSTRAY modern electronic systems has led to lower voltage logic, APPROX which in turn can cause incompatibility between input 20pF and output levels for the logic families within a system. It is not unusual, for example, that a digital section operating at 1.8V must communicate with an analog subsection operating at 3.3V. This article examines the basics of logic operation and considers, primarily for Figure 1. A resistor-diode topology is one alternative technique to serial-data systems, the available methods for translating translation in both directions on the same signal line. between different domains of logic voltage. select. Data in and data out are also known as master in, The need for logic-level translation slave out (MISO) and master out, slave in (MOSI). SPI can be clocked in excess of 20Mbps, and is driven by The growth of digital ICs that feature incompatible CMOS push-pull logic. As SPI is unidirectional, voltage rails, lower VDD rails, or dual rails for VCORE and translation in both directions on the same signal line is VI/O has made the translation of logic levels necessary. unnecessary. This makes level translation simpler, The use of mixed-signal ICs with lower supply voltages because you can employ simple techniques involving that have not kept pace with those of their digital counter- resistors and diodes (Figure 1) or discrete/digital parts also creates the need for logic-level translation.
    [Show full text]
  • Circuit Design with VHDL Volnei A
    46183Pedroninew 2004-10-11 14:06 Page 1 Circuit Design Circuit Circuit Design with VHDL Volnei A. Pedroni This textbook teaches VHDL using system examples com- bined with programmable logic and supported by laboratory exercises. While other textbooks concentrate only on lan- guage features, Circuit Design with VHDL offers a fully inte- grated presentation of VHDL and design concepts by including a large number of complete design examples, illustrative circuit diagrams, a review of fundamental design concepts, fully explained solutions, and simulation results. The text presents the information concisely yet completely, discussing in detail all indispensable features of the VHDL synthesis. The book is organized in a clear progression, with the first part covering the circuit level, treating foundations of VHDL and fundamental coding, while the second part cov- ers the system level (units that might be located in a library for code sharing, reuse, and partitioning), expanding upon the earlier chapters to discuss system coding. Part I, “Circuit Design,” examines in detail the back- ground and coding techniques of VHDL, including code structure, data types, operators and attributes, concurrent with Circuit Design and sequential statements and code, objects (signals, vari- ables, and constants), design of finite state machines, and examples of additional circuit designs. Part II, “System with Design,” builds on the material already presented, adding VHDL elements intended mainly for library allocation; it examines VHDL packages and components, functions and procedures, and additional examples of system design. Appendixes on pro- Volnei A. Pedroni grammable logic devices (PLDs/FPGAs) and synthesis tools follow Part II. The book’s highly original approach of teach- ing through extensive system examples, as well as its unique integration of VHDL and design, makes it suitable both for use by students in computer science and electrical engineering.
    [Show full text]
  • Logic Selection Guide
    Logic Selection Guide NC7SV19 Decoder/Demultiplexer combines high speed at low voltages in MicroPak™ and SC70 6 Lead SC70 79 mils .007 in2 2.0 mm 4.2 mm2 49 mils 1.25 mm 35 mils 83 mils 0.9 mm 2.1 mm FXLP34 FXL Series Translators for 1.0V-3.6V Logic Levels in MicroPak and SC70 MicroPak 57 mils .002 in2 1.45 mm 1.45 mm2 21 mils Optoelectronics 0.55 mm 39 mils 1 mm FXLP34 NC7NZ04 Triple-Bit Logic in MicroPak 8 and US8 8 Terminal MicroPak Interface & Logic 62 mils .003 in2 1.6 mm 2.56 mm2 21 mils 0.55 mm 62 mils 1.6 mm Analog Discrete FSAL200 Quad Analog SPDT Switches 16 Terminal MLP 118 mils .014 in2 3 mm 9 mm2 118 mils 39 mils 3 mm 1 mm 16 Lead QSOP 193 mils 4.90 mm .045 in2 29.35 mm2 53 mils 1.35 mm 63 mils 1.60 mm Across the board. Around the world.™ Logic Selection Guide Logic Migration and Low-Voltage Transition How to use this guide The data on this page (page 2) give an HC historic overview of Fairchild’s available Mature 5V CD4000 AS 74C logic families. The Quick Reference Attributes charts on page 3 may be a good first step if a particular type performance needs emphasis. The Family Specifications Comparison chart on page 4 lists general FACT VHC FAST ABT Advanced 5V performance by operating voltage. ALS Propagation Delay and Power Consumption are then further detailed in charts on page 5.
    [Show full text]
  • Design and Implementation of a High-Speed PCI-Express Bridge Mandus Börjesson Håkan Gerner
    LiU-ITN-TEK-A--19/012--SE Design and implementation of a high-speed PCI-Express bridge Mandus Börjesson Håkan Gerner 2019-06-05 Department of Science and Technology Institutionen för teknik och naturvetenskap Linköping University Linköpings universitet nedewS ,gnipökrroN 47 106-ES 47 ,gnipökrroN nedewS 106 47 gnipökrroN LiU-ITN-TEK-A--19/012--SE Design and implementation of a high-speed PCI-Express bridge Examensarbete utfört i Elektroteknik vid Tekniska högskolan vid Linköpings universitet Mandus Börjesson Håkan Gerner Handledare Qin-Zhong Ye Examinator Adriana Serban Norrköping 2019-06-05 Upphovsrätt Detta dokument hålls tillgängligt på Internet – eller dess framtida ersättare – under en längre tid från publiceringsdatum under förutsättning att inga extra- ordinära omständigheter uppstår. Tillgång till dokumentet innebär tillstånd för var och en att läsa, ladda ner, skriva ut enstaka kopior för enskilt bruk och att använda det oförändrat för ickekommersiell forskning och för undervisning. Överföring av upphovsrätten vid en senare tidpunkt kan inte upphäva detta tillstånd. All annan användning av dokumentet kräver upphovsmannens medgivande. För att garantera äktheten, säkerheten och tillgängligheten finns det lösningar av teknisk och administrativ art. Upphovsmannens ideella rätt innefattar rätt att bli nämnd som upphovsman i den omfattning som god sed kräver vid användning av dokumentet på ovan beskrivna sätt samt skydd mot att dokumentet ändras eller presenteras i sådan form eller i sådant sammanhang som är kränkande för upphovsmannens litterära eller konstnärliga anseende eller egenart. För ytterligare information om Linköping University Electronic Press se förlagets hemsida http://www.ep.liu.se/ Copyright The publishers will keep this document online on the Internet - or its possible replacement - for a considerable time from the date of publication barring exceptional circumstances.
    [Show full text]
  • Section 5 – Digital Circuitry
    EE201: Digital Circuits and Systems 5 Digital Circuitry page 1 of 31 EE201: Digital Circuits and Systems Section 5 – Digital Circuitry 5.1 Classes - Bipolar Junction Transistors(BJTs) o TTL, LTTL, STTL, LSTTL o ECL, I(ntegrated)I(njection)L, D(Diode)TL - Metal Oxide Semiconductor (MOS) o PMOS, NMOS, CMOS 5.2 Operational Parameters 5.2.1 Voltage & Current Vxy => Voltage x defined as either Input or Output => Voltage y defines either logic high or low Ixy => Current x defined as either Input or Output => Current y defines either logic high or low VIH => Min voltage at input which can be ‘read’ as a 1(high) VIL => Max voltage at input which can be ‘read’ as a 0(low) VOH => Min voltage at output which allows a 1(high) VOL => Max voltage at output which can be ‘read’ as a 0(low) IIH => Input current when input = 1 IIL => Input current when input = 0 IOH => Output current when output = 1 IOL => Output current when output = 0 EE201: Digital Circuits and Systems 5 Digital Circuitry page 2 of 31 5V Logic 1 VIH VIL Logic 0 0V 5.2.2 Fan-out o Max amount of inputs driven by output. Example Determine the Fan-out of an NAND only circuit given the following values: IOH = 400 uA, IIH = 60 uA, IOL = 16 mA, IIL = 1.6 mA During high condition => Each NAND gate provides 400 uA current at output Each NAND gate sources 60 uA current at input. EE201: Digital Circuits and Systems 5 Digital Circuitry page 3 of 31 Fan-outHIGH = IOH / IIH = 400 / 60 = 6 (Rounded down since cannot drive part of a gate!) During low condition => Each NAND gate provides 16 mA current at output Each NAND gate sources 1.6 mA current at input.
    [Show full text]