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2012 International Workshop on Information and Electronics Engineering (IWIEE) Logic Level Conversion Method in Serial Data System

Baosheng Yanga*, Hongmei Lua , Xiaoying Yangb

aLaboratory of Intelligent Information Processing, Suzhou University, Suzhou 234000, China

bInformation Engineering School, Suzhou University, Suzhou 234000, China

Abstract

As electronic design has changed considerably since TTL and 5V CMOS were the dominant standards for logic circuits. The increasing complexity of modern electronic systems has led to lower voltage logic, which in turn can cause incompatibility between input and output levels for the logic families within a system. This article examines the basics of logic operation and considers, primarily for serial-data systems, analyzes the current digital IC for logic- level translation; include unidirectional high- to low-Level conversion, input overvoltage tolerance, mixed high-low and low-high translation. Using a transmission-gate method realizes convert bi-level mode transceiver. Through the design of a speed-up scheme that actively pulls up rising edges, thereby minimizing the effect of capacitive loads, in order to solve the rate problem. Now the bidirectional and topology-independent features (push-pull or open-drain) of a single chip solve the universal voltage problem.

© 2011 Published by Elsevier Ltd.

Keywords: Electronic design; Intergrated circuit; Level conversion; Serial bus

1. Introduction

The growth of digital ICs that feature incompatible voltage rails, lower VDD rails, or dual rails for [1] VCORE and VI/O has made the translation of logic levels necessary . The use of mixed-signal ICs with lower supply voltages that have not kept pace with those of their digital counterparts also creates the need for Logic Level Conversion[2]. Now, logic design requires attention to these, because the device must be able to any input signal to make the right judgments (yes or no)[3,4]. It is necessary to ensure that different types and generations of interoperability between devices, and need to be able to support different levels, for example, between 3.3 V and 5 V conversion, or the lower voltage conversion between standards.

* Corresponding author. Tel./ fax: +86-557-287-1028. E-mail address: [email protected].

1877-7058 © 2011 Published by Elsevier Ltd. doi:10.1016/j.proeng.2012.01.169 15402 B.Baosheng S. Yang etYang al. et/ Procedia al. / Procedia Engineering Engineering 00 (2011) 29 (2012) 000–000 1539 – 1543

2. The demand for logic level translation

Translation methods vary according to the range of voltages encountered, the number of lines to be translated (e.g., a 4-line Serial Peripheral Interface (SPI™) versus a 32- data bus), and the speed of the digital signals[6,7,8]. Many logic ICs can translate from high to low levels (such as 5V to 3.3V logic), but fewer can translate from low to high (3.3V to 5V)[9]. Level Conversion can be accomplished with single discrete transistors or even with a resistor-diode combination, but the parasitic capacitance inherent in these methods can reduce the data-transfer rate. Although byte-wide and word-wide level translators are available, they are not optimal for the < 20Mbps serial buses discussed in this article (SPI, I²C, USB, etc.). Thus, translators that require large packages with high pin counts and an I/O-direction pin are not meant for small serial and peripheral interfaces. The Serial Peripheral Interface consists of the unidirectional control lines data in, data out, clock, and chip select[10,11]. Data in and data out are also known as master in, slave out (MISO) and master out, slave in (MOSI). SPI can be clocked in excess of 20Mbps, and is driven by CMOS push-pull logic[12,13,14]. As SPI is unidirectional, translation in both directions on the same signal line is unnecessary. This makes Level Conversion simpler, because you can employ simple techniques involving resistors and diodes (Figure 1) or discrete/digital transistors (Figure 2).

Fig. 1. A resistor-diode topology is one alternative technique to translation in both directions on the same signal line.

Fig. 2. Using discrete/digital transistors is another alternative to bidirectional translation. BaoshengB. S. Yang etet al.al. // ProcediaProcedia EngineeringEngineering 2900 (2012)(2011) 1539000–000 – 1543 15413

The I²C, SMBus, and 1-Wire, interfaces are all bidirectional, open-drain I/O topologies. I²C has three speed ranges: standard mode at ≤ 100kbps, fast mode at ≤ 400kbps, and high-speed mode at ≤ 3.4Mbps. Level Conversion for bidirectional buses is more difficult, because one must translate in both directions on the same data line. Simple topologies based on resistor-diode and single-stage-transistor translators with open collector or drain do not work because they are inherently unidirectional.

3. Unidirectional High-to-Low Level Conversion—Input Overvoltage Tolerance

To translate from higher to lower logic levels, IC manufacturers produce a range of devices that are said to tolerate overvoltage at their inputs. A logic device is defined as input-overvoltage protected if it can withstand (without damage) an input voltage higher than its supply voltage. Such input-protected devices simplify the task of translating from higher- to lower-VCC logic while increasing the signal-to- noise margin. Overvoltage-tolerant inputs, for example, allow a logic device to cope with logic levels of 1.8V and higher while powered from a 1.8V supply. Devices in the LVC , which are mostly input- overvoltage protected, work well in applications requiring high-to-low translations. The opposite situation of low-to-high translation is not as easy. It may not be feasible to generate higher voltage Logic Level thresholds (VIH) from lower voltage logic. When designing a circuit for which connectors, high fanout, or stray load capacitance produce a high capacitance load, you should remember that for all logic families, reducing the supply voltage also decreases the drive capability. An exception occurs between 3.3V CMOS or TTL (LV, LVT, ALVT, LVC, and ALVC) and 5V standard TTL (H, L, S, HS, LS, and ALS). In these logic families, the 3.3V and 5V logic activation points (VOL, VIL, VIH, and VOH) match each other.

4. Bidirectional Transceiver Methods

For the larger byte- and word-wide buses where WR and RD signals already exist, one method for transferring data across the voltage levels is a bus such as the 74CBTB3384. Such devices are typically optimized for operation between 3.3V and 5V. For smaller 1- and 2-wire buses, this approach raises two issues. Firstly, it requires a separate enable pin to control the direction of data flow, and this ties up valuable port pins. Secondly, it requires large ICs that take up valuable board space. All techniques have their pros and cons. Nonetheless, designers need a universal device that works across all translation levels, enables mixed low-to-high and high-to-low logic transitions, and includes unidirectional and/or bidirectional translation. A next-generation bidirectional level shifter (the MAX3370 in the MAX3370–MAX3393 family of ICs) fulfills those needs while overcoming some of the problems associated with alternative approaches. The MAX3370, which implements a transmission-gate method of Level Conversion (Figure 4), relies on external output drivers to sink current, whether they operate in a low-voltage or higher voltage logic domain. That capability enables the device to work with either open-drain or push-pull output stages. The relatively low on-resistance of a transmission gate (less than 135Ω), moreover, limits the speed of operation much less than the series resistor of Figure 1.

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Fig. 4. The MAX3370 implements a transmission-gate method of Level Conversion

The design in Figure 4 offers two other advantages. Firstly, for open-drain topologies, the MAX3370 includes 10kΩ pull-up resistors paralleled by a "speed-up" switch. This minimizes the need for external pull-up resistors while reducing the RC time-constant ramp associated with traditional open-drain topologies. Secondly, the MAX3370's tiny SC70 package also conserves valuable board space. Figure 5 shows an example of rail-to-rail driving of the output from a MAX3370 high-speed test circuit.

Fig. 5. The rail-to-rail driving of the output from a high-speed test circuit

5. Conclusion

The next generations of CMOS process will be packaged in an increasingly low input voltage. Designers need to be able to use these low-voltage devices, which use the latest high-speed, low-power silicon, but must be able to with other sub-systems connected components, such as liquid crystal display. This requires the transceiver to run at higher voltages, so bring on the level shifting needs. At present, many logic designers to meet the minimum operating voltage requirements as low as 0.8 V 1.2 V logic levels and other devices, such as micro-controllers, FPGA, ASIC and ASSP, and up to 3.3 V or 5 V BaoshengB. S. Yang etet al.al. // ProcediaProcedia EngineeringEngineering 2900 (2012)(2011) 1539000–000 – 1543 15435

CMOS voltage connect the circuit to work. As always, the demand is in power, speed, size and cost of inter-measure option.

Acknowledgements

This work was supported by Suzhou University Intelligent Information Processing Laboratory Open Subject Foundation under Grant 2011YKF11, in part by Education Department of Anhui Province Key Natural Science Research Foundation of China under Grant No. KJ2010A352, and Suzhou University Natural Science Research Foundation under Grant No. 2011YYB09.

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