DOCSLIB.ORG

Logic Selection Guide

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Logic Selection Guide Logic Selection Guide NC7SV19 Decoder/Demultiplexer combines high speed at low voltages in MicroPak™ and SC70 6 Lead SC70 79 mils .007 in2 2.0 mm 4.2 mm2 49 mils 1.25 mm 35 mils 83 mils 0.9 mm 2.1 mm FXLP34 FXL Series Translators for 1.0V-3.6V Logic Levels in MicroPak and SC70 MicroPak 57 mils .002 in2 1.45 mm 1.45 mm2 21 mils Optoelectronics 0.55 mm 39 mils 1 mm FXLP34 NC7NZ04 Triple-Bit Logic in MicroPak 8 and US8 8 Terminal MicroPak Interface & Logic 62 mils .003 in2 1.6 mm 2.56 mm2 21 mils 0.55 mm 62 mils 1.6 mm Analog Discrete FSAL200 Quad Analog SPDT Switches 16 Terminal MLP 118 mils .014 in2 3 mm 9 mm2 118 mils 39 mils 3 mm 1 mm 16 Lead QSOP 193 mils 4.90 mm .045 in2 29.35 mm2 53 mils 1.35 mm 63 mils 1.60 mm Across the board. Around the world.™ Logic Selection Guide Logic Migration and Low-Voltage Transition How to use this guide The data on this page (page 2) give an HC historic overview of Fairchild’s available Mature 5V CD4000 AS 74C logic families. The Quick Reference Attributes charts on page 3 may be a good first step if a particular type performance needs emphasis. The Family Specifications Comparison chart on page 4 lists general FACT VHC FAST ABT Advanced 5V performance by operating voltage. ALS Propagation Delay and Power Consumption are then further detailed in charts on page 5. The Product Portfolio and Description chart on page 6 summarizes VCX ALVC the functions that are available within each LVX LCX LVT TinyLogic® ULP of the logic families. The packaging table Low Voltage TinyLogic ULP-A (page 7) provides dimensions for all pack- FXL ages, and their availability by logic family. Performance Product Life Cycle Introduction Growth Maturity Saturation Decline Highest High High-volume Price Decreasing performance design-in production stability supplier base New High level Multiple Limited Not technologies of supplier suppliers new designs recommended resources for new designs Decreasing supplier base Increasing prices LV VHC ABT F100K ECL FACT HCMOS 100EL/100LVEL ECL Process Key FST BiCMOS FAST TinyLogic (UHS, HS, HST) BiCMOS (Low Voltage) LV ALS/AS LV LVT CMOS olume V CMOS (Low Voltage) LV GTLP LV LV LCX/LVX Bipolar LV VCX CD4000 ECL series LV ALVC TinyLogic (ULP, ULPA) FSA Analog Switch FXL Translators 2003 2000 1995 1990 1985 1980 1975 1970 1965 Product Introduction 2 www.fairchildsemi.com/logic Quick Reference Attributes for Logic Low-Static Analog Signal Logic Level Process Tech. High Speed Low Noise High Drive Low Voltage Board Space Power Video Signal Translation BiCMOS 5V ABT ABT BiCMOS 3V LVT LVT LVT CMOS 5V TinyLogic UHS TinyLogic HS/HST TinyLogic HS/HST TinyLogic HS/HST UHS FACT QS FACT FACT HC/HCT FACT QS FS VHC/VHCT HC/HCT FST (Fairchild Switch) VHC/VHCT GTLP GTLP FXL Translators FSA (Analog Switch) FST (Fairchild Switch) CMOS LV VCX LVX LCX LCX TinyLogic UHS FXL Translators LCX TinyLogic HS LVX LVX VCX Translators TinyLogic UHS VCX VCX FXLP Translators TinyLogic ULP-A TinyLogic ULP TinyLogic HS/UHS ALVC TinyLogic ULP TinyLogic ULP TinyLogic ULP GTLP GTLP TinyLogic ULP-A GTLP TinyLogic ULP-A TinyLogic ULP-A Bipolar FASTr ALS FASTr FAST ECL F100K ECL 100 EL / LVEL Series ECL Noise* Quick Reference Attributes for Analog Switches VOLP (V) VOLV (V) BiCMOS Notes Part Configuration RON (Ω) Supply RON (Ω) Band- THD Packages Voltage Flatness width ABT 0.6 -1.0 (VCC) (MHz) LVT/LVTH 3.3V 0.8 -0.8 ’244 SC70, MicroPak, FSA66 SPST 5.0 1.65V - 5.5V 6.0 250 0.011% SOT23 CMOS Quiet Output SC70, MicroPak, ULP 1.8V ** ** FSAT66 SPST 7.0 1.65V - 5.5V 6.0 250 0.011% SOT23 0.2 -0.2 VCX° (16) 1.8V HL or LH FSA3157 SPDT 5.0 1.65V - 5.5V 6.0 250 0.011% SC70, MicroPak 2.5V 0.6 -0.6 Transition FSA4157 SPDT 1.0 1.65V - 5.5V 0.2 350 0.003% SC70, MicroPak 3.3V 0.8 -0.8 ™ FSA266 Dual SPST 7.0 1.65V - 5.5V 6.0 300 0.016% US8, MicroPak V 0.3 -0.3 OLP LCX (16) 2.5V FSAU3157 SPDT 5.0 1.65V - 5.5V 6.0 250 0.011% SC70, MicroPak 3.3V 0.4 -0.5 FSA4684A Dual SPDT 1.0 1.65V - 5.5V 0.2 350 0.003% MicroPak CROSSVOLT 0.5 -0.5 LCX (8) 2.5V Quiet VOLV Quad SPDT Video TSSOP, QSOP, Output FSAV330 7.0 4.0V - 5.5V 300 3.3V 0.7 -0.7 Switch SOIC LVX 0.3 -0.2 Quad 2:1 FSAL200 Mux/Demux 6.0 3.0V - 5.5V 3.0 300 QSOP, MLP AC 1.6 -1.5 * ’244 function, (SPDT) LAN Switch C = 50pF, ACQ 0.9 -0.6 LOAD FSA3357 SP3T 6.0 1.65V - 5.5V 5.0 250 0.010% US8, MicroPak RL = 500 Ω, seven ACT 1.6 -1.6 TSSOP, SOIC, outputs switching, 74VHC4051 8 Channel Mux 30.0 2.0V - 6.0V N/A 35 0.008% PDIP ACTQ 0.9 -0.5 minimum input Dual 4 Channel TSSOP, SOIC, VHC 0.6 -0.6 skew, typical 74VHC4052 30.0 2.0V - 6.0V N/A 35 0.008% Mux PDIP values VHCT 0.7 -0.7 Triple 2 Channel TSSOP, SOIC, 74VHC4051 30.0 2.0V - 6.0V N/A 35 0.008% HC 0.5 -0.3 ** No overshoot/ Mux PDIP TSSOP, SOIC, HCT 0.5 -0.3 undershoot 74VHC4066 Quad SPST 30.0 2.0V - 12.0V N/A 100 0.008% ringing evident for PDIP Bipolar oscilliscope FASTr 0.8 -0.8 measurements FAST 0.6 -0.3 °C = 30pF AS 0.8 -1.4 LOAD ALS 0.2 -0.5 ‡ 16612 function www.fairchildsemi.com/logic 3 Family Specification Comparison* Technology Specified Power Supply** Speed † Drive †† Supply Current † Nominal VCC tPD IOL / IOH ICC Notes Sub 3 Volt * ’244 function used unless otherwise noted TinyLogic® ULP ◊◊ CMOS 0.9 / 1.2 / 1.5 / 1.8 / 2.5 / 3.3V 7ns -2.6µA / 2.6µA 5µA TinyLogic® ULP-A ◊◊ CMOS 0.9 / 1.2 / 1.5 / 1.8 / 2.5 / 3.3V 3ns -24µA / 24µA 5µA ** except for ECL and HC ◊◊◊ VCX CMOS 1.2 / 1.5 / 1.8 / 2.5 / 3.3V 2.5 / 3.2ns -24mA / 24mA 20µA ‡ input levels recognized by ALVC CMOS 1.8 / 2.5 / 3.3V 3.0ns -24µA / 24µA 20µA the device ‡‡ input levels the device is 3 Volt capable of driving TinyLogic® UHS ◊◊ CMOS 1.65 / 2.5 / 3.3 / 5V 4.5ns -32mA / 32mA 20µA † maximum specification at LCX (8) CMOS 2.5 / 3.3V 6.5ns -24mA / 24mA 10µA maximum specified VCC LCX (16) CMOS 2.5 / 3.3V 4.5ns -24mA / 24mA 20µA †† at maximum specified LVT (8) BiCMOS 3.3V 3.5ns -32mA / 64mA 5mA VCC LVT (16) BiCMOS 3.3V 3.5ns -32mA / 64mA 5mA ° 7407 used for LVX (8) CMOS 3.3V 12.0ns -4mA / 4mA 40µA specifications °° CD4010 used for 3Volt - 5 Volt specifications VHC CMOS 3.3 / 5V 8.5ns -8mA / 8mA 40µA ◊◊ NAND Gate (00) function HC CMOS 2 / 4.5 / 6V 25ns -6mA / 6mA 80µA for data TinyLogic® HS ◊◊ CMOS 2.0 / 3.0 / 4.5 / 6V°°° 21ns -2.6mA / 2.6mA 10µA ◊◊◊ CLOAD = 30pF AC CMOS 3.3 / 5V 7.5ns -24mA / 24mA 80µA ACQ CMOS 3.3 / 5V 6.5ns -24mA / 24mA 80µA GTLP CMOS 3.3 / 5V -48mA / 48mA 5mA 5 Volt VHCT CMOS 5V 9.5ns -8mA / 8mA 40µA HCT CMOS 5V 25ns -6mA / 6mA 80µA FST Fairchild Switch CMOS 4.0 - 5.5V 0.25ns N/A 3µA FASTr™ BiPolar 5V 3.9ns -15mA / 64mA 75mA FAST® BiPolar 5V 6.5ns -15mA / 64mA 90mA AS BiPolar 5V 6.2ns -15mA / 64mA 90mA ALS BiPolar 5V 10ns -15mA / 24mA 27mA F100K ECL -5.7 to -4.2V 1.55ns -1.8V into 50Ω -65mA 100 EVL ECL -5.5 to -4.2V 0.385ns -1.8V into 50Ω -36mA 100 LVEL ECL -3.0 to -3.8V 0.435ns -1.8V into 50Ω -30mA ACT CMOS 5V 10.0ns -24mA / 24mA 80µA ACTQ CMOS 5V 7.0ns -24mA / 24mA 80µA ABT BiCMOS 5V 3.6ns -32mA / 64mA 30mA TinyLogic® HST ◊◊ CMOS 4.5 / 5 / 5.5V 30ns -2.0mA / 2.0mA 10µA 15 Volt 74C CMOS 3 - 15V 70ns -14mA / 12mA 300µA CD4K°° CMOS 3 - 15V 40ns -1.25mA / 8mA 3µA 4 www.fairchildsemi.com/logic Propagation Delay* Output Rise and Fall Time* ECL F100K ‘315 0.9 (tpd) ABT 1.4 1.6 ECL 100 EL ‘11 0.3 (tpd) LVT (8) 3.3V 2.9 2.7 HL Edge LH Edge LVT (8) 3.5 4.5 ‘244 LVT (16) 3.3V 1.9 2.2 BiCMOS VCX°(16) 3.3V 2.1 2.4 LVT (16) ‘244 3.5 5.0 BiPolar VCX°(16) 2.5V 2.5 3.1 3.6 6.0 ‘244 VCX°(16) 1.8V 3.1 3.9 CMOS ABT ‘245 3.6 6.0 ALVC 1.8V 3.1 3.9 ‘374 4.0 6.5 LCX (8) 3.3V 2.4 2.9 ‘244 3.9 6.6 FASTr LCX (8) 2.5V 4.0 4.2 ‘245 3.9 7.0 LCX (16) 3.3V 2.4 2.9 ‘244 6.2 9.0 LCX (16) 2.5V 2.8 3.6 Ω AS ‘245 7.5 9.5 LVX 3.7 4.8 9.0 10.0 ‘374 AC 1.5 1.7 =500 L ‘244 6.7 8.0 ACT 1.5 1.7 FAST ‘245 7.0 9.0 ACQ 2.4 2.4 10.0 12.5 ‘374 ACTQ 2.4 2.5 = 50pF, R = 50pF, ‘244 10 20.0 VHC 3.2 4.1 10 20.0 4.1 3.6 ALS ‘245 HC LOAD ‘374 16 18 HCT 3.9 4.6 1.5 2.1 ULP-A SV125 1.0 FASTr FAST 2.3 2.3 = 30pF UHS 2.6 2.8 SZ125 AS 1.5 2.1 LOAD FS ‘211 0.25 3.3 ALS 2.3 2.3 * ’244 function, C * ‡ 16612 function °C ULP SP125 3.0 3.0 01 2 3 4 5 1.8V ‘244 3.2 3.9 Speed (ns) VCX° (16) 2.5V ‘244 2.2 2.6 3.3V ‘244 1.7 2.1 ‘244 3.2 3.9 Dynamic Current Consumption* (mA) ALVC ‘244 2.2 2.6 ‘244 1.7 2.1 1MHz 10MHz 35MHz 70MHz 90MHz LCX (16) ‘244 4.5 5.5 BiCMOS pd pz HST ST00 6.3 (tpd) t t ABT 19.7 43.8 115.9 266.0 303.3 HS 7.5 (tpd) ECL S00 LVT (8) 11.0 29.3 75.8 133.4 170.2 9.5 BiCMOS ‘244 6.5 LVT (16) 12.5 90.1 246.2 494.3 580.1 ACQ ‘245 7.0 10.0 BiPolar ‘374 9.0 10.0 CMOS CMOS ‘244 7.0 10.0 VCX (16) 9.9 61.9 146.8 253.7 312.7 ACTQ ‘245 7.5 10.5 LOAD ALVC 9.9 61.9 146.8 253.7 312.7 ‘374 9.5 10.5 LCX (8) 2.2 20.9 64.8 146.6 163.1 ‘244 8.5 10.5 VHC ‘245 8.5 12.0 LCX (16) 6.7 61.9 160.0 294.4 375.1 ‘374 11.5 11.0 LVX 2.0 19.4 64.0 100.1 106.3 ‘244 7.5 9.5 AC ‘245 7.0 10.0 AC 3.9 38.9 105.5 352.8 404.2 ‘374 10.5 12.5 ACQ 5.4 52.3 139.5 206.0 218.5 ‘244 10.0 10.5 VHC 3.1 30.8 103.0 180.7 192.1 ACT ‘245 9.0 11.0 ‘374 11.5 12.5 = 30pF HC 3.8 37.9 132.0 181.5 — ‘244 10.6 12.3 LOAD Bipolar LVX 10.1 14.5 ‘245 * datasheet maximum specification °C FAST 42.9 69.4 136.6 221.1 246.8 ‘374 14.1 13.2 FASTr 38.6 58.0 94.5 198.2 232.4 ‘244 25.0 38.0 HC/HCT ‘245 29.0 53.0 ALS 14.1 41.0 126.7 240.2 393.8 All figures represent typical performance values.
Load more

Recommended publications
  • EE 434 Lecture 2
    EE 330 Lecture 6 • PU and PD Networks • Complex Logic Gates • Pass Transistor Logic • Improved Switch-Level Model • Propagation Delay Review from Last Time MOS Transistor Qualitative Discussion of n-channel Operation Source Gate Drain Drain Bulk Gate n-channel MOSFET Source Equivalent Circuit for n-channel MOSFET D D • Source assumed connected to (or close to) ground • VGS=0 denoted as Boolean gate voltage G=0 G = 0 G = 1 • VGS=VDD denoted as Boolean gate voltage G=1 • Boolean G is relative to ground potential S S This is the first model we have for the n-channel MOSFET ! Ideal switch-level model Review from Last Time MOS Transistor Qualitative Discussion of p-channel Operation Source Gate Drain Drain Bulk Gate Source p-channel MOSFET Equivalent Circuit for p-channel MOSFET D D • Source assumed connected to (or close to) positive G = 0 G = 1 VDD • VGS=0 denoted as Boolean gate voltage G=1 • VGS= -VDD denoted as Boolean gate voltage G=0 S S • Boolean G is relative to ground potential This is the first model we have for the p-channel MOSFET ! Review from Last Time Logic Circuits VDD Truth Table A B A B 0 1 1 0 Inverter Review from Last Time Logic Circuits VDD Truth Table A B C 0 0 1 0 1 0 A C 1 0 0 B 1 1 0 NOR Gate Review from Last Time Logic Circuits VDD Truth Table A B C A C 0 0 1 B 0 1 1 1 0 1 1 1 0 NAND Gate Logic Circuits Approach can be extended to arbitrary number of inputs n-input NOR n-input NAND gate gate VDD VDD A1 A1 A2 An A2 F A1 An F A2 A1 A2 An An A1 A 1 A2 F A2 F An An Complete Logic Family Family of n-input NOR gates forms
    [Show full text]
  • CSCE 5730 Digital CMOS VLSI Design
    Lecture 2: Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides are borrowed from various books, websites, authors pages, and other sources for academic purpose only. The instructor does not claim any originality. CSCE 5730: Digital CMOS VLSI Design 1 Lecture Outline • Historical development of computers • Introduction to a basic digital computer • Five classic components of a computer • Microprocessor • IC design abstraction level • Intel processor family • Developmental trends of ICs • Moore’s Law CSCE 5730: Digital CMOS VLSI Design 2 Introduction to Digital Circuits CSCE 5730: Digital CMOS VLSI Design 3 What is a digital Computer ? A fast electronic machine that accepts digitized input information, processes it according to a list of internally stored instruction, and produces the resulting output information. List of instructions Æ Computer program Internal storage Æ Memory CSCE 5730: Digital CMOS VLSI Design 4 Different Types and Forms of Computer • Personal Computers (Desktop PCs) • Notebook computers (Laptop computers) • Handheld PCs • Pocket PCs • Workstations (SGI, HP, IBM, SUN) • ATM (Embedded systems) • Supercomputers CSCE 5730: Digital CMOS VLSI Design 5 Five classic components of a Computer Computer Processor Memory Devices Control Input Datapath Output (1) Input, (2) Output, (3) Datapath, (4) Controller, and (5) Memory CSCE 5730: Digital CMOS VLSI Design 6 What is a microprocessor ? • A microprocessor is an integrated circuit (IC) built on a tiny piece of silicon. It contains thousands, or even millions, of transistors, which are interconnected via superfine traces of aluminum. The transistors work together to store and manipulate data so that the microprocessor can perform a wide variety of useful functions.
    [Show full text]
  • Digital Logic and Design (Course Code: EE222) Ltlecture 6: Lliogic Famili Es
    Indian Institute of Technology Jodhpur, Year 2018‐2019 Digital Logic and Design (Course Code: EE222) LtLecture 6: LiLogic Fam ilies Course Instructor: Shree Prakash Tiwari EilEmail: sptiwari@iitj .ac.i n Webpage: http://home.iitj.ac.in/~sptiwari/ Course related documents will be uploaded on http://home.iitj.ac.in/~sptiwari/DLD/ Note: The information provided in the slides are taken form text books Digital Electronics (including Mano & Ciletti), and various other resources from internet, for teaching/academic use only 1 Overview •Early families (DL, RTL) • TTL •Evolution of TTL family • CMOS family and its evolution 2 Logic families Diode Logic (DL) •simpp;lest; does not scale •NOT not possible (need = an active element) Resistor-Transistor Logic (RTL) • replace diode switch with a tittransistor switc h •can be cascaded = • large power draw 3 Logic families Diode-Transistor Logic (DTL) • essentially diode logic with transistor amplification • reduced power consumption •faster than RTL = DL AND gate Saturating inverter 4 Logic Families • The bipolar transistor as a logical switch TTL Bipolar Transistor-Transistor Logic (TTL) •First introduced by in 1964 (Texas Instruments) •TTL has shaped digital technology in many ways • Standard TTL family (e.g. 7400) is obsolete •Newer TTL families used (e.g. 74ALS00) 6 TTL Bipolar Transistor-Transistor Logic (TTL) Distinct features •Multi‐emitter transistors 7 TTL A Standard TTL NAND gate 8 TTL A standard TTL NAND gate with open collector output 9 TTL evolution Schottky series (74LS00) TTL •A major
    [Show full text]
  • Chapter6-6.Pdf
    MEMS1082 Chapter 6 Digital Circuit 6-6 Department of Mechanical Engineering TTL and CMOS ICs , TTL and CMOS output circuit totem pole configuration When the upper transistor is forward biased and the bottom When input is high, the p- transistor is off, the output is type transistor (top) is off, high. The resistor, transistor, n-type is on. So the and diode drop the actual output is pulled low. The output voltage to a value device sinks current typically about 3.4 V. When the lower transistor is forward When input is low, the n- biased and the top transistor is type transistor (bottom) is off, the output is low. off, p-type is on. So the The TTL device sources current output is pulled high. The when there is a high output and device sources current. sinks current when the output is low. TTL device dissipates power continuously regardless of whether the output is high or low. Department of Mechanical Engineering The MOSFET and MOSFET switching states There are presently two general types of MOSFETs: depletion and enhancement. MOS digital ICs use enhancement MOSFETs exclusively The direction of the arrow indicates either P- or N-channel. The symbols show a broken line between the source and drain to indicate that there is normally no conducting channel between these electrodes. Symbol also shows a separation between the gate and the other terminals to indicate the very high resistance (typically around 1012 Ω ) between the gate and channel. Department of Mechanical Engineering The MOSFET and MOSFET switching states Department of Mechanical Engineering N-MOS Inverter Department of Mechanical Engineering N-MOS NAND Gate Department of Mechanical Engineering N-MOS NOR Gate Department of Mechanical Engineering CMOS Logic The complementary MOS (CMOS) logic family uses both P- and N- channel MOSFETs in the same circuit to realize several advantages over the P-MOS and N- MOS families.
    [Show full text]
  • Anr018 Gnss I2c Communication
    ANR018 GNSS I2C COMMUNICATION VERSION 1.2 JUNE 2, 2021 Revision history Manual Notes Date version 1.0 • Initial version June 2020 1.1 • Figure 7 and 8 updated July 2020 1.2 • Updated Chapter 3 June 2021 ANR018 GNSS I2C Communication version 1.2 © June 2021 www.we-online.com/wireless-connectivity 1 Abbreviations and abstract Abbreviation Description ASCII American Standard Code for Information Interchange CTS Clear to send I2C Inter-IC bus GND Ground GNSS Global Navigation Satellite System HIGH Digital (logic) high level IC Integrated Circuit IDC Insulation Displacement Contact LOW Digital (logic) low level µC Microcontroller NMEA National Marine Electronics Association OSP One Socket Protocol PC Personal Computer RTS Request to send SCL Serial Clock SDA Serial Data USB Universal Serial Bus ANR018 GNSS I2C Communication version 1.2 © June 2021 www.we-online.com/wireless-connectivity 2 Contents 1 Introduction5 2 I2C Digital interface6 2.1 General characteristics..............................6 2.2 SDA and SCL logic levels............................6 2.3 Communication phase..............................6 2.3.1 Idle state.................................6 2.3.2 START(S) and STOP(P) condition...................7 2.3.3 Data validity...............................7 2.3.4 Data format...............................8 2.3.5 Acknowledge and No-Acknowledge..................8 2.3.6 Addressing the GNSS module.....................8 2.3.7 GNSS communication protocol....................9 2.4 I2C timing parameters..............................9 3 Hardware Setup 10 3.1 Hardware Setup - 1.8V.............................. 10 3.2 Evaluation Board Modification - 1.8V...................... 11 3.3 Hardware Setup - Erinome-I........................... 13 3.4 Evaluation Board Modification - Erinome-I................... 14 4 Application Example 16 4.1 Total Phase Aardvark host adapter......................
    [Show full text]
  • VLSI Overview
    Lecture 1: VLSI Overview Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides are borrowed from various books, websites, authors pages, and other sources for academic purpose only. The instructor does not claim any origgyinality. Digital CMOS VLSI Design 1 Lecture Outline • Historical development of computers • ItIntro duc tion toabibasic dig ita l computer • Five classic components of a computer • Microprocessor • IC design abstraction level • Processor Trend • DlDevelopmen tltal tdtrendsof ICs • Moore’s Law Digital CMOS VLSI Design 2 Introduction to Digital Circuits Digital CMOS VLSI Design 3 What is a digital Computer ? A fast electronic machine that accepts digitized input information, processes it according to a list of internally stored instruction, and produces the resulting output information. List of instructions Computer program Internal storage Memory Digital CMOS VLSI Design 4 Different Types and Forms of Computer • Personal Computers (Desktop PCs) • Notebook computers (Laptop computers) • Handheld PCs • Pocket PCs • WkttiWorkstations (SGI, HP, IBM, SUN) • ATM (Embedded systems) • Supercomputers Digital CMOS VLSI Design 5 Five classic components of a Computer Computer Processor Memory Devices Control Input Datapath Output (1) Input, (2) Output, (3) Datapath, (4) Controller, and (5) Memory Digital CMOS VLSI Design 6 What is a microprocessor ? • A microprocessor is an integrated circuit (IC) built on a tiny piece of silicon. It contains thousands, or even millions, of transistors, which are interconnected via superfine traces of aluminum. The transistors work together to store and manipulate data so that the microprocessor can perform a wide variety of useful functions. The particular functions a microprocessor performs are dictated by software.
    [Show full text]
  • Logic Families/Objectives
    Logic Families/Objectives – Digital Logic Voltage and Current Parameters • Fan-out, Noise Margin, Propagation Delay – TTL Logic Family – Supply current spikes and ground bounce – TTL Logic Family Evolution –ECL – CMOS Logic Families and Evolution – Logic Family Overview 29/09/2005 EE6471 (KR) 121 Logic Families/Level of Integration – SSI <12 gates/chip Level of integration ever increasing, because of – MSI 12..99 gates/chip •cost •speed – LSI ..1000 gates/chip •size •power – VLSI …10k gates/chip •reliability – ULSI …100k gates/chip Limits of integration: – GSI …1Meg gates/chip •packaging •power dissipation •inductive and capacitive components Note: Ratio gate count/transistor count •flexibility is roughly 1/10 •critical quantity 29/09/2005 EE6471 (KR) 122 Logic Families/Level of Integration – Remember: Gordon Moore, 1975. Predictions: • Mosfet device dimensions scale down by a factor of 2 every 3 years • #transistors/chip double every 1-2 years. Source: G. Sery, Intel 29/09/2005 EE6471 (KR) 123 Logic Families/Static VI Parameters Vcc Vcc Vcc Ioh Iih Iol Iil Voh Vih Vol Vil Parameter Comment Voh(min) High-Level Output Voltage. The minimum voltage level at a logic circuit output in the logical 1 state under defined load conditions. Vol(max) Low-Level Output Voltage. The maximum voltage level at a logic circuit output in the logical 0 state under defined load conditions. 29/09/2005 EE6471 (KR) 124 Logic Families/Static VI Parameters Vcc Vcc Vcc Ioh Iih Iol Iil Voh Vih Vol Vil Parameter Comment Vih(min) High-Level Input Voltage. The minimum voltage level required for a logical 1 at an input.
    [Show full text]
  • Computer Architectures an Overview
    Computer Architectures An Overview PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 25 Feb 2012 22:35:32 UTC Contents Articles Microarchitecture 1 x86 7 PowerPC 23 IBM POWER 33 MIPS architecture 39 SPARC 57 ARM architecture 65 DEC Alpha 80 AlphaStation 92 AlphaServer 95 Very long instruction word 103 Instruction-level parallelism 107 Explicitly parallel instruction computing 108 References Article Sources and Contributors 111 Image Sources, Licenses and Contributors 113 Article Licenses License 114 Microarchitecture 1 Microarchitecture In computer engineering, microarchitecture (sometimes abbreviated to µarch or uarch), also called computer organization, is the way a given instruction set architecture (ISA) is implemented on a processor. A given ISA may be implemented with different microarchitectures.[1] Implementations might vary due to different goals of a given design or due to shifts in technology.[2] Computer architecture is the combination of microarchitecture and instruction set design. Relation to instruction set architecture The ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers, address and data formats among other things. The Intel Core microarchitecture microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machine is usually represented as (more or less detailed) diagrams that describe the interconnections of the various microarchitectural elements of the machine, which may be everything from single gates and registers, to complete arithmetic logic units (ALU)s and even larger elements.
    [Show full text]
  • 48-Bit, High Current, Logic Level Digital I/O Board for PCI
    User's Guide http://www.omega.com e-mail: [email protected] CIO-DIO48 CIO-DIO48H CIO-DIO96 CIO-DIO192 INTRODUCTION ................................... 1 Cable from DIO board QUICK START ..................................... 2 plugs into connector TM labeled IN Cable to second ERB or INSTALL THE INSTACAL SOFTWARE .................... 2 TM SSR board plugs into RUN INSTACAL ..................................... 2 connector labeled OUT OPERATION ....................................... 4 INSTALLATION ...................................... 4 BASE ADDRESS ...................................... 4 WAIT STATE JUMPER .................................. 6 INSTALLING THE CIO-DIO IN THE COMPUTER ............... 6 CABLING TO THE DIO CONNECTOR ....................... 7 SIGNAL CONNECTION - CIO-DIO48 ........................ 7 UNCONNECTED INPUTS FLOAT .......................... 8 CONNECTOR DIAGRAM ................................ 8 Cable from DIO board Cable to second ERB or ARCHITECTURE ................................... 9 plugs into connector SSR board plugs into labeled IN connector labeled OUT 82C55 CONTROL & DATA REGISTERS ...................... 9 82C55 DIGITAL I/O REGISTERS .......................... 11 SPECIFICATIONS ................................. 14 POWER CONSUMPTION ............................... 14 DIGITAL I/O ........................................ 15 ELECTRONICS AND INTERFACING ................. 16 PULL UP & PULL DOWN RESISTORS ...................... 16 UNCONNECTED INPUTS FLOAT ......................... 18 CIO-ERB-24 and SSR-RACK24 provide
    [Show full text]
  • Designing Combinational Logic Gates in Cmos
    CHAPTER 6 DESIGNING COMBINATIONAL LOGIC GATES IN CMOS In-depth discussion of logic families in CMOS—static and dynamic, pass-transistor, nonra- tioed and ratioed logic n Optimizing a logic gate for area, speed, energy, or robustness n Low-power and high-performance circuit-design techniques 6.1 Introduction 6.3.2 Speed and Power Dissipation of Dynamic Logic 6.2 Static CMOS Design 6.3.3 Issues in Dynamic Design 6.2.1 Complementary CMOS 6.3.4 Cascading Dynamic Gates 6.5 Leakage in Low Voltage Systems 6.2.2 Ratioed Logic 6.4 Perspective: How to Choose a Logic Style 6.2.3 Pass-Transistor Logic 6.6 Summary 6.3 Dynamic CMOS Design 6.7 To Probe Further 6.3.1 Dynamic Logic: Basic Principles 6.8 Exercises and Design Problems 197 198 DESIGNING COMBINATIONAL LOGIC GATES IN CMOS Chapter 6 6.1Introduction The design considerations for a simple inverter circuit were presented in the previous chapter. In this chapter, the design of the inverter will be extended to address the synthesis of arbitrary digital gates such as NOR, NAND and XOR. The focus will be on combina- tional logic (or non-regenerative) circuits that have the property that at any point in time, the output of the circuit is related to its current input signals by some Boolean expression (assuming that the transients through the logic gates have settled). No intentional connec- tion between outputs and inputs is present. In another class of circuits, known as sequential or regenerative circuits —to be dis- cussed in a later chapter—, the output is not only a function of the current input data, but also of previous values of the input signals (Figure 6.1).
    [Show full text]
  • Design of 64-Bit Arithmetic Logic Unit (ALU) Based on BSIM4 Model Using Tanner
    IJSART - Volume 2 Issue 10 –OCTOBER 2016 ISSN [ONLINE]: 2395-1052 Design of 64-bit Arithmetic Logic Unit (ALU) Based on BSIM4 Model Using Tanner Pragati Nagdeote1, Prof. Manisha Waje2 1, 2 Department of ENTC 1, 2 SPPU/G.H.Raisoni College of Engineering and Management, Pune, Maharashtra/Zone, India Abstract- Arithmetic circuits play a vital role in computational CMOS provides: an exceptionally low power-delay product, and digital circuits. Arithmetic Logic Unit (ALU) can perform the ability to accommodate millions of devices on a single various arithmetic and logical functions. Proposed 64-bit ALU chip, and flexible, custom design methodologies which permit comprises of different arithmetic functions such as addition, optimization, as required, for lowest cost, lowest power, or subtraction and logical functions like AND logic, OR logic, highest speed. In the recent years, there has been a large NOR logic and NAND logic. ALU always faces the issues of progress in the area of computer systems which are produce power consumption when there are the complex operations, and based on general purpose micro-processors [4]. ALU is therefore to overcome this problem the low power 64-bit ALU one of the most power hungry building blocks in the is designed using adiabatic logic with 180nm CMOS processor, increasing the power and thermal issues. The technology. BSIM4 model is used for the implementation of presence of multiple ALUs in current-day processors further 64-bit full adder, 64-bit AND logic, 64-bit OR logic, 4:1 creates the problem, impacting the circuit reliability and Multiplexer, 2:1 Multiplexer and Proposed design is verified increasing the power cost.
    [Show full text]
  • Voltage Translation How to Manage Mixed-Voltage Designs with NXP Level Translators SECTION 1.0 Why Voltage Translation Matters
    Voltage translation How to manage mixed-voltage designs with NXP level translators SECTION 1.0 Why voltage translation matters Table of contents In recent years, voltage translation has become an important part of electronic design, especially in portable 1.0 Why voltage translation matters 3 applications. That’s because the latest data and application processors for mobile applications are typically 2.0 Unidirectional level translators 7 produced in advanced, low-power CMOS process technologies that use a supply voltage of 1.8 V or lower, but the peripherals they connect to, including memories, image sensors, relays, and RF transceivers, are more 2.1 Low-to-high level translation 7 likely to use older, lower-cost process technologies that operate at higher levels, at or above 3 or 5 V. Voltage- 2.2 High-to-low level translation 10 level translators (Figure 1-1) enable these different devices to work together, without producing damaging current flow or signal loss, so the system operates more efficiently and saves power. 3.0 Bidirectional level translators with direction pin 12 4.0 Bidirectional level translators with auto direction sensing 14 AC/DC Battery 4.1 Active devices for bidirectional translation with auto direction 14 charger 4.2 Passive devices for bidirectional translation with auto direction 19 5.0 Application-specific level translators 28 Memory Charger PMU SIM card 5.1 Translators for use with SIM cards 28 card 5.2 I2C muxes and switches that also perform bidirectional translation 30 Audio Cellular & RF, GPS, connectity Voltage-level translators WLAN, BT radio Blinker black light Voltage- Voltage- level Processor level translators translators Flash MCU, special I2C, MIPI, NFC/RFID function µC SPI UART Camera Voltage-level translators Display USB Keypad Sensor HDMI Figure 1-1.
    [Show full text]