Design and Implementation of a High-Speed PCI-Express Bridge Mandus Börjesson Håkan Gerner

LiU-ITN-TEK-A--19/012--SE

Design and implementation of a high-speed PCI-Express bridge Mandus Börjesson Håkan Gerner

2019-06-05

Department of Science and Technology Institutionen för teknik och naturvetenskap Linköping University Linköpings universitet nedewS ,gnipökrroN 47 106-ES 47 ,gnipökrroN nedewS 106 47 gnipökrroN LiU-ITN-TEK-A--19/012--SE

Design and implementation of a high-speed PCI-Express bridge Examensarbete utfört i Elektroteknik vid Tekniska högskolan vid Linköpings universitet Mandus Börjesson Håkan Gerner

Handledare Qin-Zhong Ye Examinator Adriana Serban

Norrköping 2019-06-05 Upphovsrätt

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This master thesis will cover the prestudy, hardware selection, design and implementation of a PCI Express bridge in the M.2 form factor. The thesis subject was proposed by WISI Norden who wished to extend the functionality of their hardware using an M.2 module. The bridge fits an M-Key M.2 slot and has the dimensions 80x22 mm. It is able to communicate at speeds up to 8 Gb/s over PCI Express and 200 Mbit/s on any of the 20 LVDS/CMOS pins. The prestudy determined that an FPGA should be used and a Xilinx Artix-7 device was chosen. A PCB was designed that hosts the FPGA as well as any power, debugging and other required systems. Associated proof-of-concept software was designed to verify that the bridge operated as expected. The software proves that the bridge works but requires improvement before the bridge can be used to translate sophisticated protocols. The bridge works, with minor hardware modifications, as expected. It fulfills all design requirements set in the master thesis and the FPGA firmware uses a well-established protocol, making further development easier. Acknowledgments

We would like to thank the supervisor and examiner who took part in this Master thesis. Your feedback has proven valuable throughout the entire thesis work, not only helping us overcome obstacles but also helping us improve the quality of the ﬁnal report.

We are grateful of our fellow students who helped motivate us, gave valuable input and were always eager to discuss ways to overcome our engineering challenges.

We also wish to extend a special thank you to our mentor Jonas Åberg. You have shared your many years of experience in hardware design and helped us boost the quality of the project beyond our expectations.

ii Contents

Abstract i

Acknowledgments ii

Contents iii

List of Figures v

List of Tables vii

1 Introduction 1 1.1 Aim...... 1 1.2 Background ...... 2 1.3 Research questions ...... 3 1.4 Design requirements ...... 3 1.5 Delimitations ...... 4

2 Prestudy 5 2.1 System sketch ...... 5 2.2 Possible solutions ...... 6

3 Selection of hardware 10 3.1 FPGA selection ...... 10 3.2 Non-volatile memory selection ...... 13 3.3 Regulator selection ...... 13

4 System Description 16 4.1 M.2 Connector ...... 16 4.2 FPGA ...... 17 4.3 Programming and debugging ...... 18 4.4 Power management ...... 19 4.5 External connectors ...... 21

5 Hardware design and implementation 22 5.1 Stackup and design rules ...... 22 5.2 M.2 connector ...... 24 5.3 FPGA conﬁguration banks ...... 25 5.4 FPGA I/O banks ...... 26 5.5 FPGA transceivers and PCI Express nets ...... 26 5.6 Power management ...... 26 5.7 Programming and debugging interface ...... 30 5.8 Decoupling ...... 31

6 Manufacturing 33

iii 6.1 Bill of materials ...... 33 6.2 Assembly and soldering ...... 33 6.3 Tests and inspection ...... 33

7 Software 37 7.1 EEPROM memory veriﬁcation ...... 37 7.2 Flash memory interfacing ...... 38 7.3 FPGA ﬁrmware ...... 41 7.4 Platform application ...... 43

8 Results 44 8.1 PCB Layout ...... 44 8.2 Bridge performance ...... 45 8.3 Summary of hardware modiﬁcations ...... 46 8.4 Software design ...... 47

9 Discussion and conclusion 49 9.1 Design requirements and research questions ...... 49 9.2 Implementation ...... 49

Bibliography 51

iv List of Figures

2.1 High level sketch of the system...... 6 2.2 System sketch of the solution using a CPU with native PCI Express support. . . . . 6 2.3 System sketch of the solution when using a CPU without native support for PCI Express...... 7 2.4 System sketch of the solution when using a FPGA...... 8

3.1 Total accumulated price for N number of units, assuming 100 units/year...... 12

4.1 System layout on the M.2 module...... 16 4.2 M.2 connector system connections...... 17 4.3 FPGA system connections...... 17 4.4 Programming and debugging system connections...... 19 4.5 Power management system connections...... 19 4.6 Power hierarchy option considered in the design...... 20 4.7 M.2 connector system connections...... 21

5.1 Illustration of design rules used during layout...... 23 5.2 Open-drain logic level conversion. HV indicates High (3.3 V) logic level, LV indicates low (1.8 V) logic level...... 24 5.3 Layout surrounding the M.2 connector on the top layer of the PCB. Notice the fencing and return path vias as well as the ground plane (yellow) on the layer below the PCI Express lanes...... 25 5.4 Fanout of the SPI and JTAG nets (highlighted) under the Artix-7...... 25 5.5 Power-on sequencing using RC networks...... 27 5.6 I/O voltage sequencing and selectable I/O voltage solution...... 28 5.7 Characteristic change of capacitance according to DC-voltage...... 29 5.8 Artix-7 FPGA power pin mapping...... 30 5.9 Programming and debugging interface with related components marked...... 31

6.1 Load switch schematic ...... 34 6.2 Reference clock differential signal measured on the bridge...... 36 6.3 PCI Express link lists the capabilities of the bridge...... 36

7.1 Console output after a successful write to the EEPROM...... 38 7.2 Enumeration of the SMBus of the bridge. Notice the SMBus-SPI bridge at ’0x28’ and the EEPROM at ’0x50’ and ’0x51’...... 38 7.3 Ideal SPI data transfer...... 39 7.4 SPI data transfer using the built-in CS pin feature...... 40 7.5 Final SPI data transfer implementation...... 40 7.6 Overview of the VHDL block design...... 41 7.7 Platform application writing to register and validates its value...... 43

8.1 Layout – Top Layer ...... 44

v 8.2 Layout – Inner Layer 1 ...... 45 8.3 Layout – Inner Layer 2 ...... 45 8.4 Layout – Bottom ...... 45 8.5 Output signal at 100 MHz...... 46 8.6 Output signal at 200 MHz...... 46 8.7 the nPor fix. Right: Altium designer screenshot with the modifications, Left: Same modification on the PCB...... 47 8.8 The CLKREQ fix. Right: Altium designer screenshot with the modification, Left: Same modification on the PCB...... 47 8.9 Signals; TX ready, data request, data in, data out, clock and state...... 48 8.10 Output signals; data and clock...... 48

vi List of Tables

1.1 PCI Express transfer characteristics...... 2

3.1 Product series candidates...... 10 3.2 Selected devices from the different product families...... 11 3.3 Artix-7 - Recommended DC and AC characteristics...... 14 3.4 Texas Instruments LM26480 internal regulators...... 15

4.1 Current ﬂow and power loss in hierarchy option A...... 21 4.2 Current ﬂow and power loss in hierarchy option B...... 21

5.1 JLC7628 layer stackup...... 23 5.2 Routing rules used during the design of the bridge...... 24 5.3 Optimum and designed power-on sequence for the different power nets...... 27 5.4 Regulator SET_IO state to voltage relation...... 28 5.5 Calculated values for Peak Current through the inductor and voltage ripple on the output, using: Vin = 3.3V, η = 0.85, Iout,max = 0.8A, Cout = 10µF, L = 2.2µH, f = 2MHz...... 29 5.6 Artix-7 Decoupling network for XC7A12T and XC7A35T ...... 31

8.1 Summary of bridge dimensions and performance ...... 44

vii

List of Tables

Abbreviations

Abbreviation Meaning AC Alternating Current BGA Ball Grid Array BOM Bill Of Materials DC Direct Current CAD Computer Aided Design CLK Clock CMOS Complementary Metal Oxide Semiconductor CPU Central Processing Unit DLL Data link layer DSP Digital Signal Processor EEPROM Electronically Erazable Programmable Read Only Memory ESR Equivalent Series Resistance FPGA Field Programmable Gate Array GPIO General Purpose Input/Output GT/s Gigatransfers per second I2C Inter-Integrated Circuit I/O Input/Output IDE Integrated Development Environment IP Intellectual Property JTAG Joint Test Action Group LDO Low Drop-Out regulator LE Logic Elements LUT Look-Up Table LVDS Low Voltage Differential Signaling MCU Micro Controller Unit MISO Master In Slave Out MMCM Mixed-Mode Clock Manager MOSI Master Out Slave In NC Normally Closed NO Normally Open NVS Non-Volatile Storage PCB Printed Circuit Board PCI Express Peripheral Component Interconnect Express PHY PHYsical PISO Parallel In - Serial Out PLL Phase-Locked Loop PMIC Power Management Integrated Circuit RAM Random Access Memory SerDes Serializer/Deserializer SIPO Serial In - Parallel Out SMBus System Management Bus SMPS Switch-Mode Power Supply SPI Serial Peripheral Interface SPDT Single Pole Double Throw SSI Synchronous Serial Interface SSTL Stub-Series Terminated Logic TL Transaction Layer TLP Transaction Layer Package TTL Transistor-Transistor Logic UI Unit interval USB Universal Serial Bus VHDL Very High-speed Integrated Circuit Hardware Description Language 1 Introduction

As modern technology develops, high-speed interfaces and expandable design are becoming more prominent. Currently, one of the most widespread standards for expansion modules in personal computers is the Peripheral Component Interconnect Express (PCI Express) interface. The interface is usually accessible through expansion slots on the device and is, for example, used to improve performance or allow communication over interfaces that are not natively supported. Examples of modules that typically ﬁt in expansion slots are hard drives, graphics processors, and ethernet cards. While a variety of boards which extend the functionality of master devices through the M.2 connector already exist, most of them are focused on hardware acceleration of algorithms with limited connectivity options. They, therefore, lack the necessary outputs needed to interface with other hardware. The main objective of this project is to add interface functionality to PCI Express capable devices with adaptability and upgradability in mind. The purpose of this Master Thesis’s work is to create an expansion board to extend the functionality of WISI Norden’s current hardware. WISI Norden provides services for distribution of TV transmissions. They are currently using hardware that features an M.2 connector with a PCI Express interface. Throughout the report, two words will be used frequently when referring to the different hardware:

• Bridge refers to the the ﬁnal product of the master thesis. This includes the PCB and components mounted on it as well as any software written.

• Platform refers to the board or contact that the bridge is supposed to be connected to.

The bridge should act as a translator between PCI Express and any other protocol deﬁned by the user. In other words, PCI Express is converted to a protocol and transmitted. If any messages are received, they are converted to PCI Express and sent to the platform.

1.1 Aim

The purpose of the master thesis is to design and implement a bridge that enables communication with hardware that does not have native PCI Express support. The bridge should convert PCI Express to Low Voltage Differential Signaling (LVDS) and/or CMOS-logic. LVDS and CMOS covers the most frequently used solutions for communicating between different

1 1.2. Background hardware; differential and single-ended. Furthermore, the (CMOS/LVDS) side should be easily re-conﬁgurable in order to support different types, amounts and combinations of interfaces.

1.2 Background

This section will describe the theoretical background which is most relevant for understanding the general concepts regarding the M.2 standard as well as the PCI Express protocol.

M.2 connector M.2 is a specification for connectors associated to computer mounted expansions cards. It defines a standard for physical dimensions. It also defines different keying-notches in order to prevent cards from being used in incompatible hosts. The M.2 standard is available in different configurations which are capable of PCI Express Gen 3.0, USB 3.0 and Serial ATA 3.0.

The PCI Express protocol PCI Express is an interface designed for expansion boards such as video-, sound- and ethernet cards. It consists of one or multiple data lanes, where each lane can transfer data in both directions. Multiple data lanes can be utilized to improve the data throughput of a PCI Ex- press link. However, more lanes correspond to a larger footprint and more complex design. Transfer rates of the standard are seen in Table 1.1.

Table 1.1: PCI Express transfer characteristics.

Full duplex bandwidth Standard version Transfer rate x1 x2 x4 PCI Express 1.0 2.5 GT/s 250 MB/s 500 MB/s 1 GB/s PCI Express 2.0 5 GT/s 500 MB/s 1 GB/s 4 GB/s PCI Express 3.0 8 GT/s 1 GB/s 2 GB/s 4 GB/s PCI Express 4.0 16 GT/s 2 GB/s 4 GB/s 8 GB/s PCI Express 5.0 32 GT/s 4 GB/s 8 GB/s 16 GB/s

The PCI Express interface is communicating through a link between a root-complex (master) and an endpoint (slave) device. The platform that this project is developed against is a root-complex. Hence, the bridge has to function as an endpoint device.

Layers PCI Express is a layered protocol which consists of a physical layer, data link layer, and a transaction layer.

Transaction Layer PCI Express relies on request and completion transactions to transfer data between devices. This is the primary task of the Transaction Layer (TL). The layer transmits requests and completion transactions from the logic core and turns them into outgoing PCI Express packets. It receives incoming transactions from the Data Link Layer (DLL) and sends them to the core.

2 1.3. Research questions

Data Link Layer The data link layer’s purpose is to detect and correct faults in the PCI Express data transmission. It continually monitors each PCI Express link and checks the data integrity of Transaction Layer Packets (TLP’s) exchanged by devices.

Physical Layer The Physical Layer (PHY) refers to the physical properties of the PCI Express link. Upon link establishment, the highest number of mutual lanes is selected to allow for the maximum compatible data rate. Each lane consists of a unidirectional transmitting and receiving differential pair, resulting in a total of 4 wires. The physical layer should be able to determine the clock frequency from the data transmission. PCI Express Gen 1 and 2 utilizes an 8B/10B encoding/decoding scheme which converts every 8 bits into 10 bits. The additional bits are placed where they generate a suf- ﬁcient amount of rising and falling edges to properly establish the clock signal. The encoding/decoding scheme adds 20 % to the package overhead. PCI Express Gen 3.0 and above implement a 128B/130B scheme with scrambling, which is far more efﬁcient at « 1.5 % additional overhead.

1.3 Research questions

The master thesis is based on a set of questions presented below.

1. What are the alternatives to achieving PCI Express to LVDS/CMOS conversion?

2. Which alternative is expected to give the best result considering:

• Signal propagation delay. • Data throughput. • Component cost. • Physical size of the design. • Complexity.

3. What signal propagation delay and throughput can be expected of the system?

1.4 Design requirements

This section will cover the requirements for the design. The solution that is chosen should fulﬁll all of the requirements.

PCI Express interface The design should be able to interface with at least a PCI Express Gen1 x2 interface, meaning that there are two data lanes at 2.5 GT/s. Later generations are desirable but not necessary. The lane conﬁguration (x2) must not change. The design should act as a PCI Express endpoint.

LVDS/CMOS interface The interface should be able to support both LVDS and CMOS interfaces. The number of interfaces should be conﬁgurable to suit the application. Furthermore, each interface should be able to transmit data at up to 150 MHz.

3 1.5. Delimitations

Physical size and characteristics The circuit board should have the dimensions 22x80x0.8 mm, which follows the standard size of M.2 expansion cards. If the size criteria is not possible to fulﬁll, the circuit board should be able to ﬁt in WISI Nordens hardware. The M.2 Connector should be M-key and the PCB should be 0.8 mm thick.

Power dissipation The design will be housed in a small area with limited cooling options. The solutions should not require active cooling.

1.5 Delimitations

The delimitations for this thesis are:

• The ﬁrmware for the solution should be seen as a demo-code, meaning all features do not have to be implemented.

• The CMOS/LVDS side of the bridge does not have to convert PCI Express to a known protocol, only show the differential/single-ended signals and their correspondence to the user input.

4 2 Prestudy

The prestudy consists of an analysis of available options that support the previously described functionality. The study includes an investigation of pros and cons with the different solutions as well as a decision of which of the solutions is to be implemented. The PCI Express standard and data ﬂow between devices were studied in order to get an understanding of what solutions were possible. When enough knowledge about the standard had been gained, different alternatives for achieving the desired functionality were investigated. The alternatives are presented below and compared in order to determine which one is best suited. Aspects that weigh into the decision include, but are not limited to:

• The price of components

• Physical size of components

• Complexity of the solution

• Life cycle of key components

• Power requirements

2.1 System sketch

Conversion between PCI Express and CMOS/LVDS can be achieved through different techniques. The focus of the prestudy is to determine the most suitable method of acquiring the desired result while considering cost, complexity, physical dimensions and longevity. The data will be transferred to the bridge via a high-speed PCI Express link where the following actions are performed:

1. PCI Express overhead is stripped from the data and sent as LVDS/CMOS to the recipi- ents over a user-deﬁned protocol.

2. The recipient answers, the overhead is reinserted into the data and sent to the root complex.

5 2.2. Possible solutions

The bridge should have the ability to communicate with multiple devices with low latency. A sketch of the system is illustrated in Fig. 2.1, where the Bridge block represents the system that handles the PCI Express to LVDS/CMOS conversion.

Figure 2.1: High level sketch of the system.

The PCI Express endpoint requirement greatly limits the number of available solutions since a large portion of available devices only supports root complex mode. Moreover, all alternatives must be able to perform some sort of data manipulation in order to convert data between the interfaces, further limiting the choices. One idea was to use a PCI Express switch with multiple hardware bridges. A benefit of such a solution is that all interfaces would show up as separate endpoints. However, the concept was discarded since such a solution would be very difficult to reconfigure after construction and the number of hardware bridges that support different interfaces is limited. With all things considered, the pool of solutions was reduced to either a Central Processing Unit (CPU) or a Field Programmable Gate Array (FPGA).

2.2 Possible solutions

The focus of this section is to describe the alternative solutions and their advantages/disadvanteges.

CPU A CPU is often a good choice when data acquisition and processing is required. They are proven to work reliably and offer high clock-speeds, which is required for the implementation of the bridge. A system sketch of a bridge using a CPU is shown in Fig. 2.2. The light gray block SSI to LVDS/CMOS Bridge symbolizes an optional interface that allows the CPU to communicate with the external contact, if it is not able to do so directly.

Figure 2.2: System sketch of the solution using a CPU with native PCI Express support.

Many CPUs allow the use of an operating system such as Linux. This means that there are more alternatives when it comes to programming languages.

6 2.2. Possible solutions

A drawback is that, while many CPUs support PCI Express, few of them can be used in an endpoint conﬁguration. Two manufacturers that produce endpoint capable CPUs are Texas Instruments and Broadcomm. Another drawback is that CPUs commonly lack LVDS output functionality. Fortunately, many CPUs feature high-speed serial interfaces such as Quad SPI that allow them to be connected to external components that can act as LVDS/CMOS interfaces. The summary of the pros and cons of this system is presented below.

Pros Cons - Easy to work with. - Limited availability for endpoint capable CPUs - Features an operating system - Boot time - Uncommon, limited amount of sources - Real-time system, possibly introduces latency - Might requre external hardware on LVDS/CMOS side - Complexity (design)

PCI Express to PHY interface If the desired device does not support PCI Express, an Integrated Circuit (IC) with PCI Express to PHY bridge functionality can be employed between the PCI Express interface and the computing device, as illustrated in Fig. 2.3.

Figure 2.3: System sketch of the solution when using a CPU without native support for PCI Express.

The IC is used as an endpoint device to establish a link with the root-complex. It includes a Serializer/Deserializer (SerDes), consisting of a Parallel In Serial Out (PISO) block and a Serial In Parallel Out (SIPO) block. The block converts data from a serial to a parallel interface in both directions. The use of a PCI Express PHY bridge greatly improves the assortment of available CPUs as the existing layers within the PCIe standard are software based. However, there are a limited amount of PHY bridges and the available options from the researched manufacturers are currently limited to PCI Express Gen 1. The summary of the pros and cons of this system is presented below.

Pros Cons - Easy to exchange physical layer - Requires PCI Express to PHY IC to operate in endpoint mode - Need to implement DLL and TL - Not possible to upgrade physical layer if manufacturers stop produce new solutions.

7 2.2. Possible solutions

Programmable logic Programmable logic, such as FPGAs are commonly used for high-speed applications and computation acceleration. Many manufacturers offer value-line and low-power FPGAs that are suited for digital processing. The system sketch when using a FPGA is shown in Fig. 4.3.

Figure 2.4: System sketch of the solution when using a FPGA.

One benefit of using a FPGA is that they usually feature a large amount (100+) of GPIOs and the majority of them support differential termination options as well as single ended termination. Some FPGAs also feature full hardware support for all PCI Express layers and are able to behave as endpoints. Due to their nature, a FPGA without hardware PCI Express support can be programmed to support it. The requirement is that they are able to communicate at PCI Express speeds, for example with the help of a transceiver. The transceiver are used in conjunction with Intellectual Property (IP) cores that implement the higher layers. While such a solution is highly configurable, it is at the expense of logic elements in the FPGA. The boot times are determined by the FPGA configuration size as well as the programming interface speed. As a result, many smaller FPGAs are able to boot faster than the 100 ms start up time criterion described by the PCI Express Base Specification[1]. Since FPGAs are usually programmed to perform very specific tasks, low and predictable latency is achievable in a FPGA-based system as well as high throughput. Both of these aspects are desirable since the bridge should allow the root complex to communicate with multiple LVDS/CMOS interfaces at high speeds. The main benefit compared to other solutions is that FPGAs can be programmed to support almost any interface. However, FPGAs lack the rich set of peripherals or software implementation of the interfaces. One design consideration when using a FPGA is that a Non- Volatile Storage (NVS) is required for storing the configuration. Another important consideration is that since the operating principle of FPGAs is quite a bit different from MPUs and CPUs, the programming also differs a lot. FPGAs are commonly programmed using Hardware Description Languages (HDLs) such as Verilog or Very High Speed Integrated Circuit HDL (VHDL), both languages differ a lot from sequential programming languages. The summary of the pros and cons of this system is presented below.

Pros Cons - High number of GPIOs. - Requires external memory. - Fast boot time. - Less intuitive programming. - Many manufacturers provide fully functional PCI Express IP cores. - Low latency and high throughput. - Capable of supporting different types of interfaces.

8 2.2. Possible solutions

Conclusion Based on the previous analysis, a few key points can be made to rule out the different solutions: CPUs: Powerful, but are unnecessarily complex and may have long boot times. The lack of connectivity options also makes this solution poorly suited for the design. Another drawback is the lack of endpoint-capable CPUs, severely limiting the selection of possible hardware. CPUs without endpoint support suffer from the same drawbacks, with the addition of relying on external PHYs. In short, none of the two CPU solutions are suitable for the application. Programmable logic: Programmable logic such as FPGAs may not be as intuitive for developers who are accustomed to CPU development, they do have a lot of features desired in the application. FPGAs are commonly used in endpoint conﬁguration and many manufacturers offer endpoint IP cores. The requirement of an external memory is compensated for by the large amount of connectivity options of a FPGA. With consideration to the information gathered in this prestudy, it was decided that the bridge should be implemented using a FPGA.

9 3 Selection of hardware

Multiple manufacturers and product lines were compared to ﬁnd a suitable FPGA as well as peripheral components. This section will discuss the process of ﬁnding, comparing and choosing the different hardware.

3.1 FPGA selection

In order to ﬁnd the best-suited FPGA for the design, several product series from multiple manufacturers were compared. Four FPGA manufacturers were considered: Intel (previously knows as Altera), Lattice semiconductor, Microsemi and Xilinx. Initially, the different product series were investigated and later speciﬁc device packages. In order to qualify as a possible candidate for the initial selection, the product series should feature support for at least PCI Express Gen 1 x2. A list of candidates was compiled and is presented in Table 3.1.

Table 3.1: Product series candidates.

Manufacturer Product family Intel Cyclone IV Intel Cyclone 10 Intel Arria V GX/GZ Intel Stratix V GX Lattice ECP2 Lattice ECP3 Lattice ECP5/ECP5-5G Microsemi IGLOO2 Microsemi SmartFusion 2 Xilinx Spartan-6 Xilinx Artix-7 Xilinx Kintex-7 Xilinx Virtex-7 XT Xilinx Kintex Ultrascale Plus Xilinx Virtex Ultrascale Plus

10 3.1. FPGA selection

Product family The device selection process focused on three main aspects: the amount of transceivers, the number of logic elements (LE’s) and the device speed grade. Transceivers are high-speed serial/parallel interfaces that operate at a higher frequency than the FPGA fabric. They are essential for PCI Express communications since the fabric itself is usually not capable of han- dling PCI Express speeds. The device used must have at least two transceiver channels and if the package is a ball grid array (BGA), it should have a ball pitch equal or larger than 0.8 mm. The reason is that while a smaller pitch device features more pins in a smaller package, the design tolerances become stricter which in turn increases the PCB production cost. The number of LE’s determines how much application logic can be implemented on the FPGA. PCI Express IP cores usually take a portion of the logic cells, depending on the manufacturer so they need to be taken into consideration1. For some manufacturers, speed grade limits performance. Components need to have a speed grade high enough to support PCI Express in order to qualify for the selection. A list was compiled with possible candidates that fulﬁlled the requirements. The complete list is presented in Appendix A, Table 3.2 shows a summary of the list.

Table 3.2: Selected devices from the different product families.

Product family Device code Footprint LE’s Transceivers Cyclone IV[6] EP4CGX30CF19C8N F324 30k 6 Cyclone 10 GX[7] 10CX085YU484I6G U484 85k 6 10CX220YF780E5G F780 220k 12 Arria V GX[8] 5AGXMA5G4F35C4G F672 75k 9 Arria V GZ[8] 5AGZME1E3H29C4N H780 220k 12 Stratix V GX[9] 5SGXMA3E3H29C4N F780 340k 12 ECP2[10] LFE2M20E-5FN256C F256 19k 4 ECP3[11] LFE3-17EA-6FTN256C ftBGA256 17k 4 ECP5[11] LFE5UM-25F-8BG381C csBGA381 25k 2 LFE5UM-45F-8BG381C csBGA381 45k 4 ECP5-5G[11] LFE5UM5G-25F-8BG381C csBGA381 25k 2 LFE5UM5G-45F-8BG381C csBGA381 45k 4 IGLOO2[12] M2GL010T-1VF400 VF400 12k 4 M2GL025T-1VF400 VF400 25k 4 SmartFusion2[13] M2S010T-1VF400 VF400 12k 4 Spartan-6[14] XC6SLX25T-N3CSG324C CSG324 24k 2 Artix-7[15] XC7A12T-2CSG325 CSG325 13k 2 XC7A15T-2CSG325 CSG325 16k 4 XC7A25T-2CSG325 CSG325 25k 4 XC7A100T-1FGG484 FGG484 101k 4 Kintex-7[15] XC7K70T-1FBG484 FBG484 65k 4 Virtex-7 XT[15] XC7VX330T-1FFG1157C FFG1157 326k 20

Device selection The initial seperation was done by putting a price cap at 100 USD/Unit. The limit was chosen since the ﬁnal design should be as cheap as possible. Any FPGA that was more expensive usually featured higher performance than what was necessary or had poor price-performance ratio. This removed all Intel devices except the Cyclone IV and all Kintex/Virtex devices.

1Each manufacturer provides a separate PCI Express IP Core, Intel and Microsemi implements the core in hard logic so no resources are required[2][3], Lattice requires 12-16k LUTs[4], Xilinx requires 1k LUTs[5, p.10-11].

11 3.1. FPGA selection

Secondly, devices were removed if they were larger than 22x22 mm since they would not ﬁt on the PCB. Older-generation devices such as the Lattice ECP3, Intel Cyclone IV and Xilinx Spartan 6 were also removed. The reason was that the newer generations are about as expensive but featured more modern hardware. The remaining product series were the Lattice ECP5/ECP5-5G, Xilinx Artix-7 and Microsemi IGLOO2/Smartfusion 2. The ECP5 device was removed since it only supports PCI Express gen 1. The Smartfusion 2 device was removed because it is essentially the same device as the IGLOO2 but with an integrated microcontroller which was not needed. In order to compare the remaining devices, an assumption was made that the bridge would require at most 10K Logic elements (not including the PCI Express interface). Choos- ing the smallest possible device from each family, the choice is narrowed down to three devices:

Device Unit price [USD] Lattice LFEUM-25F-8BGC381C 19 Microsemi M2GL010T-1VF400 37 Xilinx XC7A12T-2CSG325 36

The Lattice device stands out from the rest since it is signiﬁcantly cheaper compared to the other devices. However, the ECP5-5G family requires a software license for both the IDE and the PCI express IP Core. The IDE cost 895 USD/year and the IP Core is a one-time cost of 1800 USD. It also requires an external PLL for its transceivers, adding around 4 USD to the unit price. The Xilinx and Microsemi both require no license for the IDE or PCI Express IP Core. Figure 3.1 shows the accumulated price for each of the devices. The comparison assumes 100 units/year, meaning that any yearly licence is required every 100 units.

Figure 3.1: Total accumulated price for N number of units, assuming 100 units/year.

As seen in Fig. 3.1, the price break between the Lattice and Microsemi devices are at about 500-600 units. The Xilinx device has a marginally lower cost/device when compared to the others. Since the price difference was so small, any of the devices was a good choice for the design. To be able to make a decision, another aspect had to be taken into account. The Xilinx Artix-7 XC7A12T-2CSG325 was considered the best candidate. The reason is that the developers where the master’s thesis is carried out all use Xilinx FPGAs, meaning that there is a great knowledge base for both hardware and software. The device naming parameters can be split-up to describe the features of the unit. The name indicates that it

12 3.2. Non-volatile memory selection is an Artix-7 Series FPGA with 12K LUTs, speed grade 2 and package type C325 [15, p.16]. It is Xilinx smallest Artix-7 FPGA but features the necessary components to accomplish the assignment. The C325 package is available in many conﬁgurations and is easily upgraded due to its pin compatibility with higher-end models of the same family. Speed grade 2 is required to communicate using PCI Express Gen 2.

3.2 Non-volatile memory selection

Since the FPGA fabric commonly consist of volatile memory, FPGAs are unable to retain their configuration when powered off. To resolve this problem, an external Non-volatile memory (NVM) is commonly used to store the configurations when power is lost. Other alternatives include loading the configuration from an external processor, or a hybrid of the two. For the bridge design, an external memory was used for loading the configuration. The reason is that the physical size of the design is restricted and a processor would not add any extra functionality other than the configuration loading. Flash memories are either NOR- or NAND-based. The techniques differ vastly in their operation. NOR flash provides sufficient addresses to map the entire memory range, which makes it possible to access random data within the memory. They feature quick read-times but have relatively high write and erase speeds. 100 % bit correctness is ensured, making them excellent to use in a code execution applications. NAND-flash has a high bit-failure and requires error correction to determine if the data is valid. The advantages of NAND-flash is high storage-density and low cost. They are therefore primarily used in applications where large capacity storage is required. The most reasonable flash technique to use as firmware storage in conjunction with an FPGA is, consequently, a NOR-flash. The flash memory parameters were chosen based on price, capacity, and footprint. MT25QL128 was a satisfactory choice since it features multiple storage sizes and a standard footprint. It communicates using SPI which is directly compatible with the FPGA. NOR-flash with the same pin-out and footprint are available with a capacity up to 256 Mb. The chosen Artix-7 with 12 kLUTs has a Bitstream size of 10 Mb while the 35 kLUTs has a size of 18 Mb [16, p.14] which will easily fit in the NVM. WISI Norden desired a small I2C EEPROM with device information, tied directly to the SMBus (I2C compatible) interface. The information on the EEPROM should include enough information for the main device to identify the PCI Express Bridge. AT24CXXD is a small and cheap EEPROM with 1-16 Kb capacity in a SOT23-5 package. It complied with the necessary requirements and featured a Write Enable (WE) pin, used to protect the user from accidentally overwriting the memory.

3.3 Regulator selection

The Artix-7 FPGA requires several different voltages to operate. It is usually achieved by a series of Switch Mode Power Supply (SMPS) or Low-dropout Regulator (LDO) ICs. SMPS are highly efﬁcient but induce electrical noise as a side effect. Low-dropout regulators are linear, which effectively means that they convert excessive power to heat by altering the resistance relative to the load. It results in an ineffective power regulator but provides a clean voltage to the load. Most voltage inputs of the FPGA are tolerant of the noise-levels produced by switching regulators. However, analog voltages related to the transceivers often require isolated and electrically clean power. SMPS are therefore mostly used when high currents are present or where the input to output voltage difference is high. An effective option to achieve clean, yet efﬁcient, power conversion is to use a switching regulator in series with an LDO. Typically, FPGAs require around 3-4 different voltages, with current draw varying greatly depending on FPGA size and application. It is, therefore, a demanding task to select a suit-

13 3.3. Regulator selection able voltage network which efﬁciently powers FPGAs. Since the current draw of the FPGA is directly related to the resources used in the user application, Xilinx provides a Power Esti- mator application. The application is used to calculate the estimated current draw based on resources selected by the user. The number of different voltages is related to the peripherals used within the device. For example, the transceiver channels require an isolated and stable source, while the core and other auxiliary circuits within the FPGA are more resistant to noise and voltage ﬂuctuations. The recommended voltage levels for the Artix-7 FPGA, along with their tolerances and estimated current consumption, is presented in Table 3.3.

Table 3.3: Artix-7 - Recommended DC and AC characteristics.

The following values were calculated using: PCI Express Gen 2, 1x2 conﬁguration, I/O Bank: 40 LVDS (2.5V) pairs @ 150 MHz, 100% LUT usage. Symbol Voltage [V] Current [mA] Tolerance Supply description ˘ VCCINT 1.0 600 3% [17] Internal power. VCCBRAM 1.0 4 - Block RAM. ˘ VMGTAVCC 1.0 200 10 mVpp [18, p.228] GTP transceivers. ˘ VCCAUX 1.8 100 5% [17] Auxiliary supply. ˘ VMGTAVTT 1.2 150 30 mVpp [17] GTP termination. VCCO_15 1.14 to 3.465 300 - HR I/O banks. VCCO_34 1.14 to 3.465 300 - HR I/O banks.

The current estimation is derived from Xilinx Power Estimator (XPE). The combination of high current consumption for the core and low noise requirements for the transceiver peripherals demands an effective yet ﬂexible power solution. To conform with the requirements, a combination of switching regulators and low dropout linear regulators were regarded as the best solution. The sensitive and low power transceiver peripherals (VMGTAVTT and VMGTAVCC) are supplied from LDOs which provides an electrically clean output, while the VCCINT and VCCAUX are supplied from the SMPS. To simplify the task of selecting a suitable power solution, mainly for FPGAs and processors, manufacturers have developed Power Management Inte- grated Circuits (PMICs). PMICs can refer to any IC which performs power conversion but generally, they are intended to include all of the necessary SMPS and LDOs within a single IC. A ﬁtting candidate is the TI LM26480, which is an IC consisting of two switching regulators and two low dropout linear regulators[19]. The key features of LM26480 are:

• Small footprint of 4x4 mm.

• Low Price.

• Hardware adjustable voltage levels on all regulators.

• Power good indicator.

• 2 MHz switching frequency, allowing the use of small external inductors and capacitors.

The voltage and current capabilities of the built-in regulators in the LM26480 can be seen in Table 3.4.

14 3.3. Regulator selection

Table 3.4: Texas Instruments LM26480 internal regulators.

Regulator type Output voltage [V] Current [A] Voltage drop Switching 0.8 to 2 1.5 - Switching 1 to 3.3 1.5 - Low Dropout 1 to 3.5 0.3 25 mV (typical) Low Dropout 1 to 3.5 0.3 25 mV (typical)

The I/O banks of the Artix-7 FPGA may be powered separately from each other. The idea is to power the I/O banks from their own LDO which provides the ability to handle multiple I/O standards. An example is to communicate with a 2.5 V interface on I/O bank 15 while I/O bank 34 runs on 3.3 V simultaneously, enabling the use of different I/O interface standards per bank. All LDOs suffers from a small dropout voltage, Vdrop, which means that the maximum ´ output voltage is limited to Vin Vdrop. This is problematic when a 3.3 V output standard is desired and Vout needs to equal Vin. However, Texas Instruments TLV758P solves this issue. ă ´ Once Vin (Vout Vdrop), it goes into a "dropout mode", where the output voltage tracks the input voltage. It features a small footprint, low price and acceptable output current of 300 mA, along with an adjustable output voltage which is conﬁgured through a voltage divider.

15 4 System Description

This chapter will present an overview of the bridge architecture. The goal is to provide the reader with an easy reference as to how each part of the bridge operates and integrates with other parts. The design is composed of many smaller systems that operate independently or alongside other systems. A rough sketch of an M.2-module with a possible layout of the systems is shown in Fig. 4.1. The complete schematic, layout, BOM and mounting guides are presented in Appendix B. Each system, left to right, will be presented in a separate section. In general, thicker lines represent buses or groups of signals and thinner lines represent single signals. Gray symbols represent physical parts, such as PCBs and components. Each internal pattern in Fig. 4.1 represents a separate system and the pattern for each section is consistent throughout the chapter. Note that power nets are only shown in the M.2 and Power management system sketches.

l M.2 connector, FPGA, a Programming and debugging interface, Power management, External connectors. Figure 4.1: System layout on the M.2 module.

4.1 M.2 Connector

The M.2 connector serves as the main interface with the platform. It is a ﬁnger-edge connector which provides both power and signaling to the bridge. The M.2 connector connects to the

16 4.2. FPGA

FPGA system, Power management system as well as the programming and debugging interface system as shown in Fig.4.2.

FPGA, a Programming and debugging interface, Power management.

Figure 4.2: M.2 connector system connections.

The PCI Express bus is the high-speed interface that is used for data exchange between the platform and bridge. It consists of two transmitting lanes, two receiving lanes and a clock lane. The PCI Express bus connects directly from the M.2 connector to the FPGA system. The platform provides a SMBus on the M.2 connector. Since the platform SMBus operates at 1.8 V logic level and the programming and debugging interface SMBus operates at 3.3 V logic level, a logic level converter is required. The converter needs to convert 1.8 V signals to 3.3 V and vice versa. The M.2 connector also provides 3.3 V power that is used to generate stable voltages for the bridge. The 3.3 V power from the card edge connector directly connects to the Power management system.

4.2 FPGA

The FPGA system interfaces with all other systems on the bridge. The main component of the system is the Artix-7 FPGA, which consists of several smaller parts such as transceivers and conﬁguration banks. This section will describe how the FPGA system interfaces with the other systems according to the diagram in Fig. 4.3. A more in-depth description of the Artix-7 and its parts is presented in chapter 5.

l M.2 connector, FPGA, a Programming and debugging interface, Power management, External connectors. Figure 4.3: FPGA system connections.

17 4.3. Programming and debugging

The SPI interface is used for loading new bitstreams to the FPGA. It is a 1x Synchronous Serial Interface (SSI), meaning it utilizes a single data channel in each direction. The bus connects to the Programming and debugging system along with the Done and Configure signals. The Done signal is used to verify that bitstreams successfully load into the FPGA and can be read over SMBus. The Configure signal triggers the loading of a new bitstream when pulsed low. The SET_IO_X_N bus is used by the FPGA to control the LDO which regulates bank voltage for the LVDS/CMOS I/O banks. This is done by pulling the signals low och putting the respective pins in High-Z mode. Chapter 5 describes the process in greater detail. The LVDS/CMOS bus consists of 10 differential signal pairs. Each pair may be reconﬁg- ured to function as two independent single-ended signals allowing for a maximum of 20 individually controllable signal pins. The LVDS/CMOS bus connects to the External connectors system.

4.3 Programming and debugging

For the programming interface, different paths for configuration were investigated. The first was to use the PCI Express interface in conjunction with a solution provided by Xilinx called PCI Express tandem. The solution was initially only named tandem and was designed to allow large bitstream devices to load the PCI Express core before loading the rest of the bitstream into the device. The entire bitstream is loaded in two stages from an external NVM and the idea was that the device should fulfill the 100 ms criterion set in the PCI Express specification. PCI Express tandem allows the user to load the first stage from a NVM and the second stage to be sent to the device over PCI Express. The solution appeared promising since there was a limited amount of interfaces on the M.2 connector and it would allow easy exchange of the bitstream in the device. Unfortunately, this solution is not available in all Artix-7 devices. The smallest device that supports it is the XC7A75T[5, p.157]. The solution was abandoned since the device is not available in the chosen package. The second path for configuration was the SMBus present on the M.2 connector. The interface is not fast enough to allow bitstream loading upon start up1 but it can be used to load new configurations to an on-board NVM. The FPGA can boot from the flash when it is powered on and if a different configuration is desired, it can be loaded into the NVM and the FPGA reloaded with the bitstream. The third path of configuration is a JTAG interface. It can be used not only for loading images to the FPGA and NVM, but also provides debugging functionality. The drawback of the interface is that it is not present on the M.2 connector meaning that it will be used mainly for debugging. Fig. 4.4 shows a sketch of signals present in the programming and debugging system. The SMBus connects to a ID NVM. The purpose is to provide a way of identifying the bridge, even if the system does not boot. It is connected directly to the SMBus with nothing between it and the M.2 connector in order to minimize the risk of failure. The NVM is write-protected and the protection can only be disabled by shorting a test pad on the PCB to ground. The SMBus is also connected to a SMBus to SPI converter. The SPI bus of the converter is connected to the Normally closed (NC) pins of a quad Single-pole, double throw (SPDT) analog switch. The Normally open (NO) pins of the SPDT is connected to the FPGA and the Common (COM) pins are connected to a NVM. In order to select what device is connected to the NVM, a GPIO on the converter is used to control the SPDT through the IN signal.

1SMBus @100 kHz requires 100+ seconds to load an entire XC7A12T bitstream of 10 Mb.

18 4.4. Power management

l M.2 connector, FPGA.

Figure 4.4: Programming and debugging system connections.

4.4 Power management

The power management system is shown in Fig. 4.5. The Power good signal indicates that all of the PMIC voltages are stable. When pulled low, the LDO and switch are enabled, powering the last sections of the bridge.

l M.2 connector, FPGA, a Programming and debugging interface.

Figure 4.5: Power management system connections.

Power tree The goal of using SMPS’s and LDOs in conjunction is to minimize the total power loss of the bridge, allowing it to run without active cooling. This section will present two possible hierarchies for the power supplies and discuss the differences between them.

19 4.4. Power management

The ﬁrst two voltage domains are the 1.0 V VCCINT/VCCBRAM and 1.8 V VCCAUX. All systems connected to these voltages are larger than 3 % tolerance to noise, as seen in Table 3.3, meaning they can be sourced from the SMPS in the PMIC. In Fig. 4.6, these are represented by regulator 1 and 2. Since the transceivers in the Artix-7 are sensitive to noise, it is preferable to use LDOs for their voltage feeds, VMGTAVCC and VMGTAVTT. The two LDOs present in the PMIC will be used, represented by regulator 3 and 4 in Fig. 4.6. Note that regulator 5 is omitted from the power loss calculations. This is partly because it is a separate regulator, but also because the current and voltage for the I/O banks may vary greatly depending on the standard used as well as the speed and number of pins. The power hierarchy is illustrated in Fig. 4.6a and 4.6b.

(a) Option A, VMGTAVCC and VMGTAVTT sourced (b) Option B, VMGTAVCC and VMGTAVTT from 1.8V. sourced from 3.3 V.

Figure 4.6: Power hierarchy option considered in the design.

Option A and B in Fig. 4.6 mainly differ in the amount of power wasted during operation. An overview of the power loss and current within the LM26480 is presented in Table 4.1 and 4.2. The SMPS regulator efficiency was chosen as 80 % to simulate a worst-case scenario and to provide some headroom if the current draw estimations are inaccurate. Typically, the efficiency should be between 85-90 % for SMPS’s. For LDOs, Iin is the same as Iout. Rewriting the formula for efficiency, E f f , in (4.1), the efficiency of an LDO is given by Vout/Vin.

Vout ¨ Iout E f f = ¨ (4.1) Vin Iin

For SMPS’s, Iin is given by rewriting (4.1) to (4.2):

Vout ¨ Iout Iin = ¨ (4.2) Vin E f f

Since Iin, Iout, Vin and Vout are now known for each regulator, the power loss can be calculated using the expected current draw presented in Table 3.3:

´ ¨ ´ ¨ Ploss = Pin Pout = Iin Vin Iout Vout (4.3) Using (4.1) to (4.3), all currents, power losses and the total power loss can be calculated for each of the two options presented in Fig. 4.6. The results for option A and B are presented in Table 4.1 and 4.2, respectively.

20 4.5. External connectors

Regulator 1 Regulator 2 Regulator 3 Regulator 4 Total Type SMPS SMPS LDO LDO - Vin [V] 3.3 3.3 1.8 1.8 - Vout [V] 1.0 1.8 1.0 1.2 - Iin [A] 0.23 0.31 0.20 0.15 1.14 Iout [A] 0.6 0.45 0.20 0.15 - Efﬁciency [%] 80 80 56 67 - Ploss [W] 0.15 0.20 0.16 0.09 0.60

Table 4.1: Current ﬂow and power loss in hierarchy option A.

Regulator 1 Regulator 2 Regulator 3 Regulator 4 Total Type SMPS SMPS LDO LDO - Vin [V] 3.3 3.3 3.3 3.3 - Vout [V] 1.0 1.8 1.0 1.2 - Iin [A] 0.23 0.07 0.20 0.15 1.25 Iout [A] 0.6 0.1 0.20 0.15 - Efﬁciency [%] 80 80 30 32 - Ploss [W] 0.15 0.05 0.46 0.32 0.97

Table 4.2: Current ﬂow and power loss in hierarchy option B.

As seen in Tables 4.1 and 4.2, option A is the best when considering power loss. The hierarchy was simulated using Texas Instruments Tina-TI and the provided model for the LM26480. During simulation, the LDO appeared to reverse feed the SMPS, causing unpredictable be- haviour. Since the design should work and it was unknown if the problem was caused by the simulation model, the ﬁnal design will include an option that allows switching between the two hierarchies using 0 ohm resistor.

4.5 External connectors

The bridge has two sets of external connectors, each connected to a group of differential pairs as shown in Fig. 4.7. All pairs connect to the FPGA system. The external connectors also feature mounting pads for external termination at the connector since testing equipment may not be terminated correctly.

FPGA Figure 4.7: M.2 connector system connections.

21 5 Hardware design and implementation

This chapter will present the ideas and considerations during the design process of the bridge.

5.1 Stackup and design rules

JLCPCB was chosen for manufacturing the PCB. While they may not have as many options as other manufacturers in their PCB stackup, they simplify the design process by providing tools for calculating line impedance both for single-ended and differential traces for all of their stackups. In order to ensure that the PCB can be produced, the design has to follow the manufacturers rules and use a stackup that JLCPCB can produce. This section will present the stackup and rules that were used for the design.

Stackup The design uses the JLCPCB 0.8 mm JLC7628 stackup shown in Table 5.1. While the manufacturer offers other stackups with higher Dielectric constant and thinner prepregs, JLC7628 was chosen due to its thin core, which increases the inter-plane capacitance between the two inner planes where the majority of the ground and power planes are located. The trade- off is a poorer coupling between the outer and inner layers, slightly increasing the width of impedance matched traces.

22 5.1. Stackup and design rules

Table 5.1: JLC7628 layer stackup.

Layer Material type Thickness (mm) Dielectric constant Top solder mask Solder mask 0.0127-0.0203 3.8 Top copper Copper 0.035 Prepreg 7628 0.2 4.6 Inner copper 1 Copper 0.0175 Core 0.265 Inner copper 2 Copper 0.0175 Prepreg 7628 0.2 4.6 Bottom copper Copper 0.035 Bottom solder mask Solder mask 0.0127-0.0203 3.8

Design rules The rules that were used in the design are presented in Table 5.2. The majority are the recommendations from the manufacturer, with the exception of the rules related to differential pairs. The Differential trace width and Differential pair gap was calculated using the manufacturers online tool, all differential lines on the PCB are designed for a nominal differential impedance of 100 Ohm. The Length difference within pair rule was chosen small because the line-to-line skew directly inﬂuences signal integrity. While perfect length matching is desirable, it is not always possible due to manufacturing defects, etc. The designer should strive for perfect length matching, but realize that minor differences are negligible. Another important note is that any differences that appear as a result of turns or connections should be ﬁxed as close to the source of the difference as possible, as shown by point I in Fig. 5.1. The reason is that the noise rejection of differential signals is best when the two signals are in phase. The Copper-Differential pair clearance rule ensures that the high speed differential pairs have proper signal integrity. As a rule of thumb, a clearance larger than 2 times the pair gap should be used to ensure that the coupling to nearby copper is negligible. The design has a 3 times larger clearance compared to the gap.

[A] Via hole size [B] Via annular [C] Copper-Differential pair clearance [D] Differential trace width [E] Differential trace gap [F] Copper-Copper clearance [G] Routing trace width [H] Solder mask sliver [I] Length difference within pair

Figure 5.1: Illustration of design rules used during layout.

23 5.2. M.2 connector

Table 5.2: Routing rules used during the design of the bridge.

mil mm Rule min nom max min nom max Clearance Copper-Differential pair 12 - - 0.3 - - Copper-Copper 4 - - 0.1 - - Trace width Routing trace 4 6 - 0.1 0.15 - Vias Via hole size 8 16 - 0.2 0.4 - Via annular size 18 31 - 0.45 0.8 - Differential pairs Trace gap 4 4.5 5 0.1 0.114 0.127 Trace width 4.96 5.54 6.05 0.126 0.141 0.154 Length difference - - 5 - - 0.127 within pair Solder mask Sliver 4 - - 0.1 - -

5.2 M.2 connector

As discussed earlier, the SMBus logic level of the platform is lower than the logic level of the programming interface so a level converter must be used. Since SMBus operates on an open- drain conﬁguration1, the circuit in Fig. 5.2 can be used for the conversion. The solution was used since it required a small number of components, resulting in a small overall footprint.

Figure 5.2: Open-drain logic level conversion. HV indicates High (3.3 V) logic level, LV indicates low (1.8 V) logic level.

Layout The main consideration during layout was to keep the high-speed traces isolated from other signals such as the SMBus as well as any other high-speed signals in order to maintain signal integrity. For the PCI Express signals, the metal directly below the signals is a ground plane as seen in Fig.5.3. Vias were also added in close proximity to layer changes of the signals to provide a good return path for the signal. Additionally, fencing vias were added around the traces where possible to further shield the high speed signals.

1In an open-drain conﬁguration, the signal is driven low and pulled high through a resistor.

24 5.3. FPGA conﬁguration banks

Figure 5.3: Layout surrounding the M.2 connector on the top layer of the PCB. Notice the fencing and return path vias as well as the ground plane (yellow) on the layer below the PCI Express lanes.

5.3 FPGA conﬁguration banks

The conﬁguration banks refer to Bank 0 and 14 in the Artix-7. These banks are used for conﬁguration of the FPGA as well as setting the voltage levels for the I/O banks. The JTAG interface on Bank 0 is used for debugging and loading new bitstreams to the NVM through the SPI interface. This interface has a separate connector on the PCB and is not connected to the M.2 connector. The SPI interface is used for loading bitstreams from the NVM. The default interface is set through the Mx pins on Bank 0. In the design, M[2..0]= 001, corresponding to Master SPI[16, p.21]. This interface is used at power-on, but may be overridden by the JTAG interface. Three IOs on Bank 14 are used to control the voltage level of the remaining I/O banks. This is achieved by altering the feedback loop of an LDO by pulling the respective IOs low or putting them in a high-Z state. This is described in greater detail in section 5.6.

Layout Since most of the configuration pins on the Artix-7 have fixed positions in the pinout, the main consideration was to avoid layer changes as much as possible. Examples of how the nets were fanned out under the Artix-7 are shown in Fig. 5.4. The LDO control pins that had no fixed position were moved close to the LDO to make routing easier.

Figure 5.4: Fanout of the SPI and JTAG nets (highlighted) under the Artix-7.

25 5.4. FPGA I/O banks

5.4 FPGA I/O banks

The I/O banks refer to Bank 15 and 34 in the Artix-7. These banks are both connected to the LVDS/CMOS connectors. Each bank has 10 pins available at the connector that may be used as either 10 single-ended pins or 5 differential pairs. Due to space constraints, one of the pairs on Bank 34 was only routed to a terminating resistor close to the Artix-7.

Layout All pairs were routed and pairwise length-matched within 0.127 mm (5 mil) with a nominal differential impedance of 100 Ohm. The clearance between pairs was kept to a minimum of 3 times the spacing within a pair to reduce cross-talk.

5.5 FPGA transceivers and PCI Express nets

The PCI Express lanes 0 and 1 of the M.2 connector were connected to the transceivers of the Artix-7. To simplify the routing, lane 0 was connected to transceiver 1 and lane 1 to transceiver 0. To reduce the complexity and number of external components of the system, the PCI Express reference clock will not only be used for the transceivers, but also to clock the core logic of the FPGA. For the PCI Express lanes, the PCI Express Base speciﬁcation states that any transmitting element should have AC coupling capacitors in the range 75 ´ 265 nF for 5 GT/s applications[1, p.357]. 100 nF capacitors were added to the TX and CLK lanes.

Layout Since the PCI Express lanes and reference clock are both differential signals, special consideration must be taken to their relative length. The most important consideration is the difference between the positive and negative signal inside a lane, since it directly inﬂuences signal integrity. The largest allowed lane-to-lane skew is 1.3 ns for TX and 8 ns for RX when UI is the nominal unit interval 200 ps[p.357,p.378,p.380][1]. Assuming a phase velocity of 0.67 c, this corresponds to 18/160 cm for TX/RX, respectively. TX lanes are completely independent from RX lanes, so they need not be matched. The characteristic impedance for all lanes are 80-120 Ohm according to the PCI Express base speciﬁcation[1, p.355, p.379]. During layout, pairs were designed to the nominal differential impedance 100 Ohm.

5.6 Power management

The Artix-7 datasheet provides the optimal power-on sequence[20, p.8] to minimize current consumption. Turn-on sequencing of the regulators was, therefore, added to minimize FPGA start-up current draw. The sequencing was accomplished by RC networks connected to the regulator enable pins, seen in Fig. 5.5, where the delay is determined by the rise-time of the supply voltage, calculated using (5.1). The optimal turn-on sequence is shown beside the designed turn-on sequence in table 5.3.

τr = R ¨ C (5.1)

26 5.6. Power management

Table 5.3: Optimum and designed power-on sequence for the different power nets.

Optimum Design 1 VCCINT VCCINT, VCCBRAM 2 VMGTAVCC VCCAUX 3 VGTAVTT VMGTAVCC 4 VCCBRAM VGTAVTT 5 VCCAUX VCCO 6 VCCO

The designed sequence does not follow the optimum sequence but intends to solve the most critical parts which are the transceiver analog supply voltage, VMGTAVCC, and its termination voltage, VMGTAVTT.

Figure 5.5: Power-on sequencing using RC networks.

The nPOR pin of the PMIC is a power-good indicator. It is driven low when either of the buck regulators is below 92 % of their desired output voltage. When the output is considered stable, there is a 60 ms delay until nPOR is pulled high. The power-good signal is used to enable the two FPGA I/O bank voltages through an N-MOS transistor and an enable signal, illustrated in Fig. 5.6.

27 5.6. Power management

Figure 5.6: I/O voltage sequencing and selectable I/O voltage solution.

I/O voltage regulation FPGA I/O voltage is regulated by a stand-alone adjustable LDO. The adjustability is achieved using software controlled feedback networks, illustrated in Fig. 5.6. The voltage of the I/O regulator is controlled by resistor dividers, where the voltage is calculated using (5.2).

R1 V = V ¨ (1 + ), V = 0.55 (5.2) out,LDO re f R2 re f The divider network essentially alters the R2 value. Since the GPIOs are tri-state capable, a single resistor divider can be selected by setting one output to LOW while the rest are high impedance (High-Z), resulting in the pattern described in Table 5.4.

Table 5.4: Regulator SET_IO state to voltage relation.

SET_IO_1V8_N SET_IO_2V5_N SET_IO_3V3_N VCCO_15_34_ADJ [V] High-Z High-Z High-Z 1.2 High-Z High-Z LOW 1.8 High-Z LOW High-Z 2.5 LOW High-Z High-Z 3.3

Passive components The PMIC circuit and selection of external components was based on the Typical Application design provided in its datasheet. The datasheet also presents a formula for calculating the output voltages of the four individually controlled regulators, seen in (5.3) [21].

R2 V = V ¨ , V = 0.5 (5.3) out re f R1 + R2 re f External components were selected to suit the output voltages and their approximated current draw. Special consideration were taken into capacitor DC-bias and inductor current saturation. The ripple and peak currents of the SMPS are highly dependent on the output

28 5.6. Power management

ﬁltering components. Equations (5.4)-(5.8) are provided by TI[21, p.27]. They allow the designer to predict the current and voltage ripple based on ﬁltering components selection, expected current draw and switch frequency. Table 5.5 shows the current ripple that can be presumed for the design.

Iripple I = I + (5.4) L,peak out,max 2 ´ Vout ¨ Vin Vout Iripple = ¨ ¨ (5.5) Vin η L F

Iripple VCout = (5.6) 8 ¨ F ¨ Cout ¨ VRout = Iripple ESRCout (5.7)

2 2 Vout,p´p = bVCout + VRout (5.8)

Table 5.5: Calculated values for Peak Current through the inductor and voltage ripple on the output, using: Vin = 3.3V, η = 0.85, Iout,max = 0.8A, Cout = 10µF, L = 2.2µH, f = 2MHz.

ESR [Ω] Parameter Condition Cout Unit 0.1 0.05 0.01 Vout = 1.0V 0.89 IL,peak A Vout = 1.2V 0.90 Vout = 1.0V 18.67 9.39 2.20 Vout mV Vout = 1.2V 20.46 10.29 2.41

Another aspect that was considered was the effect of DC-bias on the capacitors in the system. DC-bias causes the capacitance of a capacitor to decline. The extent of the effect varies greatly between different types of capacitors but a ceramic X5R capacitor usually has a curve similar to Fig. 5.7[22]. The main difference is where the capacitance starts declining rapidly, this is not necessarily related to the voltage rating of the capacitor. To reduce the overall amount of different components in the system, any capacitor used in the design had to maintain at least 90 % of its nominal capacitance at 3.3 V. This makes it possible to use the same value capacitors anywhere in the design.

Figure 5.7: Characteristic change of capacitance according to DC-voltage.

The Equivalent Series Resistance (ESR) of the capacitors was also examined. However, since all capacitors were of relatively small capacitance, ceramic capacitors with naturally low ESR were selected. The ESR could, consequently, be neglected in this application.

29 5.7. Programming and debugging interface

Layout The four copper layers of the PCB were divided into multiple sections to distribute the voltages efﬁciently. Power pins of the FPGA with the same voltage are often grouped together in the footprint, illustrated in Fig. 5.8.

VCCINT, VMGTAVTT, VMGTAVCC, VCCO, VCCBRAM, VCCAUX, GND b Bank 0, b Bank 14, b Bank 15, b Bank 34, b Bank 216 (Transceivers)

Figure 5.8: Artix-7 FPGA power pin mapping.

A suitable solution was to form a number of voltage planes conﬁned in the inner layers of the PCB. Sections where a speciﬁc voltage was frequently used, were made larger to max- imize inter-plane capacitance to adjacent ground planes. Vias connect the inner and outer layers together to distribute the power between connectors and components. Ground planes on multiple layers provide a low impedance connection to the regulator. The layout of the PMIC and the LDO originates from the Layout Examples provided by TI [23][21].

5.7 Programming and debugging interface

There are two parts tied to the programming interface. Firstly, JTAG, which is connected directly to the programming pins of the FPGA. It is used for conﬁguration as well as debugging. Secondly, the SMBus interface, which is used to program the NVM through a SMBus to SPI bridge. Upon start-up of the FPGA, it reads the NVM and loads the stored bitstream into its volatile memory. It was desired to have the possibility to program the memory through the SMBus, so that the bridge bitstream may be updated through the platform it is connected to.

30 5.8. Decoupling

Layout The components of the programming interface that were connected to the SMBus were placed close to the M.2 connector together with the SMBus level converter, marked by the orange box in Fig 5.9. The ﬂash memory, SPDT and JTAG connector were all placed close to the FPGA to reduce the routing complexity, marked by a red box.

Figure 5.9: Programming and debugging interface with related components marked.

5.8 Decoupling

In order to ensure that the design operates as expected, proper decoupling is required. The decoupling network consists of capacitors and provides a temporary energy reservoir during current surges. A general rule of thumb when designing decoupling networks is to place smaller value capacitors closer to the circuit and to increase the amount when the capacitance decreases (the amount of capacitors is usually doubled when the capacitance is decreased by a factor 10). Xilinx provides recommendations for decoupling networks when designing with their FPGAs. The amount of capacitors depend on the footprint and number of LUTs. The design should be compatible with devices as dense as XC7A35T, the footprint is however considered constant since a change in footprint would require redesigning the PCB. The PCB was designed to accommodate the XC7A35T since the XC7A12T requires less decoupling and any extra components can be omitted during mouting.

Table 5.6: Artix-7 Decoupling network for XC7A12T and XC7A35T

The recommended decoupling networks for 80 % of LUTs and registers at 245 MHz, 80 % block RAM and DSP at 491 MHz, 50 % MMCM and 25 % PLL at 500 MHz, 100 % I/O at SSTL 1.2/1.35 at 1,200/800 MHz[24, p.15-16]. V V V V V CCO CCO CCINT CCBRAM CCAUX Bank 0 (Others, per bank) Capacitance, 100 4.7 0.47 47 0.47 47 4.7 0.47 47 47 4.7 0.47 uF XC7A12T 1 1 2 1 1 1 1 2 1 1 2 4 XC7A35T 1 2 3 1 1 1 2 3 1 1 2 4

The PCB Design Guidelines also state that banks that share a common voltage feed may also share bulk (47 uF) capacitor[24, p.15, note 3]. This reduces the total amount since the I/O banks share feed. In order to reduce the amount of different components, all 47 uF capacitors

31 5.8. Decoupling were replaced with 100 uF since changing the bulk capacitor to a larger value should not affect the performance notably. The VMGTAVCC and VMGTAVTT supplies are described in a separate guide targeted speciﬁ- cally at the GTP transceivers. Xilinx recommend using one 4.7 uF and two 0.1 uF 10 % ceramic capacitors for power supply ﬁltering for each of the supplies[18, p.230].

Layout The main consideration during layout of the decoupling network was that small value capacitors should have a low-impedance connection to its related power pin. This was achieved by moving the capacitors under the FPGA and having a dedicated set of vias for each capacitor. The latter consideration may not seem like it would matter much, but sharing vias between several capacitors increases the impedance of the path. It generally considered bad practice for high frequency designs.

32 6 Manufacturing

Manufacturing is a key phase of this degree project. In this chapter, main aspects of this process are presented and discussed. They will cover the manufacturing and testing of the PCB, as well as the electrical interfaces.

6.1 Bill of materials

A Bill of Materials (BOM) is a list of components used to manufacture a product. The list includes the necessary data to correctly designate every part in a project, which involve designator, value and part number. The most convenient solution to successfully generate the BOM is to supply every component with the required information and let the PCB CAD software compile it automatically.

6.2 Assembly and soldering

The first prototypes were assembled and soldered at Linköping University. A solder stencil was used in combination with solder paste to deploy a thin layer onto the pads of the PCB. The components were placed on the PCB and solder in a soldering oven. During assembly, the XC7A12T was exchanged for a larger variant, XC7A35T. The devices are pin-compatible and the larger device was used to ensure that there was enough configuration space. In the final design, the bridge may be fitted with whatever device fits the implementation bitstream.

6.3 Tests and inspection

During and after assembly, the board had to be tested to verify that all components func- tioned as expected. A test plan was created in order to ensure that no important functionality remained untested. Since every design is different, the test plan is usually tailored to the design. The test plan used is presented in Appendix C. This section will discuss the tests, with focus on tests that were skipped or failed.

33 6.3. Tests and inspection

Pre-component mounting It was to no surprise that the PCB passed all 1.1.x tests since the manufacturer tests the PCB using a ﬂying-probe technique. The trace impedance test was skipped since it required more advanced measuring equipment than what was at hand during testing.

Post-component mount The purpose of these tests was to verify that no nets had been shorted during component soldering and that the regulators would present the correct voltage when power is applied to the board.

PCB under power These test were designed to verify that the design performed as expected when not configured. The current draw is measured to see if it is reasonable. An excessive current draw, over 1 A, could indicate that something is shorted or malfunctioning. Point 1.3.1 was passed with a standby current of around 86 mA. All voltages except VCCO_0_3V3 was within a couple mV of spec. The cause and solution of the deviation is described later in this section. A few problems were encountered during the tests. The first was that the sequencing was not as expected. Both bank voltages VCCO_0_3V3 and VCCO_14_35_ADJ briefly started at power- on, powering off after a few milliseconds. The cause was believed to be the nPOR signal being pulled high before the core logic in the PMIC had drawn it low. To remedy the problem, a shunt capacitor was added to the nPOR net, the charge time for the capacitor was long enough to hold the signal low until the PMIC could pull it low. The second problem was that VCCO_0_3V3 only reached about 2.5 V. The cause was that when the NMOS which lets power through to the net does not fully open since the source node reaches the same potential as the gate. The fix was to connect VCCO_0_3V3 directly to VCC_3V3. The drawback is that the power sequence is no longer correct, causing a slightly higher current draw at power on. The problem could also be fixed by using a load switch circuit, such as the one shown in Fig. 6.1. Such a solution would work as intended but requires more components. For testing, connecting VCCO_0_3V3 to V3V3 was considered adequate.

Figure 6.1: Load switch schematic

A third problem was that the four voltages sourced from the PMIC started simultaneously. The cause was most likely that the capacitors used for power sequencing charged to logic HIGH before the PMIC had started. Since the only consequence of powering on all nets at the same time is a higher current draw at power on, no action was taken to correct the problem.

34 6.3. Tests and inspection

In order to improve the power sequencing in future designs, a power sequencer could be used. The drawback is that the design becomes more complex and requires more components.

FPGA system These tests aimed to verify that all important signal connections to the FPGA had been properly soldered. Note that this section does not cover the PCI Express nets, as they were tested separately. The JTAG connectivity was veriﬁed by connecting a debugger and seeing that the device appears in the debug environment. To verify that all LVDS/CMOS pins were connected to their respective pins, a shift register was implemented in VHDL. By connecting the shift register to the pins and sending a single ’1’ through it, all pins could be set high one at the time. By measuring the voltage at the LVDS/CMOS header, it was possible to verify that all pins were properly isolated and connected. To verify the LDO voltage level control, each state of the conﬁguration presented in Ta- ble 5.4 was tested. All 2.1.x points were passed.

SMBus For the SMBus tests, a SMBus master was connected to the 3.3 V side of the level converter. The reason for not connecting it to the 1.8 V side was that the conversion had already been veriﬁed and the masters at hand during testing operated at 3.3 V. Point 2.2.1 and 2.2.3 were done by performing an enumeration of the SMBus and verifying that the devices were being properly enumerated. Both passed. Point 2.2.2 was tested by writing data to the EEPROM and reading it back. If the write and read data is identical, the point was passed. The same test was done the check point 2.2.5, the difference being that the communication to the FLASH memory is done through the SMBus-SPI bridge. 2.2.4 was veriﬁed by writing to the registers on the bridge that control the GPIOs and checking that they behave as expected.

PCI Express The PCI Express connection was verified by inserting the bridge in an M.2 connector and uploading the "AXI Memory mapped to PCI Express" IP core to the FPGA through JTAG. If the device was recognized by the operating system, the test was passed. Initially, the device did not appear in the OS, indicating that there was something wrong with either the IP core or the electrical connections. The PCI Express signals related to the reference clock were probed on both the bridge and a third party M.2 module that was known to function. It was immediately apparent that the reference clock was absent on the bridge. The fault was that the CLKREQ pin on the M.2 connector of the bridge had been left floating during design, when it should have been shorted to ground. The problem was corrected by soldering a jumper from the pin to an exposed ground pad on the bridge. After the fix, the reference clock appeared on the bridge and the platform was able to enumerate it properly. The differential reference clock signal that was measured on the bridge after the fix is shown in Fig. 6.2.

35 6.3. Tests and inspection

Figure 6.2: Reference clock differential signal measured on the bridge.

The Linux command lspci -vv was used to verify that the device had been enumerated by the system. The console output is displayed in Fig. 6.3, where the LnkSta ﬁeld shows that the link operates at 5 GT/s in an x2 conﬁguration.

Figure 6.3: PCI Express link lists the capabilities of the bridge.

36 7 Software

This chapter describes the developed software for each subsystem of the bridge. Each component requires a certain software coded in a certain programming language. These parts of the bridge must work together to deliver the desired functionality within speciﬁcations.

7.1 EEPROM memory veriﬁcation

The purpose of this software was to verify that the ID memory could be written and read back by a SMBus master. The software was developed mainly in Python targeted towards a Raspberry Pi. The code attempts to clear the memory and rewrite it with a text string. The memory is then read back to show if it was properly programmed. In order to program the ID memory, the write protect test pad in the design should be pulled to ground potential. The program ﬂow can be broken down to three major actions:

1. Clear ID Memory by writing ’0xFF’ to all memory addresses

2. While address is smaller than memory size and not at end of ﬁle:

• Send a packet of data to the memory • Increment address counter

3. Read back memory

If the write protect pin was pulled low, and the EEPROM functions as intended, the data that is read back should be the same as what was sent. If the write protect is not pulled low, the read back data will be whatever was present on the memory prior to the write. The console output following a successful write to the EEPROM is shown in Fig. 7.1.

37 7.2. Flash memory interfacing

Figure 7.1: Console output after a successful write to the EEPROM.

An interesting point, related to the functionality of the EEPROM is how it presents itself on the SMBus. Read/write operations on SMBus usually consist of two bytes, followed by the actual data that is to be sent to the device. The first byte is an address and read/write bit, telling the devices on the SMBus what device the master wants to interface with. The second byte is a command whose function is usually defined by the manufacturer and provided in the device-specific datasheet. In the case of the EEPROM, the second Byte is the address that the master wants to read from or write to. However, since it is a 4 kBit / 512 Byte memory it cannot be addressed using a single command Byte. Instead the memory presents itself at two addresses, one for each half of the memory. This is confirmed by running i2cdetect on the Raspberry Pi when the bridges SMBus is connected. i2cdetect attempts to write to all possible device addresses and displays the devices that respond, meaning that they are present on the bus. The result is shown in Fig. 7.2.

Figure 7.2: Enumeration of the SMBus of the bridge. Notice the SMBus-SPI bridge at ’0x28’ and the EEPROM at ’0x50’ and ’0x51’.

7.2 Flash memory interfacing

As with the ID Memory, the flash memory interface software is also written on a Raspberry Pi. The purpose of the software is to write an entire bit stream to the configurations memory over SMBus. As described earlier, the SMBus does not connect directly to the configuration

38 7.2. Flash memory interfacing memory. Instead, it communicates through a SMBus-to-SPI converter. The bridge introduces some limitations that need to be taken into consideration during read/write of the configuration memory. The first is that the bridge only has a buffer size of 256 bytes, limiting the amount of data that can be received before a transmission is required. The second limitation is that while the bridge has multiple signal pins that may be used as both chip select (CS) or as a GPIO, it required that at least one is configured as chip select in order for the bridge to transmit any data. The fact that the CS pin is automatically pulled low and high when transmitting data in conjunction with the small buffer size causes problems when interfacing with the configuration memory since it expects large (256+ bytes) packets.

Ideal transfer Ideally, the buffer size of the bridge would not influence the transfers. Commands and data transfers would be sent as complete packages, regardless of the size of the package. The signal for such a solution is displayed in Fig. 7.3. This solution would greatly decrease the complexity of the configuration procedure. However, since the bridge is limited by its fixed buffer size and the CS pin is automatically controlled, such a solution is only possible for sub-256 Byte packages. Note that the DONE signal is not used and should be configured as an input on the bridge. The SPI signal symbolizes that there is ongoing activity on the MISO, MOSI and CLK signals.

Figure 7.3: Ideal SPI data transfer.

1. IN pulled LOW, connecting bridge to conﬁguration memory.

2. CS pulled LOW, to indicate start of transfer.

3. The entire data package is sent over SPI interface.

4. CS pulled HIGH, indicating end of transfer.

5. IN pulled HIGH, reconnecting FPGA to conﬁguration memory.

6. (optional) Program_B pulsed LOW, loads new conﬁguration to FPGA.

Using the built-in CS pin The second solution would be to transfer data in smaller packets. This eliminates the problem of the buffer size but signiﬁcantly increases the amount of overhead needed for addressing and command declaration to the memory. The signal timing for such a solution is shown in Fig. 7.4. Note that package size is limited to a maximum of 256 bytes by the bridge, but may be further limited by SMBus buffer size in the SMBus master. Again, the DONE signal is unused and should be conﬁgured as an input on the bridge.

39 7.2. Flash memory interfacing

Figure 7.4: SPI data transfer using the built-in CS pin feature.

1. IN pulled LOW, connecting bridge to conﬁguration memory.

2. Data packages are transferred over SPI, with the CS pin going HIGH between packages.

3. IN pulled HIGH, reconnecting FPGA to conﬁguration memory.

4. (optional) Program_B pulsed LOW, loads new conﬁguration to FPGA.

Final solution The solution that was implemented was to use one of the other GPIO pins as a "dummy" CS, speciﬁcally the DONE signal. This solution strives to replicate the ideal transfer solution as closely as possible from a signal perspective. The signal timing is displayed in Fig. 7.5.

Figure 7.5: Final SPI data transfer implementation.

1. IN pulled LOW, connecting bridge to conﬁguration memory.

2. Program_B pulled LOW, unloading any conﬁguration from the FPGA.

3. CS pulled LOW, to indicate start of transfer.

4. Data packages are sent over SPI interface.

5. CS pulled HIGH, indicating end of transfer.

6. IN pulled HIGH, reconnecting FPGA to conﬁguration memory.

7. Program_B pulled HIGH, loads new conﬁguration to FPGA.

The DONE pin was a good candidate because it has a series resistor that limits any currents and it has no effect on the system when the Program_B signal is LOW. The real CS can then be configured as a GPIO, and controlled manually through software allowing much larger continuous transactions to the configuration memory. The drawback is that the FPGA loses its configuration when new bit streams are loaded into memory. This trade-off was considered acceptable since uploading a new bit stream to the configuration memory implies that the "old" configuration will no longer be used.

40 7.3. FPGA ﬁrmware

7.3 FPGA ﬁrmware

The VHDL developing environment used to create the FPGA firmware was Xilinx Vivado De- sign Suite HLx 2018.3. It features simulation, debugging and numerous Intellectual Property (IP) cores, which are pre-programmed blocks that may be used to accelerate development. A block design structure was used to create the firmware in VHDL. A simplified view of the block design is shown in Fig. 7.6

Figure 7.6: Overview of the VHDL block design.

AXI4 Protocol The AXI protocol is a part of ARM AMBA, which is a series of microcontroller bus standards initially introduced in 1996 and developed by ARM. AXI4 is the second version of the protocol and exist in three variations [25]:

• AXI4, High-performance memory mapped • AXI4-Lite, Simple, low throughput memory mapped • AXI4-Stream, High-speed data streaming

Xilinx adapted AXI4 when they introduced the Spartan-6 and Virtex-6 family devices as the preferred communication protocol between IP cores. The VHDL solution developed in this thesis uses a combination of AXI4 and AXI4-Lite interfaces. Each block that utilizes the AXI-bus gets a dedicated address span. The AXI protocol is used for point to point communication, from master to slave, with a focus on high performance. If it is desired to connect multiple slaves to a single master, or vice versa, an AXI interconnect can be used to separate the transmissions.

PCI Express The PCI Express functionality was implemented using the IP core AXI Memory Mapped to PCI Express. The core functions as an interface between PCI Express and AXI4. It translates the PCI Express transaction layer packets (TLPs) to AXI4 memory read and writes. Likewise, PCI Express memory read or write TLPs are translated to AXI4 interface commands [26]. Data is mapped to the platform memory using Block Address Registers (BARs). A BAR holds the address to the data of a particular VHDL block. The BAR contains the necessary information to accurately route the data from PCI Express to AXI4 through the address translation and ensures that the data ends up at the correct destination. The IP core has a series of inputs and outputs which has to be constrained to the physical ports of the FPGA associated with the M.2 PCI Express pins. Once the device is programmed and the platform device requests a PCI Express enumeration, the device’s PCI Express End- point functionality is detected. The correct conﬁguration (PCI Express Gen 2 x2), reported by the platform system, indicates that the link operates as anticipated.

41 7.3. FPGA ﬁrmware

Clock Buffers The PCI Express link requires a reference clock, provided through the M.2 as a part of the PCI Express standard. The clock signal originates from a differential source and needs additional buffers to bring the off-chip signals to the internal circuitry. A Utility Buffer IP is used to convert the differential inputs into a buffered single-ended clock signal. This signal can be connected directly to the reference clock input of the PCI Express IP.

Block RAM A block RAM (BRAM) is used to store data. It is part of the FPGA and has varying sizes between FPGAs. The purpose of the BRAM in this thesis is to act as a FIFO buffer. The BRAM is conﬁgured to have two ports, Port A and Port B. Both ports have access to the same data with individual clocks. The idea is to connect the writing interface to Port A, while Port B is used to read the data to the GPIOs. The data is loaded through the PCI Express to AXI4 link, on an address location speciﬁed by the user. The Block RAM is generated by the IP Block RAM Generator, which allocates a set amount of space and automates memory optimizations. The BRAM connects to the AXI4 interface through a Block RAM Controller IP, which translates AXI4 to the BRAM interface and provides direct access to the memory via AXI4.

Custom IP A custom IP block was needed to test the functionality of the PCI Express Bridge. The logic of the IP block has three main objectives; read a control register from the AXI-bus, read the data register and shift the data on the output. The implementation, therefore, requires AXI communication with custom logic. Fortunately, Vivado includes a utility to easily create custom AXI peripherals, which takes care of the AXI communication and leaves the user to implement the custom logic. The data rate of the output is selectable through a conﬁgurable PLL. This clock output is synchronized with the data, resulting in synchronous serial communication, perfectly ﬁtted for a test application. The selectable output frequency is used to test the maximum transmission rate on the GPIO outputs. By setting a high data rate and modifying the transmitted data, it was possible to measure the performance of the LVDS/CMOS side. By having a 400 MHz data rate and sending 1111000011110000..., the bridge would generate a 50 MHz square wave. 110011001100... would generate a 100 MHz square wave. The maximum frequency that was tested was 200 MHz.

Constraints Constraints exist to inform the FPGA of each pin’s behavior. They are used to constrain the internal ports to the external pins of the FPGA. Additionally, they can be used to set direction, terminations, and voltage levels. Certain pins are designed to operate certain functions. Constraints covering these pins are, therefore, restricted.

Simulation and Debug The Vivado design suite offers the creator to simulate individual blocks or the entire ﬁrmware without synthesizing or implementing the design, which enables faster developing. The simulation utility interprets the behavior of the blocks and presents the input and output signals and their values. The debug core displays the signal values in a similar style but are instead running on the actual FPGA instead of in a simulator. An IP called Virtual Input/Output (VIO) is a part of the debug utility and lets the user set or read speciﬁc ports in real time.

42 7.4. Platform application

Test application The functionality is going to vary based on future applications, but the device should have the capability to output Serial based protocols at reasonable speeds. Consequently, as a test application, the user should enter data to a register on the platform system. Once the data is set, the user deﬁnes the number of bytes to be clocked out and triggers the event through a control register. The FPGA uses a separate clock signal to clock out the data, bit by bit, at the desired rate. The application should read the data on a separate pin and verify that the input matches the output. The result should present an indication of the maximum obtainable throughput possible on the GPIO side.

7.4 Platform application

Every PCI Express device retrieves a base address upon enumeration. The base address spans the necessary length to include all addressable memory as defined within the FPGA. If the BAR is configured to point to a specific block at address 0x00001000 and the base address defined by the platform system is 0x80300000, the resulting memory location is 0x80301000. This memory corresponds to the physical memory of the platform, rather than the virtual memory. The location of the physical memory is on the platform’s RAM, while the virtual memory is located at the hard drive. The capacity is, therefore, limited by the RAM volume on the platform device. The physical memory is directly accessible from Linux through \dev\mem, as seen in Fig. 7.7. An operation which writes a value to the resulting address above can be used to trigger an event inside the FPGA. Once a value to a specific register is written, the FPGA can respond to the operation and perform an action based on the content of the value.

Figure 7.7: Platform application writing to register and validates its value.

43 8 Results

This chapter will present the results of this thesis. The results cover the PCB layout and the measured performance of the bridge. The chapter will also summarize the hardware modiﬁcations that were made to the bridge after the components had been mounted. A brief summary of the bridge size and performance is presented in Table 8.1.

Table 8.1: Summary of bridge dimensions and performance

Property Value Dimensions (Width x Length) 22x80 mm M.2 connector keying M-key Height (above PCB) 4.9 mm Height (below PCB) 0.9 mm Max transfer rate (PCI Express) 5 GT/s Link width x2 Max data rate (PCI Express) 8 Gb/s Max data rate (LVDS/CMOS) 200 Mb/s per pin Number of GPIOs 20 Single ended or 10 Differential

8.1 PCB Layout

The PCB consists of a 4 layer stackup. The layers are presented below.

Figure 8.1: Layout – Top Layer

44 8.2. Bridge performance

Figure 8.2: Layout – Inner Layer 1

Figure 8.3: Layout – Inner Layer 2

Figure 8.4: Layout – Bottom

8.2 Bridge performance

The PCI Express side of the bridge behaves as expected with it being recognized by the platform as a PCI Express 5GT/s x2 device. With the 8/10 bit encoding employed by PCI Express, this results in a max transfer rate of 8 Gb/s. The temperature of the Artix-7 as measured by the Vivado IDE was consistently lower than 75o C. As seen in Fig. 8.5-8.6 the LVDS/CMOS side was able to output waveforms at up to 200 MHz.

45 8.3. Summary of hardware modiﬁcations

Figure 8.5: Output signal at 100 MHz.

Figure 8.6: Output signal at 200 MHz.

Unfortunately, it proved difﬁcult to measure the latency of the bridge. The main reason being that the PCI Express link frequency at 5 GHz was too high to measure using any of the instruments at hand.

8.3 Summary of hardware modiﬁcations

This section will summarize the hardware modiﬁcations that were done to the bridge after it had been assembled. These changes were necessary for the bridge to boot and behave as expected.

46 8.4. Software design

The nPor ﬁx

The first hardware modification was the "nPor fix". It included fixing the VCCO,3V3 voltage level as well as modifying the power-up sequence. The problem and cause is described in greater detail under section 6.3. Fig. 8.7 displays the fix both in Altium designer and on the PCB.

Figure 8.7: the nPor fix. Right: Altium designer screenshot with the modifications, Left: Same modification on the PCB.

The reference clock fix The second modification will be referred to as the reference clock. During design, the CLKREQ pin on the M.2 connector was left floating. Its purpose is to tell the master device that there is a PCI Express device connected and that it requires a reference clock. The pin should have been connected directly to ground. A small wire was soldered to the pin and an unused ground pad on the bridge. The fix is shown in Fig. 8.8. The two black wires at the bottom left of Fig. 8.8 are for SMBus debugging and are not necessary in the final product.

Figure 8.8: The CLKREQ fix. Right: Altium designer screenshot with the modification, Left: Same modification on the PCB.

8.4 Software design

PCI Express commands are sent from the platform through PCI Express, translated to AXI and stored in a FIFO buffer. A series of control register bits are used to initiate a transmission which forwards data to the GPIOs. Fig. 8.9 shows a simulated signal of the output signals from Vivado. The real output signals, measured by a logic analyzer, is illustrated in Fig. 8.10

47 8.4. Software design

Figure 8.9: Signals; TX ready, data request, data in, data out, clock and state.

Figure 8.10: Output signals; data and clock.

48 9 Discussion and conclusion

This chapter will discuss the component choices, implementation, and future improvements of the PCI Express Bridge.

9.1 Design requirements and research questions

The final design manages to fulfill all design requirements with the exception of the latency, which was not measured. It has a PCI Express Gen 2 x2 interface, one generation better than the specified Gen 1. The LVDS/CMOS interface is capable of communicating at speeds up to 200 MHz on multiple pins simultaneously and independently. As for the physical size of the bridge, it is within the 22x80x0.8 mm requirement and fits any standard M.2 expansion slot. The bridge runs at a slightly high 75o C without air flow but the temperature does not appear to rise further under load. It was unfortunate that the latency proved difficult to measure. Since both the PCI Ex- press and internal AXI are high-speed interfaces, the latency through the system should be low. It may be possible to measure the delay using internal signals in the FPGA or with better measuring equipment, but it was of greater interest focus on the software and enhance functionality. As for the research questions, the prestudy concluded that the use of an FPGA was the best solution since it introduces very little delay and allows for high throughput on multiple channels.

9.2 Implementation

The bridge works, with minor modifications, as expected. The bridge can accept commands sent through PCI Express and perform pre-programmed actions specified in its firmware. The minor modifications are related to the power sequence functionality and PCI Express clock reference request. They are solved by performing the fixes described in Section 8.3. The software is implemented to test the bridges functionality. Further development, to fully implement the desired protocols, is required. The current firmware can load and transmit data sent over PCI Express. A desired improvement would be to add the ability to receive data on the LVDS/CMOS interface and sent it over PCI Express.

49 9.2. Implementation

The bridge is using a general purpose pin header for the inputs and outputs. The solution is universal, adaptable, and works for low to medium speed applications. Applications which operate at a high frequency might require special connectors with sufficient shielding and controlled impedance to improve the signal integrity and noise sensitivity. Changes to the bridge layout should be made to suit specific requirements or applications. A benefit of the current design is that the interface that is used internally is the well established AXI interface. Any further development on the bridge can be targeted towards AXI, rather than a device specific PCI Express implementation. This greatly decreases the complexity of the solution.

50 Bibliography

[1] PCI-SIG. PCI Express®Base Speciﬁcation Revision 3.0. Tech. rep. 2010. [2] [UG-01145] Intel® Arria® 10 or Intel® Cyclone®10 GX Avalon®-MM DMA Interfacefor PCI Express* Solutions UserGuide. Page 12. Intel. 2018. [3] [UG0447] User Guide, SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces, Rev. 8.0. Page 17. Microsemi. 2018. [4] [FPGA-IPUG-02009] PCI Express x1/x2/x4 Endpoint IP Core User Guide. Page 6-7. Lattice Semiconductor. 2017. [5] [PG054] 7 Series Integrated Block for PCIe, v3.3. Xilinx Inc. 2018. [6] CYCLONE® IV FPGAs PRODUCT TABLE. Intel. URL: https://www.intel.com/ content/dam/www/programmable/us/en/pdfs/literature/pt/cyclone- iv-product-table.pdf. [7] INTEL® CYCLONE® 10 GX FPGAs PRODUCT TABLE. Intel. URL: https://www. intel.com/content/dam/www/programmable/us/en/pdfs/literature/ pt/cyclone-10-gx-product-table.pdf. [8] ARRIA V FPGA AND SoC FEATURES. Intel. URL: https : / / www . intel . com / content/dam/www/programmable/us/en/pdfs/literature/pt/arria- v-product-table.pdf. [9] STRATIX V FPGA FEATURES. Intel. URL: https://www.intel.com/content/ dam / www / programmable / us / en / pdfs / literature / pt / stratix - v - product-table.pdf. [10] [DS1006] LatticeECP2/M Family Data Sheet. Page 3. Lattice Semiconductor. June 2017. [11] [I0211] PRODUCT SELECTOR GUIDE November 2018. Page 6. Lattice Semiconductor. 2018. [12] [PB0121] Product Brief, IGLOO2 FPGA. Page 8. Microsemi. 2018. [13] [PB0115] Product Brief, SmartFusion2 SoC FPGA. Page 9-10. Microsemi. 2018. [14] [DS160] Spartan-6 Family Overview, v2.0. Page 2-3. Xilinx Inc. 2011. [15] [DS180] 7 Series FPGAs Data Sheet: Overview, v2.6. Page 3-6. Xilinx Inc. 2018. [16] [UG470] 7 Series FPGAs Conﬁguration User Guide, v1.13.1. Xilinx Inc. 2018.

51 Bibliography

[17] Power-Supply Solutions for Xilinx FPGAs. Maxim Integrated. URL: https : / / www . maximintegrated.com/en/app-notes/index.mvp/id/5132. [18] [UG482] 7 Series FPGAs GTP Transceivers User Guide, v1.9. Xilinx Inc. 2016. [19] [SNVS543N9] LM26480 Dual 2-MHz, 1.5-A Buck Regulators and Dual 300-mA LDOs With Individual Enable and Power Good. Texas Instruments. URL: www.ti.com/lit/ds/ symlink/lm26480.pdf. [20] [DS181] Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics, v.1.25. Xilinx Inc. 2018. [21] [SNVS543N] LM26480Dual 2-MHz,1.5-A Buck Regulators and Dual 300-mA LDOs With Individual Enable and Power Good, Rev. N. Page 25-27, 28-30. Texas Instruments Inc. 2016. [22] Murata. Ceramic Capacitors FAQ. URL: https : / / www . murata . com / en - sg / support/faqs/products/capacitor/mlcc/char/0005. [23] [SBVS351C] TLV758P 500-mA, high-accuracy, adjustable LDO in a small size package, Rev. C. Texas Instruments Inc. 2019. [24] [UG483] 7 Series FPGAs PCB Design Guide, v1.13. Xilinx Inc. 2017. [25] AXI Reference Guide. Xilinx Inc. URL: https : / / www . xilinx . com / support / documentation/ip_documentation/ug761_axi_reference_guide.pdf. [26] AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.8. Xilinx Inc. URL: https://www. xilinx.com/support/documentation/ip_documentation/axi_pcie/v2_ 8/pg055-axi-bridge-pcie.pdf.

52 Appendix A Comparison Chart

GPIO Speed GPIO Speed Manufacturer Product name Price (USD) PCIe support Logic element/cells Footprint (Pitch & Type) Size (BxH) GPIOs I/O-voltage SerDes Channels Candidate? Motivation (Single-ended) (Differential) Lattice ECP2 (LFE2M20E-5FN256C) 41 Gen1 x4 19K 1 mm BGA 17x17 140 1.2V-3.3V 311 MHz 4 No Expensive price/performance

Lattice ECP3 (LFE3-17EA-6FTN256C) 18 Gen1 x4 17K 1 mm BGA 17x17 133 1.2V-3.3V 500 MHz 4 No Expensive price/performance

Next gen hardware available for Lattice ECP5 (LFE5UM-25F-8BG381C) 15 Gen1 x4 24,000 0.8 mm BGA 17x17 197 1.2V-3.3V 150 MHz 400 MHz 2 No almost the same price Next gen hardware available for Lattice ECP5 (LFE5UM-45F-8BG381C) 26 Gen1 x4 44K (Upp till 85K) 0.8 mm BGA 17x17 203 1.2V-3.3V 150 MHz 400 MHz 4 No almost the same price

Lattice ECP5-5G (LFE5UM5G-25F-8BG381C) 19 Gen2 x2 soft 24K (Upp till 85K) 0.8 mm BGA 17x17 203 1.2V-3.3V 150 MHz 400 MHz 4 Yes

Lattice ECP5-5G (LFE5UM5G-45F-8BG381C) 31 Gen2 x2 soft 44K (Upp till 85K) 0.8 mm BGA 17x17 203 1.2V-3.3V 150 MHz 400 MHz 2 Yes

Requires Speed Grade 2 for PCIe Xiilinx Artix-7 (XC7A12T-2CSG325) 36 Gen2 x2 8k 0.8 mm BGA 15x15 150 1.2V-3.3V 200 MHz 1250 Mbps 2 Yes Gen 2 Requires Speed Grade 2 for PCIe Xilinx Artix-7 (XC7A25T-2CSG325I) 47 Gen2 x4 25K (Upp till 50K) 0.8 mm BGA 15x15 150 1.2V-3.3V 200 MHz 1250 Mbps 4 Yes Gen 2 Requires Speed Grade 2 for PCIe Xilinx Artix-7 (XC7A15T-2CSG325C) 47 Gen2 x4 16K (Upp till 50K) 0.8 mm BGA 15x15 150 1.2V-3.3V 200 MHz 1250 Mbps 4 Yes Gen 2

Xilinx Artix-7 (XC7A100T-1FGG484) 70 Gen2 x4 101K (Upp till 215K) 1 mm BGA 23x23 250 1.2V-3.3V 200 MHz 1250 Mbps 4 No Too big

Cheaper alternative with better Xilinx Spartan-6 (XC6SLX25T-N3CSG324C) 46 Gen1 x2 24K 0.8 mm BGA 15x15 190 1.5V-3.3V 1060 Mbps 2 No performance

Xilinx Kintex-7 (XC7K70T-1FBG484) 150 Gen2 x8 65K (Upp till 160K) 1 mm BGA 23x23 285 1.2V-3.3V 4 No Expensive, Too big

Xilinx Kintex Ultrascale Plus (XCKU3P-1SFVB784E) 1,000 Gen3 x16 356K 0.8 mm BGA 23x23 304 1.0V-3.3V 16 No Expensive, Too big

Xilinx Virtex Ultrascale Plus (XCVU3P-1FFVC1517E) 9,000 Gen3 x16 862K 1 mm BGA 40x40 520 1.0V-3.3V 40 No Expensive, Too big

Xilinx Virtex-7 XT (XC7VX330T-1FFG1157C) 2,500 Gen3 x8 326K 1 mm BGA 35x35 600 1.2V-3.3V 20 No Expensive, Too big

Expensive price/performance Intel Cyclone IV (EP4CGX30CF19C8N) 64 Gen1 x4 29K 1 mm BGA 19x19 150 1.2V-3.3V 200 MHz 848 Mbps 4 No (Gen1 PCIe)

Intel Cyclone 10 GX (10CX085YU484I6G) 100 Gen2 x4 85K 0.8 mm BGA 19x19 188 1.2V-3.0V 200 MHz 1.4 Gbps 6 No Expensive

Intel Cyclone 10 GX (10CX220YF780E5G) 260 Gen2 x4 220K 1 mm BGA 29x29 284 1.2V-3.0V 200 MHz 1.4 Gbps 12 No Expensive, Too big

Intel Arria V GX (5AGXMA5G4F35C4G) 1,000 Gen2 x4 75K (Upp till 504K) 1 mm BGA 27x27 336 1.2V-3.3V 200 MHz 1.6 Gbps 9 No Expensive, Too big

Intel Stratix V GX ( 5SGXMA3E3H29C4N ) 2,000 Gen3 x8 340K 1 mm BGA 29x29 360 1.2V-3.0V 167 MHz 1.6 Gbps 12 No Expensive, Too big

Intel Arria V GZ (5AGZME1E3H29C4N) 1,500 Gen3 x8 220K (Upp till 450K) 1 mm BGA 29x29 342 1.2V-3.3V 200 MHz 1.6 Gbps 12 No Expensive, Too big

Microsemi SmartFusion2 (M2S010T-1VF400) 36 Gen2 x4 12K 0.8 mm BGA 17x17 195 1.2V-3.3V 400 MHz 700 Mbps 4 No Complicated, Hard to source

Microsemi IGLOO2 (M2GL025T-1VF400) 63 Gen2 x4 25K 0.8 mm BGA 17x17 195 1.2V-3.3V 400 MHz 700 Mbps 4 Yes

Microsemi IGLOO2 (M2GL010T-1VF400) 37 Gen2 x4 12K 0.8 mm BGA 17x17 195 1.2V-3.3V 400 MHz 700 Mbps 4 No Hard to source

Microsemi IGLOO2 (M2GL005-VFG256) 30 Gen1 x4 12K 0.8 mm BGA 17x17 195 1.2V-3.3V 400 MHz 700 Mbps 2 No Cant do PCIe

Utvecklings Intressanta serier Licenskrav IDE

Lattice ECP5-5G Series Diamond Ja

Xilinx Artix-7 Series Vivado Nej

Intel Cyclone 10 Series Quartus Pro

Microsemi IGLOO2 Series Libero Gold 1 2 3 4 Appendix B

A A

B B

C C

D D Rev. 1.0 System Sketch Sheet1 of 8 Project: PCIe Bridge File: system_sketch.SchDoc Linköping University 2019-03-27 Author(s): Håkan Gerner Mandus Börjesson 1 2 3 4 1 2 3 4

VCC_3V3 VCC_3V3 COU3U3

VCC_3V3 PIR2302 PIR2401 PIU301616 COR23R23 COR24R24 VCC TS3A5018 4 x SPDT PIC2002 PIC2102 10K 10K 15 PIU3015 EN# COC20C20 COC21C21 PIR2301 PIR2402 1 A PIU301 IN1 A PIC2001 0.47uF PIC2101 0.47uF 3 NO1 PIU303 FPGA_CFG_CS_N COU4U4 6 NO2 PIU306 10 GND NO3 PIU3010 FPGA_CFG_MOSI VCC_3V3 NOR Flash FLASH_CS_N 4 13 16 kb, SPI PIU304 COM1 NO4 PIU3013 FPGA_CFG_CLK GND 8 5 FLASH_MOSI 7 PIU408 VDD SI/SIO0 PIU405 PIU307 COM2 2 FLASH_MISO 9 SO/SIO1 PIU402 PIU309 COM3 1 6 FLASH_CLK 12 2 PIU401 CE# SCK PIU406 PIU3012 COM4 NC1 PIU302 3 5 PIU403 WP#/SIO2 NC2 PIU305 7 11 PIU407 HOLD#/SIO3 NC3 PIU3011 14 NC4 PIU3014 4 8 PIU404 GND PIU308 GND 17 PIU3017 DAP SST26VF016B GND TS3A5018 GND DAP = Die Attached Pad, Not used Common MISO since there is only one driving node (FLASH memory), reduces number of used SPDTs (easier to route)

VCC_3V3 COU5U5 B B PIR2502 I2C to SPI Bridge COR25R25 12 6 PROG_MOSI PIU5012 VDD MOSI PIU506 10K 5 MISO PIU505 FPGA_CFG_MISO PIR2501 3 11 PROG_CLK RESET_N PIU503 RESET# SPICLK PIU5011 9 PIU509 INT# 8 SCL PIU508 SMB_CLK 7 SDA PIU507 SMB_DATA 1 SS0#/GPIO0 PIU501 2 SS1#/GPIO1 PIU502 FPGA_PROGRAM 10 SS2#/GPIO2 PIU5010 FPGA_DONE 13 PROG_CS_N SS3#/GPIO3 PIU5013 16 A2 PIU5016 15 VCC_3V3 A1 PIU5015 4 14 PIU504 GND A0 PIU5014 PIR2601 COU6U6 SC18IS602B COR26R26 4 1 C PIU604 VCC SCL PIU601 C 10K 3 SDA PIU603 GND I2C address: 0101[A2][A1][A0][R/W] GND PIR2602 5 PITP901 PIU605 WP COTP9TP9 EEPROM 4 kb, I2C 2 PIU602 GND AT24C04D VCCO_0_3V3 GND PIR2702 PIR2802 PIR2902 COR27R27 COR28R28 COR29R29 10K 10K 10K COP1P1 PIR2701 PIR2801 PIR2901 1 3 PIP101 VREF TMS PIP103 JTAG_TMS 4 2 PIP104 GND TCK PIP102 JTAG_TCK 7 6 PIP107 GND TDO PIP106 JTAG_TDO 8 5 D PIP108 GND TDI PIP105 JTAG_TDI D Rev. 1.0 Programming Interface Sheet2 of 8 JTAG Project: PCIe Bridge GND JTAG File: Programming.SchDoc Linköping University 2019-03-27 Author(s): Håkan Gerner Mandus Börjesson 1 2 3 4 1 2 3 4

Requirements: [UG470] - 7 Series FPGAs Configuration User Guide, p.25-26: PUDC_B = HIGH to force IO's to HIGH-Z (For SET_IO regulation to work as expected PROGRAM_B: Reloads configuration when pulsed LOW. U7B INIT_B: Initialization, Can be held low to stall initialization on power-up, external <4.7k Pullup. BANK 14 DONE: Goes HIGH when a configuration is complete, internal 10k Artix-7 CSG325 FPGA Pullup. A A K16 CFGBVS: Configuration bank voltage select, HIGH -> 3.3V or 2.5V. IO_L1P_T0_D00_MOSI_14 PIU70K16 FPGA_CFG_MOSI L17 IO_L1N_T0_D01_DIN_14 PIU70L17 FPGA_CFG_MISO J15 IO_L2P_T0_D02_14 PIU70J15 [UG470] - 7 Series FPGAs Configuration User Guide, v1.13.1, p.27-28. J16 IO_L2N_T0_D03_14 PIU70J16 COR45 J18 IO_L3P_T0_DQS_PUDC_B_14 PIU70J18PIR4502 PIR4501 VCCO_0_3V3 PUDC_B: When PUDC_B is [LOW/HIGH], internal pull-up resistors are K18 IO_L3N_T0_DQS_EMCCLK_14 PIU70K18 330 [ENABLED/DISABLED] on each SelectIO pin. L15 IO_L6P_T0_FCS_B_14 PIU70L15 FPGA_CFG_CS_N EMCCLK: Optional external configuration clock, <1k pull to T18 IO_L15N_T2_DQS_DOUT_CSO_B_14 PIU70T18 SET_IO_3V3_N LOW/HIGH. CSO: For serial modes: CSO_B is a multi-purpose pin that functions as L14 IO_0_14 PIU70L14 the DOUT pin. K17 IO_L4P_T0_D04_14 PIU70K17 L18 IO_L4N_T0_D05_14 PIU70L18 J14 IO_L5P_T0_D06_14 PIU70J14 K15 IO_L5N_T0_D07_14 PIU70K15 M15 IO_L6N_T0_D08_VREF_14 PIU70M15 M16 M[2:0] = 001 SPI Master Mode IO_L7P_T1_D09_14 PIU70M16 M17 IO_L7N_T1_D10_14 PIU70M17 COU7ACOU7BU7A M14 IO_L8P_T1_D11_14 PIU70M14 VCCO_0_3V3 N14 B IO_L8N_T1_D12_14 PIU70N14 BANK 0 B N16 Artix-7 CSG325 FPGA IO_L9P_T1_DQS_14 PIU70N16 F13 N17 M2_0 PIU70F13 IO_L9N_T1_DQS_D13_14 PIU70N17 R11 N18 M1_0 PIU70R11 IO_L10P_T1_D14_14 PIU70N18 R12 PIR4602 PIR4702 P18 M0_0 PIU70R12 IO_L10N_T1_D15_14 PIU70P18 SET_IO_2V5_N COR46R46 COR47R47 P15 IO_L11P_T1_SRCC_14 PIU70P15 GND 4.7K 4.7K P16 IO_L11N_T1_SRCC_14 PIU70P16 T10 PIR4601 PIR4701 P14 INIT_B_0 PIU70T10 IO_L12P_T1_MRCC_14 PIU70P14 P10 R15 PROGRAM_B_0 PIU70P10 FPGA_PROGRAM IO_L12N_T1_MRCC_14 PIU70R15 T14 IO_L13P_T2_MRCC_14 PIU70T14 E8 T15 CCLK_0 PIU70E8 FPGA_CFG_CLK IO_L13N_T2_MRCC_14 PIU70T15 R16 COR48 IO_L14P_T2_SRCC_14 PIU70R16 F12 R48 DONE: Short-circuit protection R17 DONE_0 PIU70F12PIR4802 PIR4801 FPGA_DONE IO_L14N_T2_SRCC_14 PIU70R17 I2C bridge output default HIGH R18 10K IO_L15P_T2_DQS_RDWR_B_14 PIU70R18 SET_IO_1V8_N E12 T17 CFGBVS_0 PIU70E12 VCCO_0_3V3 IO_L16P_T2_CSI_B_14 PIU70T17 U17 IO_L16N_T2_A15_D31_14 PIU70U17 T9 U15 TDI_0 PIU70T9 JTAG_TDI IO_L17P_T2_A14_D30_14 PIU70U15 R8 U16 TMS_0 PIU70R8 JTAG_TMS IO_L17N_T2_A13_D29_14 PIU70U16 F8 V16 TCK_0 PIU70F8 JTAG_TCK IO_L18P_T2_A12_D28_14 PIU70V16 T8 V17 TDO_0 PIU70T8 JTAG_TDO C IO_L18N_T2_A11_D27_14 PIU70V17 C R13 IO_L19P_T3_A10_D26_14 PIU70R13 T13 IO_L19N_T3_A09_D25_VREF_14 PIU70T13 U14 IO_L20P_T3_A08_D24_14 PIU70U14 E11 M10 V14 PIU70E11 VCCBATT_0 DXP_0 PIU70M10 IO_L20N_T3_A07_D23_14 PIU70V14 M9 V12 DXN_0 PIU70M9 IO_L21P_T3_DQS_14 PIU70V12 V13 IO_L21N_T3_DQS_A06_D22_14 PIU70V13 GND L10 T12 VREFP_0 PIU70L10 IO_L22P_T3_A05_D21_14 PIU70T12 VCCAUX_1V8 XADC K9 U12 VREFN_0 PIU70K9 IO_L22N_T3_A04_D20_14 PIU70U12 J10 K10 U11 PIU70J10 VCCADC_0 VP_0 PIU70K10 IO_L23P_T3_A03_D19_14 PIU70U11 J9 L9 V11 PIU70J9 GNDADC_0 VN_0 PIU70L9 IO_L23N_T3_A02_D18_14 PIU70V11 U9 IO_L24P_T3_A01_D17_14 PIU70U9 Artix-7 FPGA V9 IO_L24N_T3_A00_D16_14 PIU70V9 GND GND U10 IO_25_14 PIU70U10 Artix-7 FPGA

D D Rev. 1.0 Artix-7 Configuration Banks Sheet3 of 8 Project: PCIe Bridge File: Bank_0_14.SchDoc Linköping University 2019-03-27 Author(s): Håkan Gerner Mandus Börjesson 1 2 3 4 1 2 3 4

COU7CCOU7EU7C U7E COP2P2

0_P PIP2011 PIP2022 BANK 15 BANK 34 0_N 3 4 Artix-7 CSG325 FPGA Artix-7 CSG325 FPGA PIP203 PIP204 1_P PIP2055 PIP2066 D10 J6 1_N 7 8 A IO_0_15 PIU70D10 IO_0_34 PIU70J6 PIP207 PIP208 A D8 K6 2_P 9 10 IO_L1P_T0_AD0P_15 PIU70D8 IO_L1P_T0_34 PIU70K6 PIP209 PIP2010 C8 K5 2_N 11 Pin Header 12 IO_L1N_T0_AD0N_15 PIU70C8 IO_L1N_T0_34 PIU70K5 PIP2011 PIP2012 D9 J5 3_P 13 1.27 mm 14 IO_L2P_T0_AD8P_15 PIU70D9 IO_L2P_T0_34 PIU70J5 PIP2013 PIP2014 C9 J4 3_N 15 16 IO_L2N_T0_AD8N_15 PIU70C9 IO_L2N_T0_34 PIU70J4 PIP2015 PIP2016 B9 K2 4_P 17 18 IO_L3P_T0_DQS_AD1P_15 PIU70B9 IO_L3P_T0_DQS_34 PIU70K2 PIP2017 PIP2018 A9 K1 4_N 19 20 IO_L3N_T0_DQS_AD1N_15 PIU70A9 IO_L3N_T0_DQS_34 PIU70K1 PIP2019 PIP2020 C11 K3 IO_L4P_T0_AD9P_15 PIU70C11 IO_L4P_T0_34 PIU70K3 B11 L2 M50-361 IO_L4N_T0_AD9N_15 PIU70B11 IO_L4N_T0_34 PIU70L2 B10 L4 IO_L5P_T0_AD2P_15 PIU70B10 IO_L5P_T0_34 PIU70L4 A10 L3 0_P 1_P 2_P 3_P 4_P IO_L5N_T0_AD2N_15 PIU70A10 IO_L5N_T0_34 PIU70L3 D11 L5 PIR3501 PIR3601 PIR3701 PIR3801 PIR3901 GND IO_L6P_T0_15 PIU70D11 IO_L6P_T0_34 PIU70L5 C12 M5 COR35R35 COR36R36 R37COR37 COR38R38 COR39R39 IO_L6N_T0_VREF_15 PIU70C12 IO_L6N_T0_VREF_34 PIU70M5 B12 4_P M2 DNM DNM DNM DNM DNM IO_L7P_T1_AD10P_15 PIU70B12 IO_L7P_T1_34 PIU70M2 A12 4_N M1 PIR3502 0_N PIR3602 1_N PIR3702 2_N PIR3802 3_N PIR3902 4_N IO_L7N_T1_AD10N_15 PIU70A12 IO_L7N_T1_34 PIU70M1 A13 3_P M6 IO_L8P_T1_AD3P_15 PIU70A13 IO_L8P_T1_34 PIU70M6 A14 3_N N6 IO_L8N_T1_AD3N_15 PIU70A14 IO_L8N_T1_34 PIU70N6 C14 N1 IO_L9P_T1_DQS_AD11P_15 PIU70C14 IO_L9P_T1_DQS_34 PIU70N1 100 Ohm LVDS Termination (For test equipment) B15 P1 IO_L9N_T1_DQS_AD11N_15 PIU70B15 IO_L9N_T1_DQS_34 PIU70P1 B14 2_P M4 B IO_L10P_T1_AD4P_15 PIU70B14 IO_L10P_T1_34 PIU70M4 B A15 2_N N4 IO_L10N_T1_AD4N_15 PIU70A15 IO_L10N_T1_34 PIU70N4 D13 N3 9_P 8_P 7_P 5_P IO_L11P_T1_SRCC_AD12P_15 PIU70D13 IO_L11P_T1_SRCC_34 PIU70N3 C13 N2 PIR4001 PIR4101 PIR4201 PIR4301 IO_L11N_T1_SRCC_AD12N_15 PIU70C13 IO_L11N_T1_SRCC_34 PIU70N2 E13 P4 COR40R40 COR41R41 R42COR42 COR43R43 IO_L12P_T1_MRCC_AD5P_15 PIU70E13 IO_L12P_T1_MRCC_34 PIU70P4 D14 P3 DNM DNM DNM DNM IO_L12N_T1_MRCC_AD5N_15 PIU70D14 IO_L12N_T1_MRCC_34 PIU70P3 E15 R2 PIR4002 9_NPIR4102 8_N PIR4202 7_N PIR4302 5_N IO_L13P_T2_MRCC_15 PIU70E15 IO_L13P_T2_MRCC_34 PIU70R2 D15 R1 IO_L13N_T2_MRCC_15 PIU70D15 IO_L13N_T2_MRCC_34 PIU70R1 E16 R3 IO_L14P_T2_SRCC_15 PIU70E16 IO_L14P_T2_SRCC_34 PIU70R3 COP3P3 D16 T2 IO_L14N_T2_SRCC_15 PIU70D16 IO_L14N_T2_SRCC_34 PIU70T2 9_P 2 1 B16 U2 5_P PIP302 PIP301 IO_L15P_T2_DQS_15 PIU70B16 IO_L15P_T2_DQS_34 PIU70U2 9_N 4 3 A17 U1 5_N PIP304 PIP303 IO_L15N_T2_DQS_ADV_B_15 PIU70A17 IO_L15N_T2_DQS_34 PIU70U1 8_P 6 5 C16 1_P V3 6_P PIP306 PIP305 IO_L16P_T2_A28_15 PIU70C16 IO_L16P_T2_34 PIU70V3 8_N 8 7 B17 1_N V2 6_N PIP308 PIP307 IO_L16N_T2_A27_15 PIU70B17 IO_L16N_T2_34 PIU70V2 7_P 10 9 E17 T4 PIP3010 PIP309 IO_L17P_T2_A26_15 PIU70E17 IO_L17P_T2_34 PIU70T4 7_N 12 Pin Header 11 D18 T3 PIP3012 PIP3011 IO_L17N_T2_A25_15 PIU70D18 IO_L17N_T2_34 PIU70T3 14 1.27 mm 13 C17 0_P U4 7_P PIP3014 PIP3013 IO_L18P_T2_A24_15 PIU70C17 IO_L18P_T2_34 PIU70U4 16 15 C18 0_N V4 7_N PIP3016 PIP3015 IO_L18N_T2_A23_15 PIU70C18 IO_L18N_T2_34 PIU70V4 5_P 18 17 G17 P6 PIP3018 PIP3017 IO_L19P_T3_A22_15 PIU70G17 IO_L19P_T3_34 PIU70P6 5_N 20 19 F18 P5 PIP3020 PIP3019 C IO_L19N_T3_A21_VREF_15 PIU70F18 IO_L19N_T3_VREF_34 PIU70P5 C H16 U6 IO_L20P_T3_A20_15 PIU70H16 IO_L20P_T3_34 PIU70U6 M50-361 G16 U5 IO_L20N_T3_A19_15 PIU70G16 IO_L20N_T3_34 PIU70U5 GND G15 R5 6_P IO_L21P_T3_DQS_15 PIU70G15 IO_L21P_T3_DQS_34 PIU70R5 F15 T5 PIR4402 IO_L21N_T3_DQS_A18_15 PIU70F15 IO_L21N_T3_DQS_34 PIU70T5 G14 R7 COR44R44 IO_L22P_T3_A17_15 PIU70G14 IO_L22P_T3_34 PIU70R7 F14 T7 DNM IO_L22N_T3_A16_15 PIU70F14 IO_L22N_T3_34 PIU70T7 H17 U7 8_P PIR4401 6_N IO_L23P_T3_FOE_B_15 PIU70H17 IO_L23P_T3_34 PIU70U7 H18 V6 8_N IO_L23N_T3_FWE_B_15 PIU70H18 IO_L23N_T3_34 PIU70V6 F17 V8 9_P IO_L24P_T3_RS1_15 PIU70F17 IO_L24P_T3_34 PIU70V8 E18 V7 9_N IO_L24N_T3_RS0_15 PIU70E18 IO_L24N_T3_34 PIU70V7 H14 R6 IO_25_15 PIU70H14 IO_25_34 PIU70R6 Artix-7 FPGA Artix-7 FPGA

D D Rev. 1.0 Artix-7 IO Bank 15&34 Sheet4 of 8 Project: PCIe Bridge File: Bank_15_34.SchDoc Linköping University 2019-03-27 Author(s): Håkan Gerner Mandus Börjesson 1 2 3 4 1 2 3 4

A A

VMGTAVTT_1V2 COU7DU7D PIR3401 BANK 216, GTP COR34R34 Artix-7 CSG325 FPGA A6 PIR3402 100 MGTRREF_216 PIU70A6 D6 B MGTREFCLK0P_216 PIU70D6 B D5 MGTREFCLK0N_216 PIU70D5 B6 PCIE_CLK_P MGTREFCLK1P_216 PIU70B6 PCIE_CLK_P B5 PCIE_CLK_N MGTREFCLK1N_216 PIU70B5 PCIE_CLK_N H2 PCIE_TX1_P MGTPTXP0_216 PIU70H2 PCIE_TX1_P H1 PCIE_TX1_N MGTPTXN0_216 PIU70H1 PCIE_TX1_N E4 PCIE_RX1_P MGTPRXP0_216 PIU70E4 PCIE_RX1_P E3 PCIE_RX1_N MGTPRXN0_216 PIU70E3 PCIE_RX1_N F2 PCIE_TX0_P MGTPTXP1_216 PIU70F2 PCIE_TX0_P F1 PCIE_TX0_N MGTPTXN1_216 PIU70F1 PCIE_TX0_N A4 PCIE_RX0_P MGTPRXP1_216 PIU70A4 PCIE_RX0_P A3 PCIE_RX0_N MGTPRXN1_216 PIU70A3 PCIE_RX0_N D2 MGTPTXP2_216 PIU70D2 D1 MGTPTXN2_216 PIU70D1 C4 MGTPRXP2_216 PIU70C4 C3 MGTPRXN2_216 PIU70C3 C C B2 MGTPTXP3_216 PIU70B2 B1 MGTPTXN3_216 PIU70B1 G4 MGTPRXP3_216 PIU70G4 G3 MGTPRXN3_216 PIU70G3 Artix-7 FPGA GND GND

D D Rev. 1.0 Artix-7 GTP Transcievers Sheet5 of 8 Project: PCIe Bridge File: Transcievers.SchDoc Linköping University 2019-03-27 Author(s): Håkan Gerner Mandus Börjesson 1 2 3 4 1 2 3 4

A A

VCC_3V3 COP4P4 1 2 PIP401 GND 3.3 V PIP402 3 4 PIP403 GND 3.3 V PIP404 5 6 PIP405 PETn3 N/A PIP406 SMBUS Specification: 7 8 PIP407 PETp3 N/A PIP408 Pull-up resistors to 1.8V (SMB_CLK, SMB_DATA) on platform. 9 10 PIP409 GND DAS/DSS PIP4010 Logic Level Converter (1.8V to 3.3V) 11 12 PIP4011 PERn3 3.3 V PIP4012 13 14 PIP4013 PERp3 3.3 V PIP4014 15 16 PIP4015 GND 3.3 V PIP4016 VCCAUX_1V8 VCC_3V3 17 18 PIP4017 PETn2 3.3 V PIP4018 19 20 PIP4019 PETp2 N/A PIP4020 PIR3002 PIR3102 21 22 PIP4021 GND N/A PIP4022 COR30R30 PIQ201 R31COR31 23 24 DNM PIP4023 PERn2 N/A PIP4024 10K 10K 25 26 PIP4025 PERp2 N/A PIP4026 PIR3001 PIR3101 B COC22 27 28 PIQ202 PIQ203 SMB_CLK B C22 PIP4027 GND N/A PIP4028 COC23 M2_TX1_N 29 30 PCIE_TX1_N C23 PIC2201 PIC2202 PIP4029 PETn1 N/A PIP4030 M2_TX1_P 31 32 VCCAUX_1V8 VCC_3V3 COQ2Q2 PCIE_TX1_P PIC2301 PIC2302 PIP4031 PETp1 N/A PIP4032 100nF 33 34 BSS806 PIP4033 GND N/A PIP4034 100nF 35 36 PIR3202 PIR3302 PCIE_RX1_N PIP4035 PERn1 N/A PIP4036 37 38 COR32R32 PIQ301 COR33R33 PCIE_RX1_P PIP4037 PERp1 M.2 Connector DEVSLP PIP4038 DNM COC24 39 Finger Edge 40 10K 10K C24 PIP4039 GND SMB_CLK PIP4040 COC25 M2_TX0_N 41 Module 3 (M key) 42 PIR3201 PIR3301 PCIE_TX0_N C25 PIC2401 PIC2402 PIP4041 PETn0 SMB_DATA PIP4042 PIQ302 PIQ303 SMB_DATA M2_TX0_P 43 44 PCIE_TX0_P PIC2501 PIC2502 PIP4043 PETp0 ALERT# PIP4044 100nF 45 46 PIP4045 GND N/A PIP4046 COQ3Q3 100nF 47 48 PCIE_RX0_N PIP4047 PERn0 N/A PIP4048 BSS806 49 50 PCIE_RX0_P PIP4049 PERp0 PERST# PIP4050 RESET_N COC26 51 52 C26 PIP4051 GND CLKREQ# PIP4052 COC27 M2_CLK_N 53 54 PCIE_CLK_P C27 PIC2601 PIC2602 PIP4053 REFCLKN PEWAKE# PIP4054 M2_CLK_P 55 56 PCIE_CLK_N PIC2701 PIC2702 PIP4055 REFCLKP MFG1 PIP4056 100nF 57 58 PIP4057 GND MFG2 PIP4058 100nF

C C 67 68 PIP4067 N/A SUSCLK PIP4068 69 70 PIP4069 PEDET 3.3 V PIP4070 71 72 PIP4071 GND 3.3 V PIP4072 73 74 PIP4073 GND 3.3 V PIP4074 75 PIP4075 GND M.2 PCIe

GND

D D Rev. 1.0 PCI Express Connector Sheet6 of 8 Project: PCIe Bridge File: PCIe.SchDoc Linköping University 2019-03-27 Author(s): Håkan Gerner Mandus Börjesson 1 2 3 4 1 2 3 4

VCC_3V3 COU1U1 COL1L1 1 5 PIU101 VINLDO12 SW1 PIU105PIL102 PIL101 VCCINT_1V0 PIC102 PIC202 PIC302 PIC402 10 2.2uH PIC502 PIR102 PIC602 COC1C1 COC2C2 COC3C3 COC4C4 PIU1010 AVDD 6 1uF 1uF 10uF 10uF PIU106 VIN1 PIC101 PIC201 PIC301 PIC401 13 PIC501 COC5C5 COR1R1 PIC601 COC6C6 PIU1013 VIN2 8 15pF PIR101 100K 10uF NPOR - Power On Reset, default 60 ms PG delay A FB1 PIU108 A PIR202 NPOR is pulled to ground when the voltages on SW1 and SW2 are not good GND COC7C7 PIC702 DNM COR2R2 Used to sequence VCCO. VCCAUX_1V8 VCC_3V3 PIC701 PIR201 100K PIR302 PIR402 COQ1Q1 COR3 COR4 GND VCC_3V3 DNM COL2L2 0 0 14 SW2 PIU1014PIL201 PIL202 VCCAUX_1V8 PIQ103 PIQ102 VCCO_0_3V3 PIR301 PIR401 Vin_LDO 19 2.2uH PIC802 PIR502 PIC902 PIU1019 VINLDO1 PIC1002 PIC1102 24 COC8C8 PIU1024 VINLDO2 8.2pF PIC801 COR5R5 PIC901 COC9C9 PIC1001 COC10C10 PIC1101 COC11C11 11 PIR501 390K 10uF NPOR PIQ101 FB2 PIU1011 1uF 1uF PIR602 BSS806 VCC_3V3 COC12C12 PIC1202 PMIC DNM COR6R6 2x Switching regulator PIR702 GND PIC1201 PIR601 150K COR7R7 2x Low drop-out regulators 100K PIR701 NPOR 3 GND VCC_3V3 COU2U2 B PIU103 NPOR B 20 6 1 LDO1 PIU1020 VMGTAVTT_1V2 PIU206 IN OUT PIU201 VCCO_15_34_ADJ VCC_3V3 VCC_3V3 VCC_3V3 VCC_3V3 PIR902 PIC1402 PIC1301 PIR802 C13COC13 4 R8COR8 PIU204 EN LDO PIR1001 PIR1101 PIR1201 COR9R9 PIC1401 COC14C14 PIC1302 1uF 7 39K PIU207 DAP COR10R10 COR11R11 COR12R12 21 PIR901 47K 1uF 3 2 PIR801 FBL1 PIU1021 PIU203 GND FB PIU202 10K 15K 4.7K 7 PIR1302 PIC1501 PIU107 ENSW1 PIR1002 PIR1102 PIR1202 12 TLV75801 COC15C15 PIU1012 ENSW2 17 COR13R13 GND PIC1502 1uF PIU1017 ENLDO1 PIU101616 PIR1301 33K PIR1402 PIR1502 PIR1602 PIR1702 ENLDO2 COR14R14 COR15R15 COR16R16 R17COR17 PIC1602 PIC1702 PIC1802 33K 15K 10K 33K 2 GND PIR1401 PIR1501 PIR1601 PIR1701 PIU102 SYNC PIC1601 COC16C16 PIC1701 COC17C17 PIC1801 COC18C18 4 23 PIR1802 PIR1902 PIR2002 PIU104 GND_SW1 LDO2 PIU1023 VMGTAVCC_1V0 100nF 100nF 100nF 15 PIR2102 PIC1902 COR18R18 COR19R19 COR20R20 PIU1015 GND_SW2 9 COR21R21 2.7K 1.5K 220 GND GND PIU109 GND_C GND GND GND 18 PIC1901 COC19C19 PIR1801 PIR1901 PIR2001 PIU1018 GND_L 25 22 PIR2101 100K 1uF PIU1025 DAP FBL2 PIU1022 PIR2202 SET_IO_2V5_N LM26480 COR22R22 C C GND SET_IO_1V8_N SET_IO_3V3_N PIR2201 100K Optimal power-on seq: Vccint, Vmgtavcc, Vgtavtt, Vccbram, Vccaux, Vcco (VGTAVCC before VGTAVTT most critical) GND Software configurable voltage divider LOW on selected voltage BUCK1, BUCK2 Startup time: 500us HIGH-Z on others LDO1, LDO2 Startup time: 300us

PITP101 VCCINT_1V0 PITP501 VMGTAVTT_1V2 RC Sequencing: Capacitors: COTP1TP1 COTP5TP5 tau_r = R*C 10uF 0805 C = 100nF -> GRM21BR61C106KE15 PITP201 VCCAUX_1V8 PITP601 VMGTAVCC_1V0 COTP2TP2 COTP6TP6 R = 5K: 500us 1uF 0603 R = 10K: 1000us GRT188R71E105KE13D PITP301 VCC_3V3 PITP701 VCCO_15_34_ADJ R = 15K: 1500us COTP3TP3 COTP7TP7 15pF 0402 GCM1555C1H150JA16D PITP401 VCCO_0_3V3 PITP801 GND D COTP4TP4 COTP8TP8 D 8.2pF 0402 Rev. 1.0 GJM1555C1H8R2CB01D Power Distribution Sheet7 of 8 Project: PCIe Bridge File: regulator.SchDoc Linköping University 2019-03-27 Author(s): Håkan Gerner Mandus Börjesson 1 2 3 4 1 2 3 4

U7G VCCINT_1V0 VCCINT_1V0 COU7FCOU7GCOU7HCOU7ICOU7JCOU7KCOU7LU7F VCCAUX_1V8 BANK VCCINT DNM DNM Artix-7 CSG325 FPGA BANK VCCAUX PIC2802 PIC2902 PIC3002 PIC3102 PIC3202 PIC3302 F7 L8 Artix-7 CSG325 FPGA VCCAUX_1V8 PIU70F7 VCCINT VCCINT PIU70L8 COC28C28 COC29C29 COC30C30 COC31C31 COC32C32 COC33C33 F9 L12 PIU70F9 VCCINT VCCINT PIU70L12 G12 PIC2801 100uF PIC2901 4.7uF PIC3001 4.7uF PIC3101 0.47uF PIC3201 0.47uF PIC3301 0.47uF G8 M7 VCCAUX PIU70G12 PIU70G8 VCCINT VCCINT PIU70M7 H13 A H7 M11 VCCAUX PIU70H13 A PIU70H7 VCCINT VCCINT PIU70M11 K13 H9 N8 VCCAUX PIU70K13 PIU70H9 VCCINT VCCINT PIU70N8 M13 GND Crossed out: J8 N10 VCCAUX PIU70M13 PIU70J8 VCCINT VCCINT PIU70N10 P13 Mount if XC7A35T is used, otherwise DNM. J12 N12 VCCAUX PIU70P13 PIU70J12 VCCINT VCCINT PIU70N12 VCCINT_1V0 K7 P9 PIU70K7 VCCINT VCCINT PIU70P9 Artix-7 FPGA K11 P11 PIU70K11 VCCINT VCCINT PIU70P11 PIC3402 PIC3502 PIC3602 PIC3702 PIC3802 PIC3902 U7L COC34C34 COC35C35 COC36C36 COC37C37 COC38C38 COC39C39 Artix-7 FPGA BANK VCCIO PIC3401 100uF PIC3501 4.7uF PIC3601 4.7uF PIC3701 0.47uF PIC3801 0.47uF PIC3901 0.47uF U7I Artix-7 CSG325 FPGA VCCO_0_3V3 DNM DNM VCCINT_1V0 E10 BANK VCCBRAM VCCO_0 PIU70E10 GND Artix-7 CSG325 FPGA R10 VCCO_0 PIU70R10 F11 VCCO_0_3V3 VCCINT_1V0 VCCBRAM PIU70F11 G10 VCCBRAM PIU70G10 V15 H11 VCCO_14 PIU70V15 PIC4002 PIC4102 PIC4202 VCCBRAM PIU70H11 U18 VCCO_14 PIU70U18 COC40C40 COC41C41 COC42C42 U8 Artix-7 FPGA VCCO_14 PIU70U8 PIC4001 100uF PIC4101 100uF PIC4201 0.47uF T11 VCCO_14 PIU70T11 U7H R14 VCCO_14 PIU70R14 B P17 B VCCO_14 PIU70P17 GND GND BANK GND L16 Artix-7 CSG325 FPGA VCCO_14 PIU70L16 VCCO_0_3V3 VCCO_15_34_ADJ H10 H15 PIU70H10 GND VCCO_15 PIU70H15 PIC4302 PIC4402 PIC4502 PIC4602 PIC4702 PIC4802 PIC4902 H8 V18 G18 PIU70H8 GND GND PIU70V18 VCCO_15 PIU70G18 COC43C43 COC44C44 COC45C45 COC46C46 COC47C47 COC48C48 COC49C49 H6 V10 E14 PIU70H6 GND GND PIU70V10 VCCO_15 PIU70E14 PIC4301 100uF PIC4401 4.7uF PIC4501 4.7uF PIC4601 0.47uF PIC4701 0.47uF PIC4801 0.47uF PIC4901 0.47uF H5 V1 D17 PIU70H5 GND GND PIU70V1 VCCO_15 PIU70D17 H4 U13 C10 PIU70H4 GND GND PIU70U13 VCCO_15 PIU70C10 H3 U3 B13 PIU70H3 GND GND PIU70U3 VCCO_15 PIU70B13 GND G13 T16 A16 PIU70G13 GND GND PIU70T16 VCCO_15 PIU70A16 G11 T6 PIU70G11 GND GND PIU70T6 VCCO_15_34_ADJ G9 R9 PIU70G9 GND GND PIU70R9 G7 P12 V5 PIU70G7 GND GND PIU70P12 VCCO_34 PIU70V5 PIC5002 PIC5102 PIC5202 PIC5302 PIC5402 PIC5502 PIC5602 G6 P8 T1 PIU70G6 GND GND PIU70P8 VCCO_34 PIU70T1 COC50C50 COC51C51 COC52C52 COC53C53 COC54C54 COC55C55 COC56C56 G5 P2 R4 PIU70G5 GND GND PIU70P2 VCCO_34 PIU70R4 PIC5001 100uF PIC5101 4.7uF PIC5201 4.7uF PIC5301 0.47uF PIC5401 0.47uF PIC5501 0.47uF PIC5601 0.47uF G1 N15 P7 PIU70G1 GND GND PIU70N15 VCCO_34 PIU70P7 F16 N13 M3 PIU70F16 GND GND PIU70N13 VCCO_34 PIU70M3 F10 N11 L6 PIU70F10 GND GND PIU70N11 VCCO_34 PIU70L6 GND C F6 N9 C PIU70F6 GND GND PIU70N9 F4 N7 Artix-7 FPGA PIU70F4 GND GND PIU70N7 VCCO_15_34_ADJ E9 N5 PIU70E9 GND GND PIU70N5 E7 M18 U7K PIU70E7 GND GND PIU70M18 PIC5702 PIC5802 PIC5902 PIC6002 PIC6102 PIC6202 E6 M12 PIU70E6 GND GND PIU70M12 COC57C57 COC58C58 COC59C59 COC60C60 COC61C61 COC62C62 E2 M8 BANK MGTAVTT PIU70E2 GND GND PIU70M8 Artix-7 CSG325 FPGA PIC5701 4.7uF PIC5801 4.7uF PIC5901 0.47uF PIC6001 0.47uF PIC6101 0.47uF PIC6201 0.47uF D12 L13 VMGTAVTT_1V2 PIU70D12 GND GND PIU70L13 D7 L11 A2 PIU70D7 GND GND PIU70L11 MGTAVTT PIU70A2 D4 L7 C1 PIU70D4 GND GND PIU70L7 MGTAVTT PIU70C1 GND D3 L1 E1 PIU70D3 GND GND PIU70L1 MGTAVTT PIU70E1 C15 K14 F3 PIU70C15 GND GND PIU70K14 MGTAVTT PIU70F3 VMGTAVTT_1V2 VMGTAVCC_1V0 C7 K12 G2 PIU70C7 GND GND PIU70K12 MGTAVTT PIU70G2 C6 K8 PIU70C6 GND GND PIU70K8 PIC6302 PIC6402 PIC6502 PIC6602 PIC6702 PIC6802 C2 K4 Artix-7 FPGA PIU70C2 GND GND PIU70K4 COC63C63 COC64C64 COC65C65 COC66C66 COC67C67 COC68C68 B18 J17 PIU70B18 GND GND PIU70J17 PIC6301 4.7uF PIC6401 0.47uF PIC6501 0.47uF PIC6601 4.7uF PIC6701 0.47uF PIC6801 0.47uF B8 J13 U7J PIU70B8 GND GND PIU70J13 B7 J11 PIU70B7 GND GND PIU70J11 B3 J7 BANK MGTAVCC PIU70B3 GND GND PIU70J7 Artix-7 CSG325 FPGA GND GND A18 J3 VMGTAVCC_1V0 PIU70A18 GND GND PIU70J3 D A11 J2 B4 D PIU70A11 GND GND PIU70J2 MGTAVCC PIU70B4 Rev. 1.0 A8 J1 C5 PIU70A8 GND GND PIU70J1 MGTAVCC PIU70C5 Artix-7 Power & Decoupling Sheet8 of 8 A7 H12 E5 PIU70A7 GND GND PIU70H12 MGTAVCC PIU70E5 Project: PCIe Bridge A5 A1 F5 PIU70A5 GND GND PIU70A1 MGTAVCC PIU70F5 File: Decoupling.SchDoc Link ping University 2019-03-27 Artix-7 FPGA Artix-7 FPGA ö Author(s): H kan Gerner GND GND å Mandus Börjesson 1 2 3 4 COR35COP2 COC34 COP3COR40 PAP201PAR3501 PAP202 COC50 PAP301 PAP302PAR4001 COR36PAP203PAR3502 PAP204 PAP303COR41 PAP304PAR4002

PAP205PAR3601 PAP206 PAP305 PAP306PAR4101 COR37PAR3602 PAC3401 PAC4101 PAR4102 PAP207 PAP208 PAP307COR42 PAP308 PAP209PAR3701 PAP2010 COC13PAP309 PAP3010PAR4201 COR38PAP2011PAR3702 PAP2012 PAC3402COC40 PAC4102COC41 PAP3011 PAP3012PAR4202 PAP2013PAR3801 PAP2014 PAP3013 PAP3014 COR39PAR3802 PAC5001 PAC4001 PAP2015 PAP2016 PAP3015COR43 PAP3016 PAP2017PAR3901 PAP2018 PAP3017 PAP3018PAR4301 PAP200 COC28 PAP300 PAP2019PAR3902 PAP2020COTP7 PAP3019 PAP3020PAR4302 PAC5002COC15 PAC4002 PATP701COR20 COR19COR18 PAR801 PAR1701COU2 PAR1601 PAR1501 PAR1401 COC43 PAR802COR21 PAR1702 PAR2002PAR1602COR22 PAR1902PAR1502 PAR1402COR13PAR1802 COR9 COR4 PAC1501 PAC1301 COC2PAU201COC11PAR2001 PAR1901PAU206COC19 PAR1801 COC14 COC10 PAC2801 PAC2802 PAU202COR8 PAU207 PAU205 PAC4301 PAC4302 COR14COR15PAC1502COR16 COR17PAU203 PAU204 PAC1302 COR3 COR7 PAC101 COR10COC18PAL202 PAL201COC3 COU1 PAL102COC4 PAL101COTP1 COR12COC6 PAC102 PAR1202 COC16PAC402PAC1802 PAC1801 PAU1012 PAU1011PAU1010 PAU109 PAU108 PAU107 PAC302COC9 PATP101 PAR1201 PAU1013 PAU106 COR11 PAU1014 PAU105 PAC602 PAC902COC17 PAR1002 PAC1602 PAU1015 PAU104 COL1PAC401 PAU1016 PAU103COL2 PAC301 PAR1001 PAC1601 PAU1017 PAU1025PAU102 COQ1 COTP2PAR1102PAR302 PAR301 PAU1018 COC1COR23PAU101 PAR701 PAC601 PAC901COR5 PAC1702 PAC1701 PAU1019 PAU1020 PAU1021PAU1022 PAU1023 PAU1024 COR2PAR1101 PAR402 PAR401 PAR702 PAQ103 PATP201COTP3 PAR502 PAC802 PAC1002 PAC1402 PAC1902 PAC1102 PAC202 PAC502 PAR102 COC5COC7PAR501 PAC801 PAC501 PAR101 COC8 COR1PATP301COTP5 PAQ101 PAQ102 PAR602 PAC1202 PAC1001 PAC1401 PAC1901 PAC1101COTP6 PAC201 PAC702 PAR202 COR6COC12 PATP501 PAR601 PAC1201 PAR902 PAR901 PAR1302 PAR1301 PAR2201 PAR2202 PAR2101COP1 PAR2102 PAC701 PAR201 COC20COU4 PATP601 COTP4 COR28 PAP107 PAU405 PAC2002 PAU404 PATP401 COR27 PAU406 PAU403 PAR2302 PAP101 PAR2802 PAC2001 COR29 PAU407 PAU409 PAU402 PAR2301 PAP102 PAR2801 PAR2702 PAU408 COC45PAU401 COU3 PAP103 PAR2701 COC52COC51PAU309 PAU308 COC44 PAR2902 PAU3010COC30 COC29 PAU307 PAP104 COR24PAU3011 PAU306 PAR2901 PAU3012 PAU305 PAP105 PAU3013 PAR2401 PAR2402 PAU304 PAU3014 PAU303 PAP106 COTP8 PAU3015 PAU302 COR45PAC2901 PAC3001 PAC4502 PAC4501 PAU3016 PAC5101 PAC5201 PAU301 COC47 PATP801 PAR4501 PAP108PAC4402 PAC4401 COC56COC48COU7 PAC2902 PAC3002 COC49 COC55 COC32PAC5102 PAR4502PAC5202 COC31 PAC4701 PAC5602 PAC4901 PAU70A18 PAU70B18 PAU70C18 PAU70D18 PAU70E18 PAC5501PAU70F18 PAU70G18COC53 PAU70H18 PAU70J18 PAU70K18 PAC4801PAU70L18 PAU70M18 PAU70N18 PAU70P18 PAU70R18 PAU70T18 PAU70U18 PAC4702PAU70V18 PAU70A17 PAU70B17 PAU70C17 PAU70D17 PAU70E17 PAU70F17 PAU70G17 PAC3201PAU70H17 PAU70J17 PAU70K17 PAU70L17COC46 PAU70M17PAC3101 PAU70N17 PAU70P17 PAU70R17 PAU70T17 PAU70U17 PAU70V17 COC33PAU70A16 PAU70B16 PAU70C16PAC5601 PAU70D16 PAU70E16 PAU70F16 PAU70G16 PAU70H16 PAU70J16 PAU70K16 PAU70L16 PAU70M16 PAU70N16 PAU70P16 PAU70R16 PAU70T16 PAU70U16 PAU70V16 PAC4902 PAC5502 PAC4802 PAU70A15 PAU70B15PAC5301 PAU70C15 PAU70D15 PAC5302PAU70E15 PAU70F15 PAU70G15 PAC3202PAU70H15 PAU70J15 PAU70K15 PAU70L15 PAU70M15PAC3102 PAU70N15 PAU70P15 PAU70R15 PAU70T15PAC4602 PAU70U15 PAU70V15 PAR4702 PAU70A14 PAU70B14COC54 PAU70C14 PAU70D14 PAU70E14 PAU70F14 PAU70G14 PAU70H14 PAU70J14 PAU70K14 PAU70L14 PAU70M14 PAU70N14 PAU70P14 PAU70R14 PAU70T14 PAU70U14 PAU70V14 PAR4701 PAU70A13 PAU70B13 PAU70C13 PAU70D13 PAU70E13 PAU70F13 PAU70G13 PAU70H13 PAU70J13 PAU70K13 PAU70L13 PAU70M13 PAU70N13 PAU70P13 PAU70R13 PAU70T13 PAU70U13 PAU70V13 PAC3301 PAC3302 COC37PAC4601 PAR4602 COC67PAU70A12COC38 PAU70B12 PAU70C12 PAU70D12 PAU70E12 PAU70F12 PAU70G12 PAU70H12 PAU70J12 PAU70K12 PAU70L12 PAU70M12 PAU70N12 PAU70P12 PAU70R12 PAU70T12 PAU70U12 PAU70V12 COC66 PAU70A11PAC5401 PAU70B11 PAU70C11PAC5402 PAU70D11 PAU70E11 PAU70F11 PAU70G11 PAU70H11 PAU70J11 PAU70K11 PAU70L11 PAU70M11 PAU70N11 PAU70P11 PAU70R11 PAU70T11 PAU70U11 COR47PAU70V11 PAR4601 COC68PAU70A10 PAU70B10 PAU70C10 PAU70D10 PAU70E10PAC3801 PAU70F10 PAU70G10 PAU70H10 PAU70J10 PAU70K10 PAU70L10PAC3701 PAU70M10 PAU70N10PAC3702 PAU70P10 PAU70R10 PAU70T10 PAU70U10 PAU70V10 COC59 PAC6602 PAC6702PAU70A9 PAU70B9 PAC6701PAU70C9COC39 PAU70D9 PAU70E9 PAU70F9 PAU70G9 PAU70H9 PAU70J9 PAU70K9 PAU70L9 PAU70M9 PAU70N9 PAU70P9 PAU70R9 PAU70T9 PAU70U9 PAU70V9 PAU70A8 PAU70B8 PAU70C8 PAU70D8 PAU70E8PAC3802 PAU70F8 PAU70G8 PAU70H8 PAU70J8 PAU70K8 PAU70L8 PAU70M8 PAU70N8 PAU70P8 PAU70R8 PAU70T8 PAU70U8 PAU70V8 PAU70A7 PAU70B7 PAU70C7PAC6801 PAU70D7 PAU70E7 PAU70F7 PAU70G7 PAU70H7 PAU70J7 PAU70K7 PAU70L7 PAU70M7 PAU70N7 PAU70P7 PAU70R7 PAU70T7 PAU70U7 PAU70V7 PAC5901 PAC6601 COC60 PAU70A6 PAU70B6 PAU70C6 PAU70D6 PAU70E6 PAU70F6 PAU70G6COC62 PAU70H6 PAU70J6 COC61PAU70K6 PAU70L6 PAU70M6 PAU70N6 PAU70P6 PAU70R6 PAU70T6 PAU70U6 PAU70V6 PAU70A5 PAU70B5 PAU70C5PAC6802 PAU70D5 PAU70E5 PAU70F5 PAU70G5 PAU70H5 PAU70J5 PAU70K5PAC3902 PAU70L5 PAU70M5PAC3901 PAU70N5 COC42 PAU70P5 PAU70R5 PAU70T5 PAU70U5 PAU70V5 PAC5902COR44 PAU70A4 PAU70B4 PAU70C4 PAU70D4 PAU70E4 PAU70F4 PAU70G4 PAU70H4 PAU70J4 PAU70K4 PAU70L4 PAU70M4 PAU70N4 PAU70P4 PAC6002PAU70R4 PAU70T4 PAU70U4 PAU70V4 COC65 COC64 COR46PAR4402 PAU70A3 PAU70B3 PAU70C3 PAU70D3 PAU70E3 PAU70F3 PAU70G3 PAU70H3 PAU70J3 PAU70K3 PAU70L3PAC6202 PAU70M3 PAU70N3PAC6102 PAU70P3 PAU70R3 PAU70T3 PAU70U3 PAU70V3 PAU70A2 PAU70B2 PAU70C2 PAU70D2 PAU70E2 PAU70F2 PAU70G2 PAU70H2 PAU70J2 PAU70K2 PAU70L2 PAU70M2 PAU70N2 PAU70P2 PAC6001PAU70R2 PAU70T2 PAU70U2 PAU70V2 COC36COC35PAC6502 COC63 PAC6402 COU5 PAR4401 PAU70A1 PAU70B1 PAU70C1 PAU70D1 PAU70E1 PAU70F1 PAU70G1 PAU70H1 PAU70J1 PAU70K1 PAU70L1PAC6201 PAU70M1 PAU70N1PAC6101 PAU70P1 PAU70R1 PAU70T1 PAU70U1 PAU70V1 PAR3402PAC6501 PAR3401 PAC6302 PAC6401 PAC5702 PAC5802 PAC4202 PAU501 PAU5016 PAC3602 PAC3502PAU502 PAC5701 PAC5801 PAC4201PAU5015 PAC6301 PAU503 COQ3PAU5014 PAU504 COR33PAU5013 COC58COC57PAC3601 PAC3501 PAU505 PAU5012 COR25PAU506 COR31PAQ303PAU5011 PAU507 PAR3302 PAR3301COQ2 COR48PAU5010 COR34 PAU508 PAU509 COC21PAR2501 PAR2502COU6 PAR3102 COR32PAR3101 PAC2101 COR30PAQ302PAR4801 PAQ203 PAR4802 COTP9PAQ301 COC27COC26COC25COC24 COC23 PAU604PAR3201 PAR3202 PAU603 PAC2102 PAR3001 PAR3002 PAU602 PATP901 PAC2701 PAC2601 PAC2501 PAC2401 PAC2301 PAC2201 PAR2601 PAU605 PAQ202PAU601 PAQ201 COP4 PAC2702 PAC2602 PAC2502 PAC2402 PAC2302 PAC2202 PAR2602 COC22 COR26 PAP4075PAP4074 PAP4073 PAP4072 PAP4070PAP4071 PAP4069PAP4068 PAP4067 PAP4058PAP4057PAP4056 PAP4055PAP4054 PAP4053 PAP4052 PAP4051 PAP4050 PAP4048PAP4049 PAP4046 PAP4047PAP4045PAP4044 PAP4043PAP4042 PAP4041 PAP4040 PAP4039PAP4038 PAP4037 PAP4036 PAP4035PAP4034 PAP4033 PAP4032 PAP4031PAP4030 PAP4028PAP4029PAP4026 PAP4027PAP4024 PAP4023 PAP4025PAP4022 PAP4021PAP4020 PAP4019PAP4018 PAP4016PAP4017PAP4014 PAP4015PAP4013PAP4012 PAP4011PAP4010 PAP409 PAP408 PAP407PAP406 PAP404PAP405 PAP402 PAP403PAP401 COR35COP2 COC34 COP3COR40 PAP201PAR3501 PAP202 COC50 PAP301 PAP302PAR4001 COR36PAP203PAR3502 PAP204 PAP303COR41 PAP304PAR4002

Designator Value Manufacturer Part Number Provider Provider Number Comment C1 1uF Murata Electronics GRT188R71E105KE13D Mouser 81-GRT188R71E105KE3D C2 1uF Murata Electronics GRT188R71E105KE13D Mouser 81-GRT188R71E105KE3D C3 10uF Murata Electronics GRM21BR61C106KE15 Mouser 81-GRM21BR61C106KE15 C4 10uF Murata Electronics GRM21BR61C106KE15 Mouser 81-GRM21BR61C106KE15 C5 15pF Murata Electronics GCM1555C1H150JA16D Mouser 81-GCM1555C1H150JA6D C6 10uF Murata Electronics GRM21BR61C106KE15 Mouser 81-GRM21BR61C106KE15 C8 8.2pF Murata Electronics GJM1555C1H8R2CB01D Mouser 81-GJM1555C1H8R2CB01 C9 10uF Murata Electronics GRM21BR61C106KE15 Mouser 81-GRM21BR61C106KE15 C10 1uF Murata Electronics GRT188R71E105KE13D Mouser 81-GRT188R71E105KE3D C11 1uF Murata Electronics GRT188R71E105KE13D Mouser 81-GRT188R71E105KE3D C13 1uF Murata Electronics GRT188R71E105KE13D Mouser 81-GRT188R71E105KE3D C14 1uF Murata Electronics GRT188R71E105KE13D Mouser 81-GRT188R71E105KE3D C15 1uF Murata Electronics GRT188R71E105KE13D Mouser 81-GRT188R71E105KE3D C16 100nF Murata Electronics GCM155R71C104KA55D Mouser 81-GCM155R71C104KA5D C17 100nF Murata Electronics GCM155R71C104KA55D Mouser 81-GCM155R71C104KA5D C18 100nF Murata Electronics GCM155R71C104KA55D Mouser 81-GCM155R71C104KA5D C19 1uF Murata Electronics GRT188R71E105KE13D Mouser 81-GRT188R71E105KE3D C20 0.47uF Murata Electronics GCM188R71C474KA55D Mouser 81-GCM188R71C474KA5D C21 0.47uF Murata Electronics GCM188R71C474KA55D Mouser 81-GCM188R71C474KA5D C22 100nF Murata Electronics GCM155R71C104KA55D Mouser 81-GCM155R71C104KA5D C23 100nF Murata Electronics GCM155R71C104KA55D Mouser 81-GCM155R71C104KA5D C24 100nF Murata Electronics GCM155R71C104KA55D Mouser 81-GCM155R71C104KA5D C25 100nF Murata Electronics GCM155R71C104KA55D Mouser 81-GCM155R71C104KA5D C26 100nF Murata Electronics GCM155R71C104KA55D Mouser 81-GCM155R71C104KA5D C27 100nF Murata Electronics GCM155R71C104KA55D Mouser 81-GCM155R71C104KA5D C28 100uF Murata Electronics GRM32ER61A107ME20 Mouser 81-GRM32ER61A107ME0L C29 4.7uF Murata Electronics GRM188R61C475KE11J Mouser 81-GRM188R61C475KE1J C31 0.47uF Murata Electronics GCM188R71C474KA55D Mouser 81-GCM188R71C474KA5D C32 0.47uF Murata Electronics GCM188R71C474KA55D Mouser 81-GCM188R71C474KA5D C34 100uF Murata Electronics GRM32ER61A107ME20 Mouser 81-GRM32ER61A107ME0L C35 4.7uF Murata Electronics GRM188R61C475KE11J Mouser 81-GRM188R61C475KE1J C37 0.47uF Murata Electronics GCM188R71C474KA55D Mouser 81-GCM188R71C474KA5D C38 0.47uF Murata Electronics GCM188R71C474KA55D Mouser 81-GCM188R71C474KA5D C40 100uF Murata Electronics GRM32ER61A107ME20 Mouser 81-GRM32ER61A107ME0L C41 100uF Murata Electronics GRM32ER61A107ME20 Mouser 81-GRM32ER61A107ME0L C42 0.47uF Murata Electronics GCM188R71C474KA55D Mouser 81-GCM188R71C474KA5D C43 100uF Murata Electronics GRM32ER61A107ME20 Mouser 81-GRM32ER61A107ME0L C44 4.7uF Murata Electronics GRM188R61C475KE11J Mouser 81-GRM188R61C475KE1J C45 4.7uF Murata Electronics GRM188R61C475KE11J Mouser 81-GRM188R61C475KE1J C46 0.47uF Murata Electronics GCM188R71C474KA55D Mouser 81-GCM188R71C474KA5D C47 0.47uF Murata Electronics GCM188R71C474KA55D Mouser 81-GCM188R71C474KA5D C48 0.47uF Murata Electronics GCM188R71C474KA55D Mouser 81-GCM188R71C474KA5D C49 0.47uF Murata Electronics GCM188R71C474KA55D Mouser 81-GCM188R71C474KA5D C50 100uF Murata Electronics GRM32ER61A107ME20 Mouser 81-GRM32ER61A107ME0L C51 4.7uF Murata Electronics GRM188R61C475KE11J Mouser 81-GRM188R61C475KE1J C52 4.7uF Murata Electronics GRM188R61C475KE11J Mouser 81-GRM188R61C475KE1J C53 0.47uF Murata Electronics GCM188R71C474KA55D Mouser 81-GCM188R71C474KA5D C54 0.47uF Murata Electronics GCM188R71C474KA55D Mouser 81-GCM188R71C474KA5D C55 0.47uF Murata Electronics GCM188R71C474KA55D Mouser 81-GCM188R71C474KA5D C56 0.47uF Murata Electronics GCM188R71C474KA55D Mouser 81-GCM188R71C474KA5D C57 4.7uF Murata Electronics GRM188R61C475KE11J Mouser 81-GRM188R61C475KE1J C58 4.7uF Murata Electronics GRM188R61C475KE11J Mouser 81-GRM188R61C475KE1J C59 0.47uF Murata Electronics GCM188R71C474KA55D Mouser 81-GCM188R71C474KA5D C60 0.47uF Murata Electronics GCM188R71C474KA55D Mouser 81-GCM188R71C474KA5D C61 0.47uF Murata Electronics GCM188R71C474KA55D Mouser 81-GCM188R71C474KA5D C62 0.47uF Murata Electronics GCM188R71C474KA55D Mouser 81-GCM188R71C474KA5D C63 4.7uF Murata Electronics GRM188R61C475KE11J Mouser 81-GRM188R61C475KE1J C64 0.47uF Murata Electronics GCM188R71C474KA55D Mouser 81-GCM188R71C474KA5D C65 0.47uF Murata Electronics GCM188R71C474KA55D Mouser 81-GCM188R71C474KA5D C66 4.7uF Murata Electronics GRM188R61C475KE11J Mouser 81-GRM188R61C475KE1J C67 0.47uF Murata Electronics GCM188R71C474KA55D Mouser 81-GCM188R71C474KA5D C68 0.47uF Murata Electronics GCM188R71C474KA55D Mouser 81-GCM188R71C474KA5D L1 2.2uH Sumida CDRH2D14NP-2R2N Mouser 851-CDRH2D14NP-2R2NC L2 2.2uH Sumida CDRH2D14NP-2R2N Mouser 851-CDRH2D14NP-2R2NC P1 JST Sales America Inc. B6B-ZR-SM3-TF JTAG P2 Harwin M50-3611042 Mouser 855-M50-3611042 M50-361 P3 Harwin M50-3611042 Mouser 855-M50-3611042 M50-361 Q1 Infineon Technologies BSS806NEH6327XTSA1 Mouser 726-BSS806NEH6327XTS BSS806 Q2 Infineon Technologies BSS806NEH6327XTSA1 Mouser 726-BSS806NEH6327XTS BSS806 Q3 Infineon Technologies BSS806NEH6327XTSA1 Mouser 726-BSS806NEH6327XTS BSS806 R1 100K R2 100K R3 0 R5 390K R6 150K R7 100K R8 39K R9 47K R10 10K R11 15K R12 4.7K R13 33K R14 33K R15 15K R16 10K R17 33K R18 2.7K R19 1.5K R20 220 R21 100K R22 100K R23 10K R24 10K R25 10K R26 10K R27 10K R28 10K R29 10K R31 10K R33 10K R34 100 R45 330 R46 4.7K R47 4.7K R48 10K U1 Texas Instruments LM26480QSQ-CF/NOPB Mouser 926-LM26480QSQCFNOPB LM26480 U2 Texas Instruments TLV75801PDRVR Mouser 595-TLV75801PDRVR TLV75801 U3 Texas Instruments TS3A5018PWR Mouser 595-TS3A5018PWR TS3A5018 U4 Microchip Technology SST26VF016B-104I/MF Mouser 579-ST26VF016B104IMF SST26VF016B U5 NXP Semiconductors SC18IS602BIPW/S8HP Mouser 771-SC18IS602BIPW8HP SC18IS602B U6 Microchip Technology / AtmelAT24C04D-STUM-T Mouser 556-AT24C04D-STUM-T AT24C04D U7 Xilinx Inc. XC7A12T-2CSG325C Artix-7 FPGA A B C D E

View from Top side (Scale 3)

21 21 19 1 12 R44 1 19 19 19 6 6 11 7 2 13 13 33 32 3 C7 9 2 10 6 19 13 1 13 1 5 22 1

7 7 20 13 5 19 19 1 1 29 28 34 5 22 1 22 17 1 5 7 7 27 1 18 14 R4 31 5 2 4 C12 30 9 5 15 16 8

2 26 11 2 7 2

Line # Designator Value Part Number Comment Line # Designator Value Part Number Comment C1, C2, C10, C11, C13, C14, 29 U2 TLV75801PDRVR TLV75801 1 1uF GRT188R71E105KE13D C15, C19 30 U3 TS3A5018PWR TS3A5018 2 C3, C4, C6, C9 10uF GRM21BR61C106KE15 31 U4 SST26VF016B-104I/MF SST26VF016B 3 C5 15pF GCM1555C1H150JA16D 32 U5 SC18IS602BIPW/S8HP SC18IS602B 4 C8 8.2pF GJM1555C1H8R2CB01D 33 U6 AT24C04D-STUM-T AT24C04D 5 C22, C23, C24, C25, C26, C27 100nF GCM155R71C104KA55D 34 U7 XC7A12T-2CSG325C Artix-7 FPGA 6 C21, C49, C59 0.47uF GCM188R71C474KA55D 3 7 C28, C34, C40, C41, C43, C50 100uF GRM32ER61A107ME20 3 8 C63 4.7uF GRM188R61C475KE11J 9 L1, L2 2.2uH CDRH2D14NP-2R2N 10 P1 B6B-ZR-SM3-TF JTAG 11 P2, P3 M50-3611042 M50-361 12 Q1 BSS806NEH6327XTSA1 BSS806 13 R1, R2, R7, R21, R22 100K 14 R3 0 15 R5 390K 16 R6 150K 17 R8 39K 18 R9 47K R16, R23, R26, R27, R28, 19 10K R29, R48 4 20 R15 15K 4 21 R46, R47 4.7K 22 R13, R14, R17 33K 26 R34 100 27 R45 330 28 U1 LM26480QSQ-CF/NOPB LM26480

A B C D E A B C D E

View from Bottom side (Scale 3)

R35 R36 R37 R38 R39 1 8 1 6 6 6

6 6 6

21 19 20 C33 6 5 8 6 5 5 19 6 8 6 6 25 C36 24 8 6 6 C39 23 6 6 8 C30 6 19 6 8 6 8 8 19 19 6 8 R32 R30 6 2 R40 R41 R42 R43 12 12 2

Line # Designator Value Part Number Comment 5 C16, C17, C18 100nF GCM155R71C104KA55D C20, C31, C32, C37, C38, C42, C46, C47, C48, C53, 6 0.47uF GCM188R71C474KA55D C54, C55, C56, C60, C61, C62, C64, C65, C67, C68 C29, C35, C44, C45, C51, 8 4.7uF GRM188R61C475KE11J C52, C57, C58, C66 3 12 Q2, Q3 BSS806NEH6327XTSA1 BSS806 3 19 R10, R24, R25, R31, R33 10K 20 R11 15K 21 R12 4.7K 23 R18 2.7K 24 R19 1.5K 25 R20 220

4 4

A B C D E A B C D E

View from Top side (Scale 3)

1 TP8 TP9 1 TP4

TP1

TP6

TP7

2 TP2 TP3 TP5 2

Top Layer (Scale 1:1) Test point Net name Voltage TP1 VCCINT_1V0 1.0V 3 TP2 VCCAUX_1V8 1.8V 3 TP3 VCC_3V3 3.3V TP4 VCCO_0_3V3 3.3V TP5 VMGTAVTT_1V2 1.2V Bottom Layer (Scale 1:1) TP6 VMGTAVCC_1V0 1.0V TP7 VCCO_15_34_ADJ Adjustable TP8 GND GND TP9 EEPROM_WP 3.3V (Pull-up)

4 4

A B C D E Bibliography

Appendix C - Test plan

Nr. Test Pass Fail Comment 1 Manufacturing and mounting 1.1 Pre-component mounting 1.1.1 Perform brief visual inspection of PCB 1.1.2 Measure continuity on sample nets 1.1.3 Test for short circuit on power nets 1.1.4 Measure trace impedance 1.2 Post-component mount 1.2.1 Test for short circuit on power nets 1.2.2 Verify resistor values on power supply 1.2.3 Visual inspection of solder joints 1.3 PCB under power 1.3.1 Measure current draw (limit supply) 1.3.2 Check supply voltage levels 1.3.3 Check power on sequence 1.3.4 Measure SMBus logic level before/after level conversion 1.3.5 Verify unused pins on M.2 connector are not live 2 Debug test procedure 2.1 FPGA system 2.1.1 Check JTAG connectivity 2.1.2 Test setting LVDS/CMOS pins HIGH one at a time 2.1.3 Test LDO voltage level control 2.2 SMBus 2.2.1 Identify EEPROM 2.2.2 Write data to EEPROM 2.2.3 Identify I2C-SPI Bridge 2.2.4 Set/read pins on bridge 2.2.5 Write test data to Flash memory and read back 2.2.6 Write FPGA bitstream to ﬂash memory 2.2.7 Boot FPGA from Flash memory 2.3 PCI Express 2.3.1 Upload small skecth with PCI Ex- press IP core and verify that the device is detected by the platform