TMS320DM365 www.ti.com SPRS457E–MARCH 2009–REVISED JUNE 2011 TMS320DM365 Digital Media System-on-Chip (DMSoC) Check for Samples: TMS320DM365 1 TMS320DM365 Digital Media System-on-Chip (DMSoC) 1.1 Features 12 • Highlights – Support for 32-Bit and 16-Bit – High-Performance Digital Media (Thumb® Mode) Instruction Sets System-on-Chip (DMSoC) – DSP Instruction Extensions and Single Cycle – Up to 300-MHz ARM926EJ-S Clock Rate MAC – Two Video Image Co-processors – ARM® Jazelle® Technology (HDVICP, MJCP) Engines – Embedded ICE-RT Logic for Real-Time – Supports a Range of Encode, Decode, and Debug Video Quality Operations • ARM9 Memory Architecture – Video Processing Subsystem – 16K-Byte Instruction Cache • HW Face Detect Engine – 8K-Byte Data Cache • Resize Engine from 1/16x to 8x – 32K-Byte RAM • 16-Bit Parallel AFE (Analog Front-End) – 16K-Byte ROM Interface Up to 120 MHz – Little Endian • 4:2:2 (8-/16-bit) Interface • Two Video Image Co-processors • 8-/16-bit YCC and Up to 24-Bit RGB888 (HDVICP, MJCP) Engines Digital Output – Support a Range of Encode and Decode • 3 DACs for HD Analog Video Output Operations, up to D1 on 216-MHz device and • Hardware On-Screen Display (OSD) up to 720p on the 270- and 300-MHz parts – Capable of 720p 30fps H.264 video – H.264, MPEG4, MPEG2, MJPEG, JPEG, processing WMV9/VC1 Note: 216-MHz is only capable of D1 • Video Processing Subsystem processing – Front End Provides: – Peripherals include EMAC, USB 2.0 OTG, • HW Face Detect Engine DDR2/NAND, 5 SPIs, 2 UARTs, 2 • Hardware IPIPE for Real-Time Image MMC/SD/SDIO, Key Scan Processing – 8 Different Boot Modes and Configurable – Resize Engine Power-Saving Modes – Resize Images From 1/16x to 8x – Pin-to-pin and software compatible with – Separate Horizontal/Vertical DM368 Control – Extended temperature (-40ºC – 85ºC) – Two Simultaneous Output Paths available for 300-MHz device • IPIPE Interface (IPIPEIF) – 3.3-V and 1.8-V I/O, 1.2-V/1.35-V Core • Image Sensor Interface (ISIF) and CMOS – 338-Pin Ball Grid Array at 65nm Process Imager Interface Technology • 16-Bit Parallel AFE (Analog Front End) • High-Performance Digital Media Interface Up to 120 MHz System-on-Chip (DMSoC) • Glueless Interface to Common Video – 216-, 270-, 300-MHz ARM926EJ-S Clock Rate Decoders – Fully Software-Compatible With ARM9™ • BT.601/BT.656/BT.1120 Digital YCbCr – Extended temperature available for 300-MHz 4:2:2 (8-/16-Bit) Interface device • Histogram Module • ARM926EJ-S™ Core • Lens distortion correction module (LDC) 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2009–2011, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. TMS320DM365 SPRS457E–MARCH 2009–REVISED JUNE 2011 www.ti.com • Hardware 3A statistics collection module • Four 64-Bit General-Purpose Timers (each (H3A) configurable as two 32-bit timers) – Back End Provides: • One 64-Bit Watch Dog Timer • Hardware On-Screen Display (OSD) • Two UARTs (One fast UART with RTS and CTS • Composite NTSC/PAL video encoder Flow Control) output • Five Serial Port Interfaces (SPI) each with two • 8-/16-bit YCC and Up to 24-Bit RGB888 Chip-Selects Digital Output • One Master/Slave Inter-Integrated Circuit • 3 DACs for HD Analog Video Output (I2C) Bus™ • LCD Controller • One Multi-Channel Buffered Serial Port • BT.601/BT.656 Digital YCbCr 4:2:2 (McBSP) (8-/16-Bit) Interface – I2S • Analog-to-Digital Convertor (ADC) – AC97 Audio Codec Interface • Power Management and Real Time Clock – S/PDIF via Software Subsystem (PRTCSS) – Standard Voice Codec Interface (AIC12) – Real Time Clock – SPI Protocol (Master Mode Only) • 16-Bit Host-Port Interface (HPI) – Direct Interface to T1/E1 Framers • 10/100 Mb/s Ethernet Media Access Controller – Time Division Multiplexed Mode (TDM) (EMAC) - Digital Media – 128 Channel Mode – IEEE 802.3 Compliant • Four Pulse Width Modulator (PWM) Outputs – Supports Media Independent Interface (MII) • Four RTO (Real Time Out) Outputs – Management Data I/O (MDIO) Module • Up to 104 General-Purpose I/O (GPIO) Pins • Key Scan (Multiplexed with Other Device Functions) • Voice Codec • Boot Modes • External Memory Interfaces (EMIFs) – On-Chip ARM ROM Bootloader (RBL) to Boot – DDR2 and mDDR SDRAM 16-bit wide EMIF From NAND Flash, MMC/SD, UART, USB, With 256 MByte Address Space (1.8-V I/O) SPI, EMAC, or HPI – Asynchronous16-/8-bit Wide EMIF (AEMIF) – AEMIF (NOR and OneNAND) • Flash Memory Interfaces • Configurable Power-Saving Modes – NAND (8-/16-bit Wide Data) • Crystal or External Clock Input (typically – 16 MB NOR Flash, SRAM 19.2 MHz, 24 MHz, 27 MHz or 36 MHz) – OneNAND(16-bit Wide Data) • Flexible PLL Clock Generators • Flash Card Interfaces • Debug Interface Support – Two Multimedia Card (MMC) / Secure Digital – IEEE-1149.1 (JTAG™) (SD/SDIO) Boundary-Scan-Compatible – SmartMedia/xD – ETB (Embedded Trace Buffer) with 4K-Bytes Trace Buffer memory • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels) – Device Revision ID Readable by ARM • USB Port with Integrated 2.0 High-Speed PHY • 338-Pin Ball Grid Array (BGA) Package that Supports (ZCE Suffix), 0.65-mm Ball Pitch – USB 2.0 High-Speed Device • 65nm Process Technology – USB 2.0 High-Speed Host (mini-host, • 3.3-V and 1.8-V I/O, 1.2-V/ 1.35-V Internal supporting one external device) • Community Resources – USB On The Go (HS-USB OTG) – TI E2E Community – TI Embedded Processors Wiki 2 TMS320DM365 Digital Media System-on-Chip (DMSoC) Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 www.ti.com SPRS457E–MARCH 2009–REVISED JUNE 2011 1.2 Description Developers can now deliver pixel-perfect images at up to 720p H.264 at 30fps in their digital video designs without concerns of video format support, constrained network bandwidth, limited system storage capacity or cost with the new TMS320DM365 digital media processor based on DaVinci technology from Texas Instruments Incorporated (TI). With multi-format HD video, the DM365 also features a suite of peripherals saving developers on system costs. This ARM9-based DM365 device offers speeds up to 300 MHz and supports production-qualified H.264, MPEG-4, MPEG-2, MJPEG and VC1/WMV9 codecs providing customers with the flexibility to select the right video codec for their application. These codecs are driven from video accelerators offloading compression needs from the ARM core so that developers can utilize the most performance from the ARM for their application. Video surveillance designers achieve greater compression efficiency providing more storage without straining the network bandwidth. Developers of media playback and camera-driven applications, such as video doorbells, digital signage, digital video recorders, portable media players and more can ensure interoperability as well as product scalability by taking advantage of the full suite of codecs supported on the DM365. Along with multi-format HD video, the DM365 enables seamless interface to most additional external devices required for video applications. The image sensor interface is flexible enough to support CCD, CMOS, and various other interfaces such as BT.656, BT1120. The DM365 also offers a high level of integration with HD display support including, 3 built-in 10-bit HD Analog Video Digital to Analog Converters (DACs), DDR2/mDDR, Ethernet MAC, USB 2.0, integrated audio, Host Port Interface (HPI), Analog to Digital Converter, and many more features saving developers on overall system costs as well as real estate on their circuit boards allowing for a slimmer, sleeker design. Copyright © 2009–2011, Texas Instruments Incorporated TMS320DM365 Digital Media System-on-Chip (DMSoC) 3 Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E–MARCH 2009–REVISED JUNE 2011 www.ti.com 1.3 Functional Block Diagram Figure 1-1 shows the functional block diagram of the TMS320DM365 device. 16Bit DDR2 16-Bit Camera ISIF IPIPE EDMA DDR2/ AFE Resizer Controller mDDR 3A FaceDet LensDist NAND/ VideoFE Buffer NAND/SM OneNAND/ 8/16Bit NORFlash, SDTV/HDTV 3Ch Memory AnalogVideo I/F SmartMedia/ DAC Video xD OSD 16Bit Digital Encoder RGB/YUV VideoBE HPI HostCPU VPSS DMA/DataandConfigurationBus ARMINTC USB2.0HSw/OTG MMC/SD(x2) ARM926EJ-S SPI(x5) HDVICP MJCP UART(x2) I2C I-Cache RAM 16KB 32KB Timer(x4-64b) WDT(x1-64b) D-Cache ROM System 8KB 16KB GIO I/O PWM(x4) Interface RTO McBSP EMAC ADC KeyScan JTAG CLOCKCtrl PRTCSS VoiceCodec I/F PLL 19.2MHz,24MHz 32.768 PMIC/ 27MHzor36MHz kHz SW Figure 1-1. Functional Block Diagram 4 TMS320DM365 Digital Media System-on-Chip (DMSoC) Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 www.ti.com SPRS457E–MARCH 2009–REVISED JUNE 2011 1 TMS320DM365 Digital Media System-on-Chip 6 Peripheral Information and Electrical (DMSoC) ................................................... 1 Specifications .......................................... 76 1.1 Features .............................................. 1 6.1 Parameter Information Device-Specific Information .....................................................