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HOT APPLICATIONS: PCI, Plug and Play, PCMCIA HOT APPLICATIONS: PCI, Plug and Play, PCMCIA PCI (Peripheral Component Interconnect) Plug and Play ISA PCMCIA Designing for High-Volume, Low-Cost Computer Solutions (PCI, Plug and Play, PCMCIA) — 1 © Copyright 1995 by Xilinx, Inc. All rights reserved. All trademarks are the property of the respective owners. Peripheral Component Interconnect (PCI) Computer Solutions (PCI, Plug and Play, PCMCIA) — 2 © Copyright 1995 by Xilinx, Inc. All rights reserved. All trademarks are the property of the respective owners. Why PCI? System Mother Board New applications—like MPU Local Bus video—demand higher Cache bandwidth Host-PCI DRAM I/O Graphics I/O SCSI Bridge Existing ISA architecture too Controller Controller slow Primary PCI Bus – Stuck with slow, 8-/16-bit performance PCI-PCI PCI - Standard Bus Bridge (ISA) – Bottleneck for I/O-intensive Bridge applications Secondary PCI Bus ISA Bus I/O LAN I/O Modem Controller Controller LAN Modem Controller Multi-Function PCI Card ISA Cards Computer Solutions (PCI, Plug and Play, PCMCIA) — 3 © Copyright 1995 by Xilinx, Inc. All rights reserved. All trademarks are the property of the respective owners. PCI Technical Challenges Input/Output Input/Output Drive Timing PCI Compliance Protocol Bus Timing Loading 100% Compliance REQUIRED for: – Add-in boards to be plugged into ANY PCI system – System to accept PCI add-in card from ANY manufacturer Computer Solutions (PCI, Plug and Play, PCMCIA) — 4 © Copyright 1995 by Xilinx, Inc. All rights reserved. All trademarks are the property of the respective owners. “Reflective-Wave” Switching PCI BUS is unterminated, key parameter is ZO Signals must switch on first reflected wave Incident Reflected Wave Wave VTH / 2 tPROP Maximum Propagation Delay tPROP = 30 - 11 - 7 - 2 = 10 ns Signal propagation delays availability of signals Signals are compliant when they follow a switching trajectory that defines both current and voltage (V/I Curves) Computer Solutions (PCI, Plug and Play, PCMCIA) — 5 © Copyright 1995 by Xilinx, Inc. All rights reserved. All trademarks are the property of the respective owners. Bus Loading Loading – PCI BUS is unterminated, key parameter is capacitance – Maximum limit is 10 loads @ 10 pF each per bus pin – Add-on cards restricted to 2 loads max – Single device pin per board pin – Expansion board (bridge) is needed to exceed max limit Xilinx input capacitance is measured to be less than 10 pF per device pin for plastic packages – EPLDs: XC7300-10 and faster in PQFP – FPGAs: XC3100A-2, XC4000E-3 and faster in PQFP Computer Solutions (PCI, Plug and Play, PCMCIA) — 6 © Copyright 1995 by Xilinx, Inc. All rights reserved. All trademarks are the property of the respective owners. Input/Output Drive Specifications PCI I/O drive is defined to correctly manage signal reflection within the impedance requirements of the PCI bus PCI defines a region on a V/I diagram with specific measurement points 5.0 5.0 4.0 4.0 V V OUT 3.0 OUT 3.0 2.4V 3.1V -2mA 2.2V -142mA 2.0 95mA 2.0 1.4V 0.71V -44mA 1.0 0.55V 206mA 1.0 24mA 100 200 300 400 -100 -200 IOL (mA) IOH (mA) Computer Solutions (PCI, Plug and Play, PCMCIA) — 7 © Copyright 1995 by Xilinx, Inc. All rights reserved. All trademarks are the property of the respective owners. Composite Input / Output Timing 30 nsec Clock t val t + t t del + t skew t su Time delays ckq on 11 nsec 12 nsec 7 nsec D Q PCI Speedway D Q D Q Clock t val = 11 nsec t su = 7 nsec t h = 0 nsec Computer Solutions (PCI, Plug and Play, PCMCIA) — 8 © Copyright 1995 by Xilinx, Inc. All rights reserved. All trademarks are the property of the respective owners. Detailed PCI Timing Specifications CLOCK tval tsu OUTPUT INPUT th toff 3-State OUTPUT ton 5 V Signaling 3.3 V Signaling Units Parameter min max min max th 0 0 nsec tsu (bussed) 7 7 nsec tsu (point-to-point) 10 12 nsec tval (bussed) 2 11 2 11 nsec tval (point-to-point) 2 12 2 11 nsec ton 2 2 nsec toff 28 28 nsec REFERENCE Computer Solutions (PCI, Plug and Play, PCMCIA) — 9 © Copyright 1995 by Xilinx, Inc. All rights reserved. All trademarks are the property of the respective owners. PCI Three-state Buffer Control: The Often-Missed Critical Issue Turn-around cycles (high-impedance state) inserted at each point where signal drive is passed from one agent to another Agents require multiple, independent output enables for different signal classes Most programmable logic devices have enough output enables for basic PCI interface — but are there enough for the rest ofyour logic? Class of Signals Signal Name Initiator/Target Target Address Data AD[31:0] Ö Ö Framing FRAME#, CBE[3:0]# Ö Parity PAR Ö Ö Parity Error PERR# Ö Ö Master Handshake IRDY# Ö Target Handshake TRDY#,DEVSEL#,STOP# Ö Ö Total 6 4 Computer Solutions (PCI, Plug and Play, PCMCIA) — 10 © Copyright 1995 by Xilinx, Inc. All rights reserved. All trademarks are the property of the respective owners. Xilinx PCI Compliant Solutions XC7300 XC3100A-2 XC4000E-3 Issue -10/7/5 XC3400 XC4400 Design Method PAL/CPLD FPGA/ASIC Process CMOS CMOS Technology EPROM SRAM PCI Compliance 100% 100% 100% Gate Density up to 5K up to 7.5K up to 25K Target Interface Ö Ö Ö Initiator Interface Simple Simple Full Configuration Internal/ Internal/ Full Registers External External Internal Signaling 5/3.3V 5V Bus Width 32 bit 32 bit 32/64 bit Computer Solutions (PCI, Plug and Play, PCMCIA) — 11 © Copyright 1995 by Xilinx, Inc. All rights reserved. All trademarks are the property of the respective owners. PCI Target in XC3164A-2 FPGA Worst Case Design at 33 MHz LOCAL DEVSEL# asserted at CONTROL clock 5 LOC_REQn LOC_GNTn TRDY# asserted at ADDR[31:24] clock 6 EPLD SRWE[3:0]n SRWE[3:0]n Requires 15 ns SRAMs SRCSn SRCSn CONTROL for one clock burst PCI INTERFACE SROEn 32 BIT SROEn TARGET Responds to memory & XC3164A SRAM CPU configuration CBE ADDRESS ADDR[23:0] ADDR ADDR Asserts STOP# on XCVR address counter PCI DATA DATA overflow and initiator read wait states On the CD-ROM Computer Solutions (PCI, Plug and Play, PCMCIA) — 12 © Copyright 1995 by Xilinx, Inc. All rights reserved. All trademarks are the property of the respective owners. XC3164A PCI Interface Block Diagram AD_REG[3:0] UP CNTR SR_ADDR[4:0] PARITY PCI_PAR Q D GENERATE NOMORE CLK AD_REG[23:4] D Q SR_ADDR[23:4] CLK SR_REG PCI_AD[31:0] Q D Q D CLK CLK AD_REG CLK Q D Q SR_DATA D CLK BA_REG [31:24] PCI_REQ CBE_REG COMPARE PCI_CBE[3:0] D Q LOC_REQn CLK ARBITER LOC_GNTn FRAME_REGn CMD DECODE IRDY_REGn FRAMEn IRDYn INC_ADDR SRCSn DEVSELn PCI_GNT PIPCON SRAM CONTROL SROEn STOPn WRGATE TRDYn SRWE[3:0]n IDSEL CRITPATH Pipelined data path De-multiplexed address/data bus Computer Solutions (PCI, Plug and Play, PCMCIA) — 13 © Copyright 1995 by Xilinx, Inc. All rights reserved. All trademarks are the property of the respective owners. XC4000E and PCI XC4000E FPGA 100% PCI compliant On-chip RAM for – Configuration memory Input Output Other FIFO FIFO Application – FIFOs Logic High-density designs – Target/Initiator in a single device Cost-reduction strategy PCI Configuration Registers – PCI compliant XC4400 HardWire gate arrays PCI Target/Initiator – 100% drop-in compatible Interface with XC4000E Computer Solutions (PCI, Plug and Play, PCMCIA) — 14 © Copyright 1995 by Xilinx, Inc. All rights reserved. All trademarks are the property of the respective owners. MuTech Video Digitizer PCI Card Required 100% PCI compliance using XC3195A Integrated specific features not found in PCI chipsets Contains PCI interface, capture control, memory control, etc. Computer Solutions (PCI, Plug and Play, PCMCIA) — 15 © Copyright 1995 by Xilinx, Inc. All rights reserved. All trademarks are the property of the respective owners. PCI Special Interest Group PCI Test Board Tests PCI system compliance Computer Solutions (PCI, Plug and Play, PCMCIA) — 16 © Copyright 1995 by Xilinx, Inc. All rights reserved. All trademarks are the property of the respective owners. Xilinx PCI Support Xilinx is an active member of PCI Special Interest Group (PCI-SIG) PCI market backgrounder PCI compliance checklists XC7300 XC3100A XC4000E Compliance 3Q XC7300 EPLD App. Note/Design Checklist Ö Ö ‘95 – VHDL and ABEL Target App Note XC3164A-2 FPGA App. and Design Files Ö Ö Note/Design Initiator/Target 3Q 3Q – Verilog source files for App Note ‘95 ‘95 Exemplar Logic CORE, or – VIEWlogic schematics EMAIL: [email protected] – Literature requests – Technical questions Computer Solutions (PCI, Plug and Play, PCMCIA) — 17 © Copyright 1995 by Xilinx, Inc. All rights reserved. All trademarks are the property of the respective owners. Plug and Play ISA Interface Computer Solutions (PCI, Plug and Play, PCMCIA) — 18 © Copyright 1995 by Xilinx, Inc. All rights reserved. All trademarks are the property of the respective owners. Why Plug and Play ISA? NoNo mechanismmechanism forfor allocatingallocating resourcesresources amongamong ISAISA cardscards inin aa systemsystem CurrentCurrent ISAISA cardscards requirerequire “jumper”“jumper” toto controlcontrol memorymemory andand I/OI/O space,space, toto steersteer DMADMA andand interruptsinterrupts OtherOther busbus standardsstandards areare alreadyalready “Plug“Plug andand Play”Play” (NuBus,(NuBus, MicroMicro Channel,Channel, EISA,EISA, PCI)PCI) PlugPlug andand PlayPlay ISAISA retrofitsretrofits samesame capabilitiescapabilities intointo thethe industry’sindustry’s mostmost popularpopular busbus standardstandard PlugPlug andand PlayPlay ISAISA cardscards willwill co-existco-exist withwith today’stoday’s ISAISA cardscards WindowsWindows ‘95‘95 andand PlugPlug andand PlayPlay BIOSBIOS comingcoming soonsoon Computer Solutions (PCI, Plug and Play, PCMCIA) — 19 © Copyright 1995 by Xilinx, Inc. All rights reserved. All trademarks are the property of the respective owners. Plug and Play ISA Technical Challenges No significant technical challenges (except understanding the specification) Every ISA board has different interface requirements Need low-cost solution for high-volume ISA market Computer Solutions (PCI, Plug and Play, PCMCIA) — 20 © Copyright 1995 by Xilinx, Inc.
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