DOCSLIB.ORG

Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH)

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet November 2008 Reference Number: 313953 Revision: 002 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Intel® 3000 and 3010 chipsets may contain design defects or errors known as errata, which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Intel, Pentium, Intel Celeron, Intel 6700PXH 64-bit PCI Hub, Intel I/O Controller Hub 7 (Intel ICH7), and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright© 2006, Intel Corporation 2 Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Contents 1 Introduction............................................................................................................... 13 1.1 Terminology ..................................................................................................... 15 1.2 Reference Documents ........................................................................................ 16 1.3 MCH Overview .................................................................................................. 17 1.3.1 Host Interface........................................................................................ 17 1.3.2 System Memory Interface ....................................................................... 17 1.3.3 Direct Media Interface (DMI).................................................................... 18 1.3.4 PCI Express* Interface(s)........................................................................ 18 1.3.5 System Interrupts .................................................................................. 19 1.3.6 MCH Clocking ........................................................................................ 19 1.3.7 Power Management ................................................................................ 20 2 Signal Description....................................................................................................... 21 2.1 Host Interface Signals........................................................................................ 23 2.2 DDR2 DRAM Channel A Interface......................................................................... 25 2.3 DDR2 DRAM Channel B Interface......................................................................... 26 2.4 DDR2 DRAM Reference and Compensation............................................................ 27 2.5 PCI Express* Interface Signals............................................................................ 27 2.6 Clocks, Reset, and Miscellaneous ......................................................................... 28 2.7 Direct Media Interface (DMI)............................................................................... 28 2.8 Power, Ground.................................................................................................. 29 2.9 Reset States and Pull-up/Pull-downs .................................................................... 29 3 MCH Register Description ............................................................................................ 33 3.1 Register Terminology ......................................................................................... 34 3.2 Platform Configuration ....................................................................................... 35 3.3 Configuration Mechanism ................................................................................... 37 3.3.1 Standard PCI Configuration Mechanism ..................................................... 37 3.3.2 PCI Express Enhanced Configuration Mechanism......................................... 38 3.4 Routing Configuration Accesses ........................................................................... 39 3.4.1 Internal Device Configuration Accesses ..................................................... 41 3.4.2 Bridge Related Configuration Accesses ...................................................... 41 3.5 I/O Mapped Registers ........................................................................................ 42 3.5.1 CONFIG_ADDRESS—Configuration Address Register ................................... 43 3.5.2 CONFIG_DATA—Configuration Data Register .............................................. 44 4 Host Bridge Registers (Device 0, Function 0).................................................................. 45 4.1 Configuration Register Details (D0:F0) ................................................................. 47 4.1.1 VID—Vendor Identification (D0:F0)........................................................... 47 4.1.2 DID—Device Identification (D0:F0) ........................................................... 47 4.1.3 PCICMD—PCI Command (D0:F0).............................................................. 48 4.1.4 PCISTS—PCI Status (D0:F0) .................................................................... 49 4.1.5 RID—Revision Identification (D0:F0) ......................................................... 50 4.1.6 CC—Class Code (D0:F0).......................................................................... 50 4.1.7 MLT—Master Latency Timer (D0:F0) ......................................................... 50 4.1.8 HDR—Header Type (D0:F0) ..................................................................... 51 4.1.9 SVID—Subsystem Vendor Identification (D0:F0)......................................... 51 4.1.10 SID—Subsystem Identification (D0:F0) ..................................................... 51 4.1.11 CAPPTR—Capabilities Pointer (D0:F0) ....................................................... 52 4.1.12 EPBAR—Egress Port Base Address (D0:F0) ................................................ 52 4.1.13 MCHBAR—MCH Memory Mapped Register Range Base Address (D0:F0) ......... 53 Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet 3 4.1.14 PCIEXBAR—PCI Express Register Range Base Address (D0:F0) .....................53 4.1.15 DMIBAR—Root Complex Register Range Base Address (D0:F0) .....................55 4.1.16 DEVEN—Device Enable (D0:F0) ................................................................56 4.1.17 DEAP - DRAM Error Address Pointer (D0:F0)...............................................56 4.1.18 DERRSYN - DRAM Error Syndrome (D0:F0) ................................................57 4.1.19 DERRDST - DRAM Error Destination (D0:F0)...............................................57 4.1.20 PAM0—Programmable Attribute Map 0 (D0:F0)...........................................58 4.1.21 PAM1—Programmable Attribute Map 1 (D0:F0)...........................................59 4.1.22 PAM2—Programmable Attribute Map 2 (D0:F0)...........................................59 4.1.23 PAM3—Programmable Attribute Map 3 (D0:F0)...........................................60 4.1.24 PAM4—Programmable Attribute Map 4 (D0:F0)...........................................60 4.1.25 PAM5—Programmable Attribute Map 5 (D0:F0)...........................................61 4.1.26 PAM6—Programmable Attribute Map 6 (D0:F0)...........................................61 4.1.27 LAC—Legacy Access Control (D0:F0) .........................................................62 4.1.28 REMAPBASE - Remap Base Address Register ..............................................63 4.1.29 REMAPLIMIT - Remap Limit Address Register..............................................63 4.1.30 TOLUD—Top of Low Usable DRAM (D0:F0) .................................................64 4.1.31 SMRAM—System Management RAM Control (D0:F0)....................................64 4.1.32 ESMRAMC—Extended System Management RAM Control (D0:F0) ..................65 4.1.33 TOM - Top of Memory..............................................................................66 4.1.34 ERRSTS—Error Status (D0:F0) .................................................................67 4.1.35 ERRCMD—Error Command (D0:F0) ...........................................................68 4.1.36 SMICMD - SMI Command (D0:F0).............................................................69 4.1.37 SCICMD - SCI Command (D0:F0) .............................................................69 4.1.38 SKPD—Scratchpad Data (D0:F0)...............................................................70
Load more

Recommended publications
  • Computer Organization and Architecture Designing for Performance Ninth Edition
    COMPUTER ORGANIZATION AND ARCHITECTURE DESIGNING FOR PERFORMANCE NINTH EDITION William Stallings Boston Columbus Indianapolis New York San Francisco Upper Saddle River Amsterdam Cape Town Dubai London Madrid Milan Munich Paris Montréal Toronto Delhi Mexico City São Paulo Sydney Hong Kong Seoul Singapore Taipei Tokyo Editorial Director: Marcia Horton Designer: Bruce Kenselaar Executive Editor: Tracy Dunkelberger Manager, Visual Research: Karen Sanatar Associate Editor: Carole Snyder Manager, Rights and Permissions: Mike Joyce Director of Marketing: Patrice Jones Text Permission Coordinator: Jen Roach Marketing Manager: Yez Alayan Cover Art: Charles Bowman/Robert Harding Marketing Coordinator: Kathryn Ferranti Lead Media Project Manager: Daniel Sandin Marketing Assistant: Emma Snider Full-Service Project Management: Shiny Rajesh/ Director of Production: Vince O’Brien Integra Software Services Pvt. Ltd. Managing Editor: Jeff Holcomb Composition: Integra Software Services Pvt. Ltd. Production Project Manager: Kayla Smith-Tarbox Printer/Binder: Edward Brothers Production Editor: Pat Brown Cover Printer: Lehigh-Phoenix Color/Hagerstown Manufacturing Buyer: Pat Brown Text Font: Times Ten-Roman Creative Director: Jayne Conte Credits: Figure 2.14: reprinted with permission from The Computer Language Company, Inc. Figure 17.10: Buyya, Rajkumar, High-Performance Cluster Computing: Architectures and Systems, Vol I, 1st edition, ©1999. Reprinted and Electronically reproduced by permission of Pearson Education, Inc. Upper Saddle River, New Jersey, Figure 17.11: Reprinted with permission from Ethernet Alliance. Credits and acknowledgments borrowed from other sources and reproduced, with permission, in this textbook appear on the appropriate page within text. Copyright © 2013, 2010, 2006 by Pearson Education, Inc., publishing as Prentice Hall. All rights reserved. Manufactured in the United States of America.
    [Show full text]
  • Instruction Register MAR = Memory Address Register MBR = Memory Buffer Register I/O AR = I/O Address Register I/O BR = I/O Buffer Register
    Hardware Level Organization Intro MIPS 1 CPU Main Memory Major components: 0 PC MAR - memory System IR MBR Bus - central processing unit Instruction I/O AR Instruction - registers Instruction Ex Unit I/O BR - the fetch/execute cycle (the hardware process ) Data I/O Module Data Data n-1 buffers PC = program counter IR = instruction register MAR = memory address register MBR = memory buffer register I/O AR = I/O address register I/O BR = I/O buffer register CS @VT Computer Organization II ©2005-2013 McQuain Central Processing Unit Intro MIPS 2 Control - decodes instructions and manages CPU’s internal resources Registers - general-purpose registers available to user processes - special-purpose registers directly managed in fetch/execute cycle - other registers may be reserved for use of operating system - very fast and expensive (relative to memory) - hold all operands and results of arithmetic instructions (on RISC systems) - save bits in instruction representation Data path or arithmetic/logic unit (ALU) - operates on data CS @VT Computer Organization II ©2005-2013 McQuain Stored Program Concept Intro MIPS 3 Instructions are collections of bits Programs are stored in memory, to be read or written just like data Main Memory CPU 0 memory for data, programs, PC MAR compilers, editors, etc. Instruction IR MBR Instruction I/O AR Instruction Ex Unit I/O BR Data Data Data n-1 Fetch & Execute Cycle Instructions are fetched and put into a special register Bits in the register "control" the subsequent actions Fetch the “next” instruction and continue CS @VT Computer Organization II ©2005-2013 McQuain Stored Program Concept Intro MIPS 4 Of course, on most systems several programs will be stored in memory at any given time.
    [Show full text]
  • Intel® 4 Series Chipset Family Datasheet
    Intel® 4 Series Chipset Family Datasheet For the Intel® 82Q45, 82Q43, 82B43, 82G45, 82G43, 82G41 Graphics and Memory Controller Hub (GMCH) and the Intel® 82P45, 82P43 Memory Controller Hub (MCH) March 2010 Document Number: 319970-007 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel® 4 Series Chipset family may contain design defects or errors known as errata, which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. I2C is a two-wire communications bus/protocol developed by Philips.
    [Show full text]
  • PCI-X & PCI Core User's Guide
    PCI-X & PCI Core User's Guide Version 7.1.0 27-Feb-2007 © PLD Applications, 1996-2007 PLD Applications Web: http://www.plda.com Europarc Pichaury A2 Email: [email protected] 1330, rue Guillibert USA : 1 866 513 0362 (toll free) 13856 Aix-en-Provence Intl : + 33 442 393 600 CEDEX 3 - France Fax : + 33 442 394 902 Associate Member PCI-X & PCI Core User's Guide Features General ° 32-bit/64-bit PCI-X & PCI master/target interface ° Supports bus speed up to 133 MHz ° Multi-function core can implement up to 2 independent functions ° Full support for 64-bit addressing ° PCI-X Specification 2.0a mode 1 compliant ° PCI Specification 3.0 compliant ° Supports PCI power management ° Built-in support for in-site programming through JTAG interface ° Supports Message Signalled Interrupts Customization ° Easy customization with the PCI Wizard's user interface and on-line help. ° PCI Wizard has built-in support for VHDL and Verilog. ° All features can be parameterized, removing all unused logic ° Full plug-and-play support Configuration ° Supports all required and optional type 0 configuration registers ° Up to 6 BARs plus expansion ROM can be implemented ° Up to 32 user defined configuration registers Data transfer ° Supports up to 4KB burst transfers with zero wait-state insertion. ° Supports all memory and I/O commands ° Supports interrupt acknowledge cycles in target mode ° Can insert wait-states and generate all types of terminations ° Up to two split channels and 32 outstanding split transactions DMA ° Up to 4 independent DMA channels with rotating priority ° Flexible backend interface can directly control FIFO devices.
    [Show full text]
  • The Central Processor Unit
    Systems Architecture The Central Processing Unit The Central Processing Unit – p. 1/11 The Computer System Application High-level Language Operating System Assembly Language Machine level Microprogram Digital logic Hardware / Software Interface The Central Processing Unit – p. 2/11 CPU Structure External Memory MAR: Memory MBR: Memory Address Register Buffer Register Address Incrementer R15 / PC R11 R7 R3 R14 / LR R10 R6 R2 R13 / SP R9 R5 R1 R12 R8 R4 R0 User Registers Booth’s Multiplier Barrel IR Shifter Control Unit CPSR 32-Bit ALU The Central Processing Unit – p. 3/11 CPU Registers Internal Registers Condition Flags PC Program Counter C Carry IR Instruction Register Z Zero MAR Memory Address Register N Negative MBR Memory Buffer Register V Overflow CPSR Current Processor Status Register Internal Devices User Registers ALU Arithmetic Logic Unit Rn Register n CU Control Unit n = 0 . 15 M Memory Store SP Stack Pointer MMU Mem Management Unit LR Link Register Note that each CPU has a different set of User Registers The Central Processing Unit – p. 4/11 Current Process Status Register • Holds a number of status flags: N True if result of last operation is Negative Z True if result of last operation was Zero or equal C True if an unsigned borrow (Carry over) occurred Value of last bit shifted V True if a signed borrow (oVerflow) occurred • Current execution mode: User Normal “user” program execution mode System Privileged operating system tasks Some operations can only be preformed in a System mode The Central Processing Unit – p. 5/11 Register Transfer Language NAME Value of register or unit ← Transfer of data MAR ← PC x: Guard, only if x true hcci: MAR ← PC (field) Specific field of unit ALU(C) ← 1 (name), bit (n) or range (n:m) R0 ← MBR(0:7) Rn User Register n R0 ← MBR num Decimal number R0 ← 128 2_num Binary number R1 ← 2_0100 0001 0xnum Hexadecimal number R2 ← 0x40 M(addr) Memory Access (addr) MBR ← M(MAR) IR(field) Specified field of IR CU ← IR(op-code) ALU(field) Specified field of the ALU(C) ← 1 Arithmetic and Logic Unit The Central Processing Unit – p.
    [Show full text]
  • Register Are Used to Quickly Accept, Store, and Transfer Data And
    Register are used to quickly accept, store, and transfer data and instructions that are being used immediately by the CPU, there are various types of Registers those are used for various purpose. Among of the some Mostly used Registers named as AC or Accumulator, Data Register or DR, the AR or Address Register, program counter (PC), Memory Data Register (MDR) ,Index register,Memory Buffer Register. These Registers are used for performing the various Operations. While we are working on the System then these Registers are used by the CPU for Performing the Operations. When We Gives Some Input to the System then the Input will be Stored into the Registers and When the System will gives us the Results after Processing then the Result will also be from the Registers. So that they are used by the CPU for Processing the Data which is given by the User. Registers Perform:- 1) Fetch: The Fetch Operation is used for taking the instructions those are given by the user and the Instructions those are stored into the Main Memory will be fetch by using Registers. 2) Decode: The Decode Operation is used for interpreting the Instructions means the Instructions are decoded means the CPU will find out which Operation is to be performed on the Instructions. 3) Execute: The Execute Operation is performed by the CPU. And Results those are produced by the CPU are then Stored into the Memory and after that they are displayed on the user Screen. Types of Registers are as Followings 1. MAR stand for Memory Address Register This register holds the memory addresses of data and instructions.
    [Show full text]
  • Volume 12: PCIE Configuration Registers (Haswell)
    © 2013 Intel Corporation Intel Open Source Graphics Programmer’s Reference Manual (PRM) for the 2013 Intel® Core™ Processor Family, including Intel HD Graphics, Intel Iris™ Graphics and Intel Iris Pro Graphics Volume 12: PCIE Configuration Registers (Haswell) 12/18/2013 1 Copyright INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. A "Mission Critical Application" is any application in which failure of the Intel Product could result, directly or indirectly, in personal injury or death. SHOULD YOU PURCHASE OR USE INTEL'S PRODUCTS FOR ANY SUCH MISSION CRITICAL APPLICATION, YOU SHALL INDEMNIFY AND HOLD INTEL AND ITS SUBSIDIARIES, SUBCONTRACTORS AND AFFILIATES, AND THE DIRECTORS, OFFICERS, AND EMPLOYEES OF EACH, HARMLESS AGAINST ALL CLAIMS COSTS, DAMAGES, AND EXPENSES AND REASONABLE ATTORNEYS' FEES ARISING OUT OF, DIRECTLY OR INDIRECTLY, ANY CLAIM OF PRODUCT LIABILITY, PERSONAL INJURY, OR DEATH ARISING IN ANY WAY OUT OF SUCH MISSION CRITICAL APPLICATION, WHETHER OR NOT INTEL OR ITS SUBCONTRACTOR WAS NEGLIGENT IN THE DESIGN, MANUFACTURE, OR WARNING OF THE INTEL PRODUCT OR ANY OF ITS PARTS. Intel may make changes to specifications and product descriptions at any time, without notice.
    [Show full text]
  • Parallel Computing in Image Processing Using GPU and CUDA Architecture
    Slovak University of Technology in Bratislava Faculty of Civil Engineering Department of Mathematics and Constructive Geometry Academic year: 2017/2018 Reg. No.: SvF-5343-63353 MASTER THESIS TOPIC Student: Bc. Alexander Baťka Student’s ID: 63353 Study programme: Mathematical and Computational Modeling Study field: 9.1.9. Applied Mathematics Thesis supervisor: Ing. Jozef Urbán, PhD. Topic: Parallel computing in image processing using GPU and CUDA architecture Language of thesis: English Specification of Assignment: Téma sa zaoberá paralelizáciou algoritmov spracovania obrazu pomocou grafických procesorov využitím architektúry CUDA (Compute Unified Device Architecture). Študent naštuduje problematiku využitia GPU pre všeobecné výpočty. Naučí sa pomocou CUDA paralelizovať výpočty používané v spracovaní obrazu ako BiConjugate Gradient Stabilized Method, filtrácia obrazu lineárnou rovnicou vedenia tepla, transformácia a registrácia obrazu. Dosiahnuté výsledky vhodne prezentuje. Selected bibliography: 1. Sanders, J. – Kandrot, E. CUDA by Example: An Introduction to General-Purpose GPU Programming. Upper Saddle River : Addison Wesley, 2011. 290 s. ISBN 978-0-13-138768-3. 2. Krivá, Z. – Mikula, K. – Stašová, O. Spracovanie obrazu: Vybrané kapitoly z prednášok. Bratislava : Slovenská technická univerzita v Bratislave, 2016. 149 s. ISBN 978-80-227-4535-2. 3. Bi-CGSTAB: A fast and smoothly converging variant of Bi-CG for the solution of nonsymmetric linear sys- tems, SIAM J. Sci. Statist. Comput., 13 (1992), pp. 631–644 4. CUDA programming: A Developers guide to parallel computing with GPUs, Shane Cook, 2013, ISBN-978- 0-12-415933-4 Assignment procedure from: 02. 10. 2017 Date of thesis submission: 10. 05. 2018 Bc. Alexander Baťka Student prof. RNDr. Radko Mesiar, DrSc. prof. RNDr.
    [Show full text]
  • Chapter 2 - Computer Evolution and Performance
    Chapter 2 - Computer Evolution and Performance A Brief History of Computers (Section 2.1) on pp. 16-38 Let's take a quick look at the history of computers so that we know where it all began. Further, we will find that most things have dramatically changed while some have not. ENIAC (Electronic Numerical Integrator and Computer) Designed by: John Mauchly and John Presper Eckert Reason: Response to wartime needs Completed: 1946 Specifics: 30 tons, 15,000 sq ft, 18000 vacuum tubes, 5000 additions/sec decimal machine with 20 accumulators each accumulator could hold a 10-digit decimal number Programming the ENIAC involved plugging and unplugging cables. If however, the program could be stored somehow and held in memory along with the data, this process would not be necessary. This is known as the "stored-program concept." Much of the credit was given to John von Neumann who helped engineer a computer (IAS) that utilized this concept and was completed in 1952. What is amazing is that today, most computers have the same general structure and function. Wow!! IAS Computer Designed by: John von Neumann Reason: Incorporate the stored-program concept Completed: 1952 Specifics: 1000 words (40-bit words) of storage, both data and instructions are stored, binary representations A word of storage can represent either an instruction or a number. The format for each is as follows: Number: bit 0 is sign bit, bits 1-39 are the number Instruction: bits 0-7 opcode of left instruction bits 8-19 address of one of the words of memory bits 20-27 opcode of right instruction bits 28-39 address of one of the words of memory Note: An instruction word really contains two instructions (left and right instructions).
    [Show full text]
  • Creating a Pci Express Interconnect in the Gem5 Simulator
    CREATING A PCI EXPRESS INTERCONNECT IN THE GEM5 SIMULATOR BY KRISHNA PARASURAM SRINIVASAN THESIS Submitted in partial fulfillment of the requirements for the degree of Master of Science in Electrical and Computer Engineering in the Graduate College of the University of Illinois at Urbana-Champaign, 2018 Urbana, Illinois Adviser: Associate Professor Nam Sung Kim ABSTRACT In this thesis, the objective was to implement a PCI (Peripheral Component Interconnect) Express interconnect in the gem5 architecture simulator. The interconnect was designed with the goal of aiding accurate modeling of PCI Express-based devices in gem5 in the future. The PCI Express interconnect that was created consisted of a root complex, PCI Express switch, as well as individual PCI Express links. Each of these created components can work independently, and can be easily integrated into the existing gem5 platforms for the ARM Instruction Set Architecture. The created PCI Express interconnect was evaluated against a real PCI Express interconnect present on an Intel Xeon server platform. The bandwidth offered by both interconnects was compared by reading data from storage devices using the Linux utility “dd”. The results indicate that the gem5 PCI Express interconnect can provide between 81% - 91.6% of the bandwidth of the real PCI Express interconnect. However, architectural differences between the gem5 and Intel Xeon platforms used, as well as unimplemented features of the PCI Express protocol in the gem5 PCI Express interconnect, necessitate more strenuous validation
    [Show full text]
  • Chapter 1 + Basic Concepts and Computer Evolution Computer Architecture 2 Computer Organization
    1 Chapter 1 + Basic Concepts and Computer Evolution Computer Architecture 2 Computer Organization • Attributes of a • Instruction set, system visible to number of bits used to represent various the programmer data types, I/O • Have a direct mechanisms, impact on the techniques for logical execution addressing memory of a program Architectural Computer attributes Architecture include: Organizational Computer attributes Organization include: • The operational • Hardware details units and their transparent to the interconnections programmer, control that realize the signals, interfaces between the computer and architectural peripherals, memory specifications technology used + IBM System 370 Architecture 3 ◼ IBM System/370 architecture ◼ Was introduced in 1970 ◼ Included a number of models ◼ Could upgrade to a more expensive, faster model without having to abandon original software ◼ New models are introduced with improved technology, but retain the same architecture so that the customer’s software investment is protected ◼ Architecture has survived to this day as the architecture of IBM’s mainframe product line System/370-145 system console. + 4 Structure and Function ◼Structure ◼ The way in which ◼ Hierarchical system components relate to each other ◼ Set of interrelated subsystems ◼Function ◼ Hierarchical nature of complex ◼ The operation of individual systems is essential to both components as part of the their design and their structure description ◼ Designer need only deal with a particular level of the system at a time ◼ Concerned
    [Show full text]
  • Microsoft Powerpoint
    William Stallings Computer Organization and Architecture Chapter 12 CPU Structure and Function Rev. 3.3 (2009-10) by Enrico Nardelli12 - 1 CPU Functions • CPU must: Fetch instructions Decode instructions Fetch operands Execute instructions / Process data Store data Check (and possibly serve) interrupts Rev. 3.3 (2009-10) by Enrico Nardelli 12 - 2 CPU Components Registri PC IR Data Lines ALU ControlControl Lines Lines AddressAddressLines Lines AC MBR CPU Internal Bus Bus InternalInternal CPU CPU MAR Control Unit Control Signals Rev. 3.3 (2009-10) by Enrico Nardelli 12 - 3 Kind of Registers • User visible and modifiable General Purpose Data (e.g. accumulator) Address (e.g. base addressing, index addressing) • Control registers (not visible to user) Program Counter (PC) Instruction Decoding Register (IR) Memory Address Register (MAR) Memory Buffer Register (MBR) • State register (visible to user but not directly modifiable) Program Status Word (PSW) Rev. 3.3 (2009-10) by Enrico Nardelli 12 - 4 Kind of General Purpose Registers • May be used in a general way or be restricted to contains only data or only addresses • Advantages of general purpose registers Increase flexibility and programmer options Increase instruction size & complexity • Advantages of specialized (data/address) registers Smaller (faster) instructions Less flexibility Rev. 3.3 (2009-10) by Enrico Nardelli 12 - 5 How Many General Purposes Registers? • Between 8 - 32 • Fewer = more memory references • More does not reduce memory references and takes up processor real estate Rev. 3.3 (2009-10) by Enrico Nardelli 12 - 6 How many bits per register? • Large enough to hold full address value • Large enough to hold full data value • Often possible to combine two data registers to obtain a single register with a double length Rev.
    [Show full text]