DOCSLIB.ORG

Magma Design Automation, Inc. Securities Litigation 05-CV-02394

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Magma Design Automation, Inc. Securities Litigation 05-CV-02394 3:05-cv-02394-CRB Document 138 Filed 11/09/2007 Page 1 of 2 1 2 3 4 5 6 7 8 9 10 UNITED STATES DISTRICT COURT 11 NORTHERN DISTRICT OF CALIFORNIA 12 SAN FRANCISCO DIVISION 13 IN RE: MAGMA DESIGN AUTOMATION, ) Case No.: C-05-2394 CRB INC. SECURITIES LITIGATION ) 14 ) CLASS ACTION 15 DECLARATION OF BLAINE F. NYE, This Document Relates to: ) PH.D. 16 ) 17 ALL ACTIONS ) DATE: November 30, 2007 18 ) TIME: 10:00 a.m. CTRM: 8, 19th 19 ) JUDGE: Hon Charles R. Breyer 20 21 22 23 24 25 26 27 28 II DECLARATION OF BLAINE F. NYE, PH.D. Case No. C-05-2394 CRB DOCS\418640v 1 3:05-cv-02394-CRB Document 138 Filed 11/09/2007 Page 2 of 2 1 I, BLAINE F. NYE, declares: 2 1. I have been retained by Counsel for Lead Plaintiff to provide expert 3 opinions in this action. I submit this declaration, in support of Lead Plaintiffs Memorandum in 4 Opposition to Defendants' Motion for Summary Judgment. 5 2. Attached hereto as Exhibit A is a true and correct copy of the Report of Blaine F. Nye, Ph.D dated October I I, 2007. 3. Attached. hereto as Exhibit B is a true and correct copy of the Declaration and Rebuttal Report of Blaine F. Nye, Ph.D dated November 9, 2007. 1 declare under penalty of perjury under the laws of the United States of America that the 10 foregoing is true and correct. Executed this 9th. day of November, 2007 at Redwood City, 11 California. 12 13 14 BLAINE"F. NVK 15 1d 17 18 19 20 21 22 23 24 25 26 27 28 OF BLAINE F. NYE, PH.D. - 1 - ase No. C-05-2394 CRB OCS\418640v1 Case 3:05-cv-02394-CRB Document 138-2 Filed 11/09/2007 Page 1 of 100 Exhibit A Case 3:05-cv-02394-CRB Document 138-2 Filed 11/09/2007 Page 2 of 100 UNITED STATES DISTRICT COURT NORTHERN DISTRICT OF CALIFORNIA SAN FRANCISCO DIVISION IN RE MAGMA DESIGN AUTOMATION, Case No.: C-05-2394 CRB INC. SECURITIES LITIGATION CLASS ACTION This Document Relates to: ALL ACTIONS THE CORNELIA I. CROWELL GST TRUST, On Behalf Of Itself and All Others Similarly Situated, Plaintiff, vs. MAGMA DESIGN AUTOMATION, INC., RAJEEV MADHAVAN, GREGORY C. WALKER, ROY E. JEWELL, Defendants. REPORT OF BLAINE F. NYE, PH.D. October 11, 2007 Case 3:05-cv-02394-CRB Document 138-2 Filed 11/09/2007 Page 3 of 100 Table of Contents I. Background and Qualifications ........................................................................................... 1 II. Scope of Engagement ......................................................................................................... 1 III. Bases for Opinions .............................................................................................................. 2 IV. Summary of Opinions ......................................................................................................... 3 V. Market Efficiency: Securities prices in efficient markets reflect the market ' s consensus as to fair value given all publicly available information at the time of purchase or sale.... 5 VI. Application of the Cammer Factors and Additional Factors as Indicia of the Efficiency of the Market for Magma's Stock ........................................................................................... 9 A. Cammer Factor 1: Weekly Trading Volume ...................................................................... 9 B. Cammer Factor 2: The Number of Securities Analysts Following and Reporting on Magma .............................................................................................................................. 11 C. Cammer Factor 3: The Number of Market Makers in Magma's Stock ............................ 12 D. Cammer Factor 4: Whether Magma was Eligible to File SEC Form S-3 ......................... 15 E. Cammer Factor 5: Empirical Facts Showing a Cause-and-Effect Relationship between Unexpected Corporate Events or Financial Releases and an Immediate Response in the Stock Price ........................................................................................................................ 17 F. Summary Regarding the Market Efficiency of Magma's Stock ....................................... 22 VII. Evidence on the Efficiency of the Market for Call and Put Options on Magma Stock.... 23 VIII. Evidence on the Efficiency of the Market for the Magma Notes ..................................... 24 A. Description of the Magma Notes ...................................................................................... 24 B. Changes in the Prices of the Magma Notes Corresponded to Changes in the Prices of Magma Stock .................................................................................................................... 25 C. Registration and Trading Venue ....................................................................................... 27 D. There was an Underwriter and Market Maker for the Magma Notes ............................... 30 E. Additional Factors Supporting My Conclusion the Market for the Magma Notes was Efficient during the Class Period ...................................................................................... 30 F. Summary of the Efficiency of the Market for the Magma Notes ..................................... 31 IX. Materiality ......................................................................................................................... 31 X. Loss Causation .................................................................................................................. 35 XI. Analysis of Per-Security Damages under Section 10(b) ................................................... 49 A. Loss Causation and the Percentage versus Dollar Measure of Inflation .......................... 49 B. Per-Security Damages: Magma Stock .............................................................................. 55 C. Per-Security Damages: Call and Put Options on Magma Stock ....................................... 57 Case 3:05-cv-02394-CRB Document 138-2 Filed 11/09/2007 Page 4 of 100 D. Per-Security Damages: Magma Notes .............................................................................. 60 XII. Aggregate Damages under Section 10(b) ......................................................................... 61 A. Aggregate Damages on Magma Stock under Section 10(b) ............................................. 61 B. Aggregate Damages on Options on Magma Stock under Section 10(b) .......................... 63 C. Aggregate Damages on the Magma Notes under Section 10(b) ....................................... 64 Appendix: Regression Analysis and Event Study .......................................................................... 1 Case 3:05-cv-02394-CRB Document 138-2 Filed 11/09/2007 Page 5 of 100 I, BLAINE F. NYE, PH.D., declare: 1. Background and Qualifications 1. I am a financial economist and the President of Stanford Consulting Group, Inc., which provides research and consulting services in financial economics and related areas to clients including government agencies, corporations, and law firms. I have a B.A. degree in physics from Stanford University, an M.S. degree in physics from the University of Washington, an M.B.A. degree from Stanford, and a Ph.D. in finance from Stanford. I have served as a consultant and/or expert witness in the areas of market efficiency, materiality, causation, and damages in a number of securities actions . My curriculum vitae is attached as Exhibit 1. During the past four years I have provided expert testimony in trial or by deposition in the matters listed in Exhibit 2. My publications during the past ten years are listed in my curriculum vitae (Exhibit 1). 2. The fees charged Lead Plaintiff for this project are the standard hourly rates of employees of Stanford Consulting Group, Inc. At present my hourly rate is $650. II. Scope of Engagement I have been retained by Counsel for Lead Plaintiff in this class action to provide expert opinions on the efficiency of markets for certain publicly traded securities of Magma Design Automation ("Magma or the "Company ) during the period October 23, 2002 through April 12, 2005, inclusive (the "Class Period ). Such securities include Magma common stock,' call and put options on Magma stock, and $150 million zero coupon convertible subordinated 1 During the Class Period, Magma's common stock traded on the NASDAQ National Market ("NASDAQ ) under the ticker "LAVA. Magma's stock was also traded on the Berlin stock exchange . The total reported trading volume during the Class Period on the Berlin stock exchange was 7,256 shares. (Source : FactSet Research Systems, Inc.) Shares traded on the Berlin stock exchange are not considered in this analysis . Herein, "Magma stock refers to the common stock of Magma traded on the NASDAQ. -1- Case 3:05-cv-02394-CRB Document 138-2 Filed 11/09/2007 Page 6 of 100 ).2, 3 notes due May 15, 2008 (the "Magma Notes I have also been asked to provide expert opinions with respect to materiality and loss causation pertaining to the alleged misrepresentations and omissions in this matter, and to provide an estimate of the damages incurred by acquirers of the above listed Magma Securities under Sections 10(b) of the Securities Exchange Act and Rule 10(b)-5 of the Securities and Exchange Commission ("SEC ) 4. The opinions offered in this Report are subject to refinement or revision based on continuing analysis of the documents and materials listed below, as well as new or additional information which may be provided to or obtained by me in the course of this matter. I expect to review additional information and documents, including information and documents that may become available through discovery and
Load more

Recommended publications
  • Final Program November 7 - 10, 2011 San Jose, Ca
    2011 FINAL PROGRAM NOVEMBER 7 - DESIGN10, TOOLS ASIC 2011 ENGINEERING VERIFICATION STRUCTURE ESDA SAN JOSE,PLANS CA CHIP EFFICIENCY INNOVATION DESIGN SIGNAL MIXED MIXED OPPORTUNITY CAD LOGIC SYNTHESIS COMPLEXITY MANUFACTURING IEEE/ACM TEMPLATES APPLIED SCIENCE PATTERN FPGA EDA AUTOMATION INTERNATIONAL METHODOLOGIES TECHNOLOGY EXHIBITCONFERENCE ON ADVANCEMENT STANDARDS CONCEPTION COMPLIANCE PIONEERING MECHANICS COMPUTER-AIDED CIRCUITS NETWORKING WORKFLOWDESIGN ELECTRONIC DESIGN2011 www.ICCAD.com www.iccad.com 2011 ICCAD continues to be the premier conference devoted to technical innovations in design automation. ICCAD’s program of technical papers, tutorials, panels, and keynote highlight ICCAD continues to host one‑day topical workshops providing focused the most important current and future research challenges. A day of coverage of topics of emerging and current interest. This year, four workshops, workshops on hot topics caps a week of non‑stop technical excitement. And on lithography, variability modeling/characterization, constraints in formal as always, a large number of side meetings and social events provide plenty of verification and adaptive power management will take place on Thursday, opportunities for networking and meeting colleagues and friends. November 10. This year’s CANDE workshop will also be co‑located with ICCAD in San Jose, and held in parallel with ICCAD workshops on Thursday, November 10. This year’s ICCAD starts on Monday, November 7 and continues through Wednesday, November 9. You will find up‑to‑date details on the conference website, http://www.iccad.com. Finally, ICCAD 2011 is privileged to have a keynote address from Dr. Georg Sigl of Technische Univ. München. Prof. Sigl will provide unique insights into the design of secure hardware systems, and asks what role EDA will play in the The core of ICCAD has always been the contributed research paper program.
    [Show full text]
  • UNITED STATES SECURITIES and EXCHANGE COMMISSION Washington, DC 20549 FORM 10-K
    UNITED STATES SECURITIES AND EXCHANGE COMMISSION Washington, D.C. 20549 FORM 10-K (Mark One) È ANNUAL REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE SECURITIES EXCHANGE ACT OF 1934 For the year ended October 31, 2013 OR ‘ TRANSITION REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE SECURITIES EXCHANGE ACT OF 1934 For the transition period from to Commission File Number 0-19807 SYNOPSYS, INC. (Exact name of registrant as specified in its charter) Delaware 56-1546236 (State or other jurisdiction of (I.R.S. Employer incorporation or organization) Identification No.) 700 East Middlefield Road, Mountain View, California 94043 (Address of principal executive offices, including zip code) (650) 584-5000 (Registrant’s telephone number, including area code) Securities Registered Pursuant to Section 12(b) of the Act: Title of Each Class Name of Each Exchange on Which Registered Common Stock, $0.01 par value NASDAQ Global Select Market Securities Registered Pursuant to Section 12(g) of the Act: None Indicate by check mark if the registrant is a well-known seasoned issuer, as defined in Rule 405 of the Securities Act. Yes È No ‘ Indicate by check mark if the registrant is not required to file reports pursuant to Section 13 or Section 15(d) of the Act. Yes ‘ No È Indicate by check mark whether the registrant (1) has filed all reports required to be filed by Section 13 or 15(d) of the Securities Exchange Act of 1934 during the preceding 12 months (or for such shorter period that the registrant was required to file such reports), and (2) has been subject to such filing requirements for the past 90 days.
    [Show full text]
  • Supply Chain Innovation: Responding to Dynamic Challenges
    Global Semiconductor Alliance SURVIVING UNDER CURRENT MARKET CONDITIONS RISK MANAGEMENT IN THE SEMICONDUCTOR SUPPLY CHAIN FAKING IT: WHY COUNTERFEITING IS THE SYMPTOM, NOT THE DISEASE ACCELERATING TECHNOLOGY EVOLUTION THROUGH PROCESS OUTSOURCING SEMICONDUCTOR EQUIPMENT SERVICE SUPPLY CHAIN—ANTICIPATING THE UPTURN Supply Chain Innovation: Responding to Dynamic Challenges Vol.16 No.3 Sept. 2009 Published by GSA $60 (U.S.) 1 A Powerful Platform for Amazing Performance Performance. To get it right, you need a foundry with an Open Innovation Platform™ and process technologies that provides the flexibility to expertly choreograph your success. To get it right, you need TSMC. Whether your designs are built on mainstream or highly advanced processes, TSMC ensures your products achieve maximum value and performance. Product Differentiation. Increased functionality and better system performance drive product value. So you need a foundry partner who keeps your products at their innovative best. TSMC’s robust platform provides the options you need to increase functionality, maximize system performance and ultimately differentiate your products. Faster Time-to-Market. Early market entry means more product revenue. TSMC’s DFM-driven design initiatives, libraries and IP programs, together with leading EDA suppliers and manufacturing data-driven PDKs, shorten your yield ramp. That gets you to market in a fraction of the time it takes your competition. Investment Optimization. Every design is an investment. Function integration and die size reduction help drive your margins. It’s simple, but not easy. We continuously improve our process technologies so you get your designs produced right the first time. Because that’s what it takes to choreograph a technical and business success.
    [Show full text]
  • Si2 Member Report 2010
    Si2Si2 MemberMember ReportReport 20102010 InnovationInnovation ThroughThrough CollaborationCollaboration BoardBoard ofof DirectorsDirectors 20102010 -- 20112011 TermTerm Apache Design Systems ARM AMD Vic Kulkarni John Goodenough Jim Miller Sr VP/General Manager of VP, Design Vice President, RTL Business Unit Technology & Automation Design Engineering Cadence Design Systems IBM Intel Charlie Huang Dr Leon Stok Rahul Goyal Senior Vice President VP, EDA Director, EDA Business and Chief Strategy Officer National GLOBALFOUNDRIES LSI Semiconductor Mojy Chian Prabhakaran Krishnamurthy James Lin Senior VP, Design Senior Director, Design VP Technology Enablment Implementation Infrastructure Group Synopsys Si2 John Chilton Steve Schulz Sr. VP & General Manager President & CEO LetterLetter fromfrom thethe ChairmanChairman Prabhu Krishnamurthy - LSI Senior Director, Design Implementation Si2 Board of Directors Chair As we turn the leaf on another successful year of collaboration at Si2, it is time to reflect on our collective accomplishments for 2010. Si2 started off the year approving the formation of a new coalition, "OpenPDK", with the goal of improving efficiency and interoperability for the creation of process design kits (PDKs), which are used universally across our industry. We are extremely pleased with the excitement that this new coalition has created, and we now have 15 member companies who are actively contributing to support the broad technical scope of OpenPDK. This scope includes an open process specification with reference implementation and plug-ins; enhanced, standardized symbols and parameters; CDF parameter and callback standards; PDK targeting support added to the OpenDFM standard; standard Pcell parameters; OpenAccess technology file enhancements; and a standardized SPICE socket. 2010 was also a strong year of progress for Si2's other coalitions.
    [Show full text]
  • Technology Commercialization in the Area of Analog IC Design Automation
    Technology Commercialization in the Area of Analog IC Design Automation Miguel Ramos de Carvalho e Costa Thesis to obtain the Master of Science Degree in Industrial Engineering and Management Supervisor: Prof. Nuno Cavaco Gomes Horta Co-supervisor: Prof. Maria Margarida Martelo Catalão Lopes de Oliveira Pires Pina Examination Committee Chairperson: Prof. Acácio Manuel de Oliveira Porta Nova Co-supervisor: Prof. Maria Margarida Martelo Catalão Lopes de Oliveira Pires Pina Member of the Committee: Prof. António Miguel Areias Dias Amaral June 2014 RESUMO Esta dissertação procura servir como uma análise de viabilidade de uma potencial atividade de comercialização para o AIDA, um software de automação e otimização do projeto de circuitos integrados analógicos desenvolvido no Instituto de Telecomunicações (IT), Unidade de Investigação do Instituto Superior Técnico (IST). Neste documento é apresentada uma pesquisa do mercado em que este software se integra, através da análise de informação de vendas, a um nível global e para cada líder de mercado em particular, e de questionários realizados a projetistas de circuitos integrados (potenciais utilizadores do software). Esta análise permite a identificação da estrutura do mercado e do comportamento dos participantes, bem como de funcionalidades de produto com importância para os projetistas, cuja integração no AIDA deve ser considerada. É também apresentada uma breve revisão bibliográfica referente à transferência de tecnologia de modo a perceber este fenómeno e como as características do produto e dos seus responsáveis afetam a comercialização – encontrando evidência que aponta para uma estratégia de licenciamento. Os resultados de uma análise financeira baseada nas vendas e custos estimados da constituição de uma start-up para explorar o potencial económico do produto demonstram que, sob as condições apresentadas, existe um potencial financeiro relevante nesta alternativa.
    [Show full text]
  • Cadence Design Systems, Inc. 2012 Annual Report Cadence Is a Global Technology Leader in Software, Hardware, IP, and Services for Electronic Design
    Cadence Design Systems, Inc. 2012 Annual Report Cadence is a global technology leader in software, hardware, IP, and services for electronic design. By delivering critical design technology for creating, integrating, and optimizing designs, Cadence enables customers to realize silicon, SoCs, and complete systems on schedule at lower costs with higher quality. Lip-Bu Tan President and Chief Executive Officer DEAR SHAREHOLDERS: In 2012, Cadence continued to perform well, grow our business, and improve our financial performance, despite global economic challenges and uncertainty in the semiconductor industry. Revenue grew 15% to $1.33 billion, operating profitability significantly improved, and operating cash flow increased 32% to $316 million. We also strengthened the Cadence team by hiring more than 700 employees worldwide, mostly in research and development and technical support functions. In keeping with our commitment to be a technology leader, we continued to invest in our product lines and delivered significant innovations to our customers. Our challenging, rewarding, customer-focused corporate culture was the foundation to our ongoing success in 2012. Cadence thrives on solving significant SoC Realization, which includes design and consumption. This technology, along with challenges for our customers in the verification IP, is a fast-growing business for FinFET technology, holds great promise for semiconductor and electronics industries. us and represents a significant opportunity. helping extend Moore’s Law. Opportunities for Cadence to thrive are Cadence offers differentiated, high- Our financial results in 2012 reflect solid created by trends like connectivity, mobility, performance and high-quality IP serving the execution, with strong financial returns that social media, cloud computing, and the rapid-growth mobile, video, and network enabled us to invest for future growth.
    [Show full text]
  • Optimality Study of Logic Synthesis for LUT-Based Fpgas Jason Cong and Kirill Minkovich
    230 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 2, FEBRUARY 2007 Optimality Study of Logic Synthesis for LUT-Based FPGAs Jason Cong and Kirill Minkovich Abstract—Field-programmable gate-array (FPGA) logic syn- thesis and technology mapping have been studied extensively over the past 15 years. However, progress within the last few years has slowed considerably (with some notable exceptions). It seems natural to then question whether the current logic-synthesis and technology-mapping algorithms for FPGA designs are produc- ing near-optimal solutions. Although there are many empirical studies that compare different FPGA synthesis/mapping algo- rithms, little is known about how far these algorithms are from the optimal (recall that both logic-optimization and technology- mapping problems are NP-hard, if we consider area optimization in addition to delay/depth optimization). In this paper, we present a novel method for constructing arbitrarily large circuits that have known optimal solutions after technology mapping. Using these circuits and their derivatives (called Logic synthesis Exam- ples with Known Optimal (LEKO) and Logic synthesis Exam- ples with Known Upper bounds (LEKU), respectively), we show that although leading FPGA technology-mapping algorithms can produce close to optimal solutions, the results from the entire logic-synthesis flow (logic optimization + mapping) are far from optimal. The LEKU circuits were constructed to show where the logic synthesis flow can be improved, while the LEKO circuits specifically deal with the performance of the technology map- ping. The best industrial and academic FPGA synthesis flows Fig. 1. Possible area-minimal mapping solutions.
    [Show full text]
  • Cadence Design Systems, Inc. Annual Report on Form 10-K for the Fiscal Year Ended December 28, 2019
    UNITED STATES SECURITIES AND EXCHANGE COMMISSION Washington, D.C. 20549 FORM 10-K (Mark One) È ANNUAL REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE SECURITIES EXCHANGE ACT OF 1934 For the fiscal year ended December 28, 2019 OR ‘ TRANSITION REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE SECURITIES EXCHANGE ACT OF 1934 For the transition period from to . Commission file number 000-15867 CADENCE DESIGN SYSTEMS, INC. (Exact name of registrant as specified in its charter) Delaware 00-0000000 (State or Other Jurisdiction of (I.R.S. Employer Incorporation or Organization) Identification No.) 2655 Seely Avenue, Building 5, San Jose, California 95134 (Address of Principal Executive Offices) (Zip Code) (408)-943-1234 (Registrant’s Telephone Number, including Area Code) Securities registered pursuant to Section 12(b) of the Act: Title of Each Class Trading Symbol(s) Names of Each Exchange on which Registered Common Stock, $0.01 par value per share CDNS Nasdaq Global Select Market Securities registered pursuant to Section 12(g) of the Act: None Indicate by check mark if the registrant is a well-known seasoned issuer, as defined in Rule 405 of the Securities Act. Yes È No ‘ Indicate by check mark if the registrant is not required to file reports pursuant to Section 13 or Section 15(d) of the Act. Yes ‘ No È Indicate by check mark whether the registrant (1) has filed all reports required to be filed by Section 13 or 15(d) of the Securities Exchange Act of 1934 during the preceding 12 months (or for such shorter period that the registrant was required to file such reports), and (2) has been subject to such filing requirements for the past 90 days.
    [Show full text]
  • Parallel Circuit Simulation: a Historical Perspective and Recent Developments Full Text Available At
    Full text available at: http://dx.doi.org/10.1561/1000000020 Parallel Circuit Simulation: A Historical Perspective and Recent Developments Full text available at: http://dx.doi.org/10.1561/1000000020 Parallel Circuit Simulation: A Historical Perspective and Recent Developments Peng Li Texas A&M University College Station, Texas 77843 USA [email protected] Boston { Delft Full text available at: http://dx.doi.org/10.1561/1000000020 Foundations and Trends R in Electronic Design Automation Published, sold and distributed by: now Publishers Inc. PO Box 1024 Hanover, MA 02339 USA Tel. +1-781-985-4510 www.nowpublishers.com [email protected] Outside North America: now Publishers Inc. PO Box 179 2600 AD Delft The Netherlands Tel. +31-6-51115274 The preferred citation for this publication is P. Li, Parallel Circuit Simulation: A Historical Perspective and Recent Developments, Foundations and Trends R in Elec- tronic Design Automation, vol 5, no 4, pp 211{318, 2011 ISBN: 978-1-60198-514-9 c 2012 P. Li All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, mechanical, photocopying, recording or otherwise, without prior written permission of the publishers. Photocopying. In the USA: This journal is registered at the Copyright Clearance Cen- ter, Inc., 222 Rosewood Drive, Danvers, MA 01923. Authorization to photocopy items for internal or personal use, or the internal or personal use of specific clients, is granted by now Publishers Inc for users registered with the Copyright Clearance Center (CCC). The `services' for users can be found on the internet at: www.copyright.com For those organizations that have been granted a photocopy license, a separate system of payment has been arranged.
    [Show full text]
  • PLM Industry Summary Jillian Hayes, Editor Vol
    PLM Industry Summary Jillian Hayes, Editor Vol. 14 No 21 Friday 25 May 2012 Contents Acquisitions _______________________________________________________________________ 2 3D Systems Acquires Bespoke Innovations ___________________________________________________2 AVEVA Acquires Bocad _________________________________________________________________3 EMC Acquires Syncplicity ________________________________________________________________4 Hexagon Acquires Norwegian Software Company myVR _______________________________________5 IFS Continues to Invest in Mobility & Field Service Management with the Acquisition of Metrix LLC. ___5 SAP to Expand Cloud Presence with Acquisition of Ariba _______________________________________7 CIMdata News _____________________________________________________________________ 9 CIMdata Publishes “Delivering PLM Technology to Solve Food & Beverage Industry Issues”___________9 “One Siemens”—Observations from the 2012 Siemens PLM Connections Event ____________________11 Company News ____________________________________________________________________ 13 Applied Software Earns Autodesk Simulation Specialization ____________________________________13 Atos Wins Major UK IT Outsourcing Contract _______________________________________________14 Carbon Design Systems, Cadence Partner for IP Optimization ___________________________________15 IMAGINiT Technologies Earns Autodesk Simulation Specialisation in Australia ____________________16 ITI TranscenData Joins the 3D PDF Consortium ______________________________________________17
    [Show full text]
  • Press Releases
    Press Releases O'Melveny Represents Berkeley Design Automation in Agreement to be Acquired by Mentor Graphics March 21, 2014 RELATED PROFESSIONALS FOR IMMEDIATE RELEASE Contact: Brian Covotta Julie Fei O’Melveny & Myers LLP Piper Hall O’Melveny & Myers LLP Silicon Valley 213.430.7792 202.220.5022 D: +1­650­473­2649 [email protected] [email protected] Warren T. Lazarow Silicon Valley D: +1­650­473­2637 SILICON VALLEY ─ March 21, 2014 ─ O’Melveny & Myers LLP is representing Berkeley Design Automation, Inc., a recognized leader in nanometer circuit verification for analog, mixed­signal, RF, and custom digital verification, in its agreement to be acquired by Mentor Graphics Corp., a leader in electronic design automation. The O’Melveny team was spearheaded by partners Warren Lazarow and Brian Covotta. O’Melveny is a leading firm in the electronic design automation (EDA) sector, having handled more than 40 M&A transactions in the space over the past 10 years. The Firm’s work led by Lazarow and Covotta includes the acquisition of Sierra Design Automation by Mentor Graphics; the acquisition of Brion Technologies by ASML; the acquisitions of Clear Shape Technologies, CommandCAD, Q Design Automation, and Taray by Cadence Design Systems; the acquisitions of Knights Technology and Mojave Design by Magma Design Automation; and the acquisitions of ArchPro Design Automation, Everest Design Automation, InnoLogic, Magma Design Automation, and VaST Systems by Synopsys. About O’Melveny & Myers LLP With approximately 800 lawyers in 16 offices worldwide, O’Melveny & Myers LLP helps industry leaders across a broad array of sectors manage the complex challenges of succeeding in the global economy.
    [Show full text]
  • 48Th DAC Final Program
    Exhibiting CompaniEs ListingasofMay12,2011 Company Booth Company Booth Accelicon Technologies, Inc. 2830 EVE-USA, Inc. 2836 ACML / 2 WCL 1227 Exhibitor Forum 1005 Agilent Technologies 1229 ExpertIO, Inc. 1813 Aldec, Inc. 1243 Extreme DA 2939 Altair Engineering 1714 FishTail Design Automation, Inc. 1304 Altos Design Automation 2749 Forte Design Systems 3417 AMIQ EDA 2114 GateRocket, Inc. 3126 AnaGlobe Technology, Inc. 3016 GiDEL 2725 Apache Design Solutions, Inc. 2448 GLOBALFOUNDRIES 1517 Applied Simulation Technology 2731 GLOBALFOUNDRIES Partner - Analog Bits 1517 ApS Brno Ltd., Codasip Division 3218 GLOBALFOUNDRIES Partner - Apache Design 1517 Arasan Chip Systems 3113 GLOBALFOUNDRIES Partner - Cadence 1517 ARM, Inc. 1323 GLOBALFOUNDRIES Partner - Mentor Graphics 1517 Artwork Conversion Software, Inc. 1613 GLOBALFOUNDRIES Partner - Synopsys 1517 ASICServe LTD 2015 GLOBALFOUNDRIES Partner - Toppan Group 1517 Asygn 2125 GLOBALFOUNDRIES Partner - ChipEstimate.com 1517 ATEEDA 1812 GLOBALFOUNDRIES Partner - Lorentz Solution 1517 Atoptech 2816 Gradient Design Automation 3249 Atrenta Inc. 1643 GRID Simulation Technology, Inc. 1918 Ausdia Inc. 3142 Helic, Inc. 3049 austriamicrosystems 2327 Hewlett-Packard Co. 2730 Avery Design Systems, Inc. 1605 IBM Corp. 1818 Axiom Design Automation 3320 IC Manage, Inc. 1617 BEEcube, Inc. 2431 iHS iSuppli 2319 Berkeley Design Automation, Inc. 3149 Imera Systems, Inc. 3225 Blue Pearl Software 1035 Infotech Enterprises 2716 Bluespec, Inc. 3031 InnoPower Technology Corp. 1715 Breker Verification Systems 1143 InPA Systems, Inc. 3216 Cadence Design Systems, Inc. 2237 Interra Systems, Inc. 2220 Calypto Design Systems 2012 IQ-Analog – IP SoC Village 1915 Cambridge Analog Technologies 2221 Isilon Systems 3213 Carbon Design Systems 1914, 2127 Jasper Design Automation, Inc. 1931 Carr & Ferrell LLP 3318 JTAG Technologies 2317 CAST, Inc.
    [Show full text]