DOCSLIB.ORG

Automated Synthesis and Verification of Embedded Systems

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Automated Synthesis and Verification of Embedded Systems AutomatedAutomated Synthesis Synthesis andand VerificationVerification of of EmbeddedEmbedded Systems:Systems: WishfulWishful Thinking Thinking or or Reality? Reality? Wolfgang Rosenstiel Computer Engineering Wilhelm-Schickard-Institute for Informatics University of Tuebingen Germany WILHELM-SCHICKARD-INSTITUT Computer Engineering FromFrom HardwareHardware SupplySupply toto thethe FinalFinal ApplicationApplication Legislator Content Regulations Provider Gateway Service Content mgmt Provider Protection Delivery System System Application infrastructure Integrator mgmt Network Chip Maker Software Equipment Semi Wafer Equipment Foundry Semi Materials Sphere of design influence Source: Medea WILHELM-SCHICKARD-INSTITUT Computer Engineering EmbeddedEmbedded SoftwareSoftware isis BecomingBecoming MoreMore ValuableValuable Innovation by Source, % Contribution to revenue, % 4 15 16 25 Electronics 70 Electronics software 80 software Electronics Electronics hardware hardware 80 Mechanics Mechanics 60 30 20 2003 2015 2003 2015 Source: 2003 McKinsey-PTW HAWK survey (Institute for Production Management at the Technical University at Darmstadt, McKinsey analysis) WILHELM-SCHICKARD-INSTITUT Computer Engineering Relatives Wachstum: Kfz, Steuergeräte, TheThe AutomotiveAutomotive SiliconSilicon DriveDrive Halbleiter 600% Semiconductors 580% 500% Cars:ECU:S/C = 1:5:12 400% ECU 300% 300% 200% Percent of Growth (2000 = 100%) Cars & light trucks 140% 100% 2000 2002 2004 2006 2008 2010 2012 2014 2016 2018 2020 Source: Bosch WILHELM-SCHICKARD-INSTITUT Computer Engineering AddedAdded ValueValue ThroughThrough NewNew ElectronicElectronic FunctionsFunctions Car fabrication cost 11.000 in EUR cost in 10.200 % relation to 2000 new functions 100 23 % 100 % todays functions 85 % 75 50 25 0 2000 2010 Source: Mercer, a.o. WILHELM-SCHICKARD-INSTITUT Computer Engineering TheThe GrowingGrowing RoleRole ofof ChipChip MakersMakers The electronic part of final applications is increasingly determined and designed by semiconductor chip makers Customer interface is shifting to the boundary between the embedded code in the semiconductor device and the application software Building intelligent systems for the future requires close collaboration between the innovation teams of chip suppliers, chip customers ÆEDA is the bridge between them Source: Panel Discussion, edaForum07 WILHELM-SCHICKARD-INSTITUT Computer Engineering OutlineOutline EDA challenges System Level Design Verification Synthesis Conclusions WILHELM-SCHICKARD-INSTITUT Computer Engineering DesignDesign CostsCosts Source: ITRS 2008 based on data from Gary Smith WILHELM-SCHICKARD-INSTITUT Computer Engineering MotivationMotivationAutomotiveAutomotiveBayesian Networks ElectronicsElectronics Modelling Automotive Software Today's readmission rate for cars is ~ 70 000 000 cars per year Average of 20 to 70 embedded systems per car 50% development effort spend on software engineering Every 2nd car recall caused by software problems Æ Software quality assessment plays an important role in cost reduction and customer satisfaction 8 WILHELM-SCHICKARD-INSTITUT Computer Engineering VerificationVerification ProblemsProblems 2004 Pontiac recalls the Grand Prix since the software did not understand leap years. 2004 was a leap year. 2003 A BMW 520 trapped a Thai politician when the computer crashed. The door locks, windows, A/C and more were inoperable. Windshield was smashed to get him out. 2002 BMW recalls the 745i since the fuel pump would shut off if the tank was less than 1/3 full. Source: http://www.embedded.com/columns/embeddedpulse/179100752?_requestid=42835 WILHELM-SCHICKARD-INSTITUT Computer Engineering VerificationVerification ChallengesChallenges Challenge: Complexity growth Example: Diesel systems 2007 Calibration parameters: 16 k Performance: 300 MIPS Memory: 4 MByte Software coding errors Finite-state machines Timing Stack/memory overflows Consistencies Non-volatile memory Source: Software Bugs seen from an Industrial Perspective. CAV07 [Kropf07] Requirements Design Coding Application WILHELM-SCHICKARD-INSTITUT Computer Engineering OutlineOutline EDA challenges System Level Design Verification Synthesis Examples and Results WILHELM-SCHICKARD-INSTITUT Computer Engineering DesignDesign FlowFlow ofof DistributedDistributed EmbeddedEmbedded SystemsSystems Model based design of distributed systems platform dependent development of the application software (UML, Matlab/Simulink, C++) early consideration of the planned target platform in the model based system design (UML) mapping of function blocks on architecture components TM SYSTEMC use of virtual prototypes for the abstract modeling of the target platform Virtual Prototype Software Network Hardware Early analysis of the system integration early verification based on virtual prototypes formal and semiformal software verification Seamless transition to the real prototype automatic “target code” generation automatic high level synthesis co-simulation/emulation SystemC as intermediate representation WILHELM-SCHICKARD-INSTITUT Computer Engineering DesignDesign andand VerificationVerification ProcessProcess 13 Challenges Requirements Management 1. Move from document centric to model centric Specification 2. Interfaces between requirements, specification, Verification aims Implementation verification aims, and implementation 3. Tracing of requirements and verification aims Verification Prozess 4. Automatic generation of Analysis (Coverage, Assertions) software, hardware and test cases (ATPG) Results WILHELM-SCHICKARD-INSTITUT Computer Engineering DesignDesign andand VerificationVerification ProcessProcess withwith UMLUML 14 Requirements Management • Interfaces between specification, verification Specification aims, and implementation • Enable code generation Verification aims Implementation • Enable test case description • Enable linking and Verification Prozess tracing of design Analysis components (Coverage, Assertions) • Missing Æ requirements Results • Missing Æ support the verification process WILHELM-SCHICKARD-INSTITUT Computer Engineering UMLUML 22 15 UML 2.x Diagram Structure Behavior Diagram Diagram Class Composition Object Activity State Machine Use-Case- Diagram Diagram Diagram Diagram Diagram Diagram Component Package Deployment Diagram Diagram Diagram Interaction Diagram Communication Sequence Timing Interaction Diagram Diagram Diagram Overview Diagram WILHELM-SCHICKARD-INSTITUT Computer Engineering SystemSystem Architecture Architecture 16 UML 2.x Diagram Structure Behavior Diagram Diagram Class Composition Object Activity State Machine Use-Case- Diagram Diagram Diagram Diagram Diagram Diagram Component Package Deployment Diagram Diagram Diagram Interaction Diagram Communication Sequence Timing Interaction Diagram Diagram Diagram Overview Diagram WILHELM-SCHICKARD-INSTITUT Computer Engineering SystemSystem BehaviorBehavior 17 UML 2.x Diagram Structure Behavior Diagram Diagram Class Composition Object Activity State Machine Use-Case- Diagram Diagram Diagram Diagram Diagram Diagram Component Package Deployment Diagram Diagram Diagram Interaction Diagram Communication Sequence Timing Interaction Diagram Diagram Diagram Overview Diagram WILHELM-SCHICKARD-INSTITUT Computer Engineering ScenarioScenario / / TestTest casecase 18 UML 2.x Diagram Structure Behavior Diagram Diagram Class Composition Object Activity State Machine Use-Case- Diagram Diagram Diagram Diagram Diagram Diagram Component Package Deployment Diagram Diagram Diagram Interaction Diagram Communication Sequence Timing Interaction Diagram Diagram Diagram Overview Diagram WILHELM-SCHICKARD-INSTITUT Computer Engineering SysMLSysML 19 SysML Structure Requirements- Behavior Diagram Diagram Diagram Block Definition Internal Block Object Activity State Machine Use-Case- Diagram Diagram Diagram Diagram Diagram Diagram Component Package Deployment Diagram Diagram Diagram Interaction Diagram Parametric Interaction Diagram Communication Sequence Timing Diagram Diagram Diagram Overview Diagram New diagrams in SysML Extended/modified diagrams in SysML WILHELM-SCHICKARD-INSTITUT Computer Engineering InterfaceInterface toto VerificationVerification 20 Requirements Management Challenge Specification • System analysis of Verification aims Implementation UML/SysML diagrams Verification Prozess • Generating for Analysis verification aims (Coverage, Assertions) (Assertions) Results WILHELM-SCHICKARD-INSTITUT Computer Engineering OutlineOutline EDA challenges System Level Design Verification Synthesis Conclusion WILHELM-SCHICKARD-INSTITUT Computer Engineering SystemSystem Analysis Analysis throughthrough Assertions Assertions 22 System Specification (UML/SysML) Sequence Deployment Structure Diagram Diagram Diagram Prozess to Communication System-Architecture Module Abstracte Property UML/SysML (High Level Description) Assertions Simulation Formale Verification System- Description WILHELM-SCHICKARD-INSTITUT Computer Engineering Assertion-basedAssertion-based VerificationVerification 23 Test bench PSL/FLTL System-Model (includes test patterns Property (Assertion) example AR Prozess1 Prozess2 Prozess3 (P1) (P2) (P3) SystemC-based Temporal Checker Accept Reject Monitors for Assertions Interfaces for test patterns Test pattern indicate test quality Assertions improve error localization Assertions for functional und formal verification WILHELM-SCHICKARD-INSTITUT Computer Engineering SoftwareSoftware ModelingModeling Integers, arrays, floating point Arithmetic operations: +, - , *, /, % Software Software Pointers Procedures
Load more

Recommended publications
  • Die Virtuelle Plattform: Der Einsatz Von Zynq Fuer Die Verifikation Und Das Debugging Von Konfigurierbaren Systemen
    Die virtuelle Plattform: Der Einsatz von Zynq fuer die Verifikation und das Debugging von konfigurierbaren Systemen Dr. Endric Schubert Missing Link Electronics Marlene-Dietrich-Straße 5 89231 Neu-Ulm www.missinglinkelectronics.com Tel: +49 (731) 141-149-0 Courtesy Xilinx 1 Challenges of Debugging Your Own ASSP © Missing Link Electronics 12. Juli 2012 2 Another Challenge When Building Your Own ASSP: Making Hardware and Software Work Together. © Missing Link Electronics 12. Juli 2012 3 ASSP System-on-Chip Design – An Embedded Designers Life © Missing Link Electronics 12. Juli 2012 4 What is a Virtual Platform? © Missing Link Electronics 12. Juli 2012 5 Virtual Platform Methodology © Missing Link Electronics 12. Juli 2012 6 Virtual Platforms Can Run Software Fast (Sometimes Faster Than Real) © Missing Link Electronics 12. Juli 2012 7 What is SystemC? Open Source Library managed by Open SystemC Initiative (OSCI) Extension to ISO C++ www.systemc.org Means to express concurrency Communication mechanisms Reactivity Concept of Time Current members: ARM Ltd. Cadence Design Systems, Inc. CoWare, Inc. Forte Design Systems Intel Event driven simulation kernel Corporation Mentor Graphics Corporation NXP Semiconductors STMicroelectronics Synopsys, Inc. Actis Design, LLC Atrenta, Inc. Bluespec, Inc. Broadcom - A modeling methodology Corporation Calypto Design Systems, Inc. Canon Inc. Carbon Design Systems Celoxica Ltd. ChipVision Design Systems AG Denali Software Inc. Doulos Ltd. ESLX, Inc. Fraunhofer Institute for Integrated Circuits Freescale Semiconductor Inc. GreenSocs Ltd. Industrial Technology Research Institute (ITRI) JEDA Technologies Inc. Infineon Technologies AG NEC Corporation Semiconductor Technology Academic Research Center (STARC) SpringSoft, Inc. Synfora Inc. Tenison EDA VaST Systems Technology Corporation © Missing Link Electronics 12.
    [Show full text]
  • Co-Simulation Between Cλash and Traditional Hdls
    MASTER THESIS CO-SIMULATION BETWEEN CλASH AND TRADITIONAL HDLS Author: John Verheij Faculty of Electrical Engineering, Mathematics and Computer Science (EEMCS) Computer Architecture for Embedded Systems (CAES) Exam committee: Dr. Ir. C.P.R. Baaij Dr. Ir. J. Kuper Dr. Ir. J.F. Broenink Ir. E. Molenkamp August 19, 2016 Abstract CλaSH is a functional hardware description language (HDL) developed at the CAES group of the University of Twente. CλaSH borrows both the syntax and semantics from the general-purpose functional programming language Haskell, meaning that circuit de- signers can define their circuits with regular Haskell syntax. CλaSH contains a compiler for compiling circuits to traditional hardware description languages, like VHDL, Verilog, and SystemVerilog. Currently, compiling to traditional HDLs is one-way, meaning that CλaSH has no simulation options with the traditional HDLs. Co-simulation could be used to simulate designs which are defined in multiple lan- guages. With co-simulation it should be possible to use CλaSH as a verification language (test-bench) for traditional HDLs. Furthermore, circuits defined in traditional HDLs, can be used and simulated within CλaSH. In this thesis, research is done on the co-simulation of CλaSH and traditional HDLs. Traditional hardware description languages are standardized and include an interface to communicate with foreign languages. This interface can be used to include foreign func- tions, or to make verification and co-simulation possible. Because CλaSH also has possibilities to communicate with foreign languages, through Haskell foreign function interface (FFI), it is possible to set up co-simulation. The Verilog Procedural Interface (VPI), as defined in the IEEE 1364 standard, is used to set-up the communication and to control a Verilog simulator.
    [Show full text]
  • Download the Compiled Program File Onto the Chip
    International Journal of Computer Science & Information Technology (IJCSIT) Vol 4, No 2, April 2012 MPP SOCGEN: A FRAMEWORK FOR AUTOMATIC GENERATION OF MPP SOC ARCHITECTURE Emna Kallel, Yassine Aoudni, Mouna Baklouti and Mohamed Abid Electrical department, Computer Embedded System Laboratory, ENIS School, Sfax, Tunisia ABSTRACT Automatic code generation is a standard method in software engineering since it improves the code consistency and reduces the overall development time. In this context, this paper presents a design flow for automatic VHDL code generation of mppSoC (massively parallel processing System-on-Chip) configuration. Indeed, depending on the application requirements, a framework of Netbeans Platform Software Tool named MppSoCGEN was developed in order to accelerate the design process of complex mppSoC. Starting from an architecture parameters design, VHDL code will be automatically generated using parsing method. Configuration rules are proposed to have a correct and valid VHDL syntax configuration. Finally, an automatic generation of Processor Elements and network topologies models of mppSoC architecture will be done for Stratix II device family. Our framework improves its flexibility on Netbeans 5.5 version and centrino duo Core 2GHz with 22 Kbytes and 3 seconds average runtime. Experimental results for reduction algorithm validate our MppSoCGEN design flow and demonstrate the efficiency of generated architectures. KEYWORD MppSoC, Automatic code generation; mppSoC configuration;parsing ; MppSoCGEN; 1. INTRODUCTION Parallel machines are most often used in many modern applications that need regular parallel algorithms and high computing resources, such as image processing and signal processing. Massively parallel architectures, in particular Single Instruction Multiple Data (SIMD) systems, have shown to be powerful executers for data-intensive applications [1].
    [Show full text]
  • ECD.June.2013.Pdf
    -community Post Joining the embedded conversation -community Post Joining the embedded conversation ON THE COVER Embedded Computing Design editors have been on the lookout for this year’s Top Embedded Innovators, and – for the first time this year -– thecommunity Most Influential Women in Post Embedded. Our two contests pulled in many inspirational, www.embedded-computing.com highly qualified candidatesJoining who are theforging embedded new ideas conversation and making a difference in the embedded industry. Read June 2013 | Volume 11 • Number 4 about the winners in this edition’s exclusive Q&As, and check out the nominees for Most Innovative Product, winners to be announced in our August edition. 7 Tracking Trends in Embedded Technology 54 -community Post Top Innovators streamline embedded technology Joining the embedded conversation By Warren Webb By Sharon Hess Silicon Software Strategies Multicore processors Finding an operating system Small form factors 8 24 31 Moving target: EEMBC evolves ▲ Choose the right ▲ VPX helps programmable 28 its benchmark suites to keep pace embedded operating system field of dreams become reality with the multicore revolution By Warren Webb By Kevin Roth, Alpha Data Q&A with Markus Levy, Founder and President of EEMBC Case study: 31 Challenges in incarnating a ARM’s big.LITTLE 11 EXPERT PANEL: 14 credit card sized SBC architecture aims to satisfy the Is EDA as easy as By Pete Lomas, Raspberry Pi hunger for power 1, 2, 3 these days? Q&A with John Goodacre, Director, Roundtable discussion with Wally Rhines, Chairman Technology and Systems, ARM Processor Division and CEO, Mentor Graphics; Brett Cline, Vice President, Forte Design Systems; Marc Serughetti, Business Development Director, Synopsys; Michał Siwinski,´ Director of Product Marketing at Cadence; Bill Neifert, 52 Cofounder and CTO, Carbon Design Systems Editor’s Choice By Sharon Hess Top Embedded Innovators Josh Lee, Cofounder, President, and CEO at Uniquify 34 Darren Humphrey, Sr.
    [Show full text]
  • Inside Chips
    InsideChips.VenturesTM Tracking Fabless, IP & Design-House Startups Volume 6, Number 7 July 2005 Business Microscope 3-D Chip Trends … For more than 30 years, the yearly conference explores market and technology chipmakers have been riding the Moore’s Law speed opportunities in the 3-D space. and performance wave. Without fail, they have been Universities, institutes/consortia, IDMs and a able to rely on reductions in transistor size used in ICs handful of startups are conducting 3-D research to achieve predicted increases in speed and around the world. Table 1 (page 2) highlights the performance. Moore’s Law, which states that chip notable players. DARPA funds most of the university performance doubles approximately every two years, programs in the U.S. held true because the RC delay has been negligible in comparison with signal propagation delay. For Initial 3-D efforts involved package stacking or submicron technology, however, RC delay becomes chip stacking in a single package with wire bond a dominant factor. As the industry moves to submicron feature interconnects. Amkor is a good illustration of this approach. sizes, shrinking two-dimensional chips will become problematic. Begun in 1998, the technology was primarily used for memory stacks. One emerging solution is 3-D integration. The technology is not new but it is becoming increasingly important as researchers One of the early pioneers of 3-D, Irvine Sensors, developed look for solutions beyond the perceived limits of today’s two- stacked chips in which the connections are made over the edge of dimensional devices. the die. One limitation, however, is that all die must be the same size.
    [Show full text]
  • An Introduction to High-Level Synthesis
    High-Level Synthesis An Introduction to High-Level Synthesis Philippe Coussy Michael Meredith Universite´ de Bretagne-Sud, Lab-STICC Forte Design Systems Daniel D. Gajski Andres Takach University of California, Irvine Mentor Graphics today would even think of program- Editor’s note: ming a complex software application High-level synthesis raises the design abstraction level and allows rapid gener- solely by using an assembly language. ation of optimized RTL hardware for performance, area, and power require- In the hardware domain, specification ments. This article gives an overview of state-of-the-art HLS techniques and languages and design methodologies tools. 1,2 ÀÀTim Cheng, Editor in Chief have evolved similarly. For this reason, until the late 1960s, ICs were designed, optimized, and laid out by hand. Simula- THE GROWING CAPABILITIES of silicon technology tion at the gate level appeared in the early 1970s, and and the increasing complexity of applications in re- cycle-based simulation became available by 1979. Tech- cent decades have forced design methodologies niques introduced during the 1980s included place-and- and tools to move to higher abstraction levels. Raising route, schematic circuit capture, formal verification, the abstraction levels and accelerating automation of and static timing analysis. Hardware description lan- both the synthesis and the verification processes have guages (HDLs), such as Verilog (1986) and VHDL for this reason always been key factors in the evolu- (1987), have enabled wide adoption of simulation tion of the design process, which in turn has allowed tools. These HDLs have also served as inputs to logic designers to explore the design space efficiently and synthesis tools leading to the definition of their synthe- rapidly.
    [Show full text]
  • Using Modelsim to Simulate Logic Circuits in Verilog Designs
    Using ModelSim to Simulate Logic Circuits in Verilog Designs For Quartus Prime 16.0 1 Introduction This tutorial is a basic introduction to ModelSim, a Mentor Graphics simulation tool for logic circuits. We show how to perform functional and timing simulations of logic circuits implemented by using Quartus Prime CAD software. The reader is expected to have the basic knowledge of the Verilog hardware description language, and the Altera Quartus® Prime CAD software. Contents: • Introduction to simulation • What is ModelSim? • Functional simulation using ModelSim • Timing simulation using ModelSim Altera Corporation - University Program 1 May 2016 USING MODELSIM TO SIMULATE LOGIC CIRCUITS IN VERILOG DESIGNS For Quartus Prime 16.0 2 Background Designers of digital systems are inevitably faced with the task of testing their designs. Each design can be composed of many modules, each of which has to be tested in isolation and then integrated into a design when it operates correctly. To verify that a design operates correctly we use simulation, which is a process of testing the design by applying inputs to a circuit and observing its behavior. The output of a simulation is a set of waveforms that show how a circuit behaves based on a given sequence of inputs. The general flow of a simulation is shown in Figure1. Figure 1. The simulation flow. There are two main types of simulation: functional and timing simulation. The functional simulation tests the logical operation of a circuit without accounting for delays in the circuit. Signals are propagated through the circuit using logic and wiring delays of zero. This simulation is fast and useful for checking the fundamental correctness of the 2 Altera Corporation - University Program May 2016 USING MODELSIM TO SIMULATE LOGIC CIRCUITS IN VERILOG DESIGNS For Quartus Prime 16.0 designed circuit.
    [Show full text]
  • Exhibition Report
    Exhibition Report Japan Electronics and Information Technology Industries Association (JEITA) Contents Exhibition Outline 1 Exhibition Configuration 2 1. Scope of Exhibits 2 2. Conference 2 3. Number of Exhibitors and Booths 2 4. Suite Exhibits 2 5. Exhibitors 3 Conference Activities 4 1. Exhibitor Seminars 4 2. Keynote Speech 4 3. Special Event Stage 4 4. The 13th FPGA/PLD Design Conference 4 5. FPGA/PLD Design Conference User’s Presentations 4 6. IP(Intellectual Property) Flea Market in EDSFair 4 7. System Design Forum 2006 Conference 4 Other Events and Special Projects 5 1. Opening Ceremony 5 2. University Plaza 5 3. Venture Conpany Pavilion 5 4. EDAC Reception 5 5. Press 5 Number of Visitors 6 Results of Visitor Questionnaire 6-7 Exhibition Outline Name . Electronic Design and Solution Fair 2006 (EDSFair2006) Duration . Thursday, January 26 and Friday, January 27, 2006 (2 days) 10:00 a.m. to 6:00 p.m. Location . Pacifico Yokohama (Halls C-D hall and Annex Hall) 1-1-1 Minato Mirai, Nishi-ku, Yokohama 220-0012, Japan Admission. Exhibition: Free (registration required at show entrance) Conference: Fees charged for some sessions Sponsorship . Japan Electronics and Information Technology Industries Association (JEITA) Cooperation . Electronic Design Automation Consortium (EDAC) Support . Ministry of the Economy, Trade and Industry, Japan (METI) Embassy of the United States of America in Japan Distributors Association of Foreign Semiconductors (DAFS) City of Yokohama Assistance . Institute of Electronics, Information and Communication Engineers (IEICE) Information Processing Society of Japan (IPSJ) Japan Printed Circuit Association (JPCA) Spacial Assistance. Hewlett-Packard Japan, Ltd. Sun Microsystems K.K Management .
    [Show full text]
  • Xcell Journal Issue 50, Fall 2004
    ISSUE 50, FALL 2004ISSUE 50, FALL XCELL JOURNAL XILINX, INC. Issue 50 Fall 2004 XcellXcelljournaljournal THETHE AUTHORITATIVEAUTHORITATIVE JOURNALJOURNAL FORFOR PROGRAMMABLEPROGRAMMABLE LOGICLOGIC USERSUSERS MEMORYMEMORY DESIGNDESIGN Streaming Data at 10 Gbps Control Your QDR Designs PARTNERSHIP 20 Years of Partnership Author! Author! Programmable WorldWorld 20042004 SOFTWARE Algorithmic C Synthesis The Need for Speed MANUFACTURING Lower PCB Mfg. Costs Optimize PCB Routability R COVER STORY FPGAs on Mars The New SPARTAN™-3 Make It You r ASIC The world’s lowest-cost FPGAs Spartan-3 Platform FPGAs deliver everything you need at the price you want. Leading the way in 90nm process technology, the new Spartan-3 devices are driving down costs in a huge range of high-capability, cost-sensitive applications. With the industry’s widest density range in its class — 50K to 5 Million gates — the Spartan-3 family gives you unbeatable value and flexibility. Lots of features … without compromising on price Check it out. You get 18x18 embedded multipliers for XtremeDSP™ processing in a low-cost FPGA. Our unique staggered pad technology delivers a ton of I/Os for total connectivity solutions. Plus our XCITE technology improves signal integrity, while eliminating hundreds of resistors to simplify board layout and reduce your bill of materials. With the lowest cost per I/O and lowest cost per logic cell, Spartan-3 Platform FPGAs are the perfect fit for any design … and any budget. MAKE IT YOUR ASIC The Programmable Logic CompanySM For more information visit www.xilinx.com/spartan3 Pb-free devices available now ©2004 Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124.
    [Show full text]
  • Using Systemc for High-Level Synthesis and Integration with TLM
    Using SystemC for high-level synthesis and integration with TLM Presented at India SystemC User Group (ISCUG) http://www.iscug.in April 14, 2013 Mike Meredith – VP Strategic Marketing Forte Design Systems © 2013 Forte Design Systems Agenda • High-level synthesis • Keys to raising abstraction level – A brief history of high-level – Implicit state machine synthesis vs explicit state machine – What is HLS? – Design exploration – HLS Basics – HLS and Arrays • Synthesizability – HLS and I/O protocols – Introduction to the • Integrating synthesizable code synthesizable subset standard in TLM models draft • User Experience – Recommendations and extensions © 2013 Forte Design Systems 2 A Brief History Of High-level Synthesis © 2013 Forte Design Systems 3 What’s In A Name? Algorithmic Behavioral Synthesis Synthesis ESL Synthesis High-level Synthesis © 2013 Forte Design Systems 4 Synthesizing Hardware From A High-level Description -- Not a New Idea! Generation 0 Generation 1 Generation 2 Research First Industrial Tools C-based Tools 1970’s 1980’s 1990’s 2000’s Today • Generation 0 - Research – 1970’s - 1990 – First mention (that I can find) - 1974 • CMU: Barbacci, Siewiorek “Some aspects of the symbolic manipulation of computer descriptions” – A sampling of key researchers: • Thomas, Paulin, Gajski, Wakabayashi, DeMann – Academic implementations • 1979 CMU - CMU-DA • 1988 Stanford Hercules – Most research focused on scheduling and allocation for datapath-dominated designs © 2013 Forte Design Systems 5 Generation 1 - 1990’s Generation 0 Generation
    [Show full text]
  • Introduction to Simulation of VHDL Designs Using Modelsim Graphical Waveform Editor
    Introduction to Simulation of VHDL Designs Using ModelSim Graphical Waveform Editor For Quartus II 13.1 1 Introduction This tutorial provides an introduction to simulation of logic circuits using the Graphical Waveform Editor in the ModelSim Simulator. It shows how the simulator can be used to perform functional simulation of a circuit specified in VHDL hardware description language. It is intended for a student in an introductory course on logic circuits, who has just started learning this material and needs to acquire quickly a rudimentary understanding of simulation. Contents: • Design Project • Creating Waveforms for Simulation • Simulation • Making Changes and Resimulating • Concluding Remarks Altera Corporation - University Program 1 October 2013 INTRODUCTION TO SIMULATION OF VHDL DESIGNS USING MODELSIM GRAPHICAL WAVEFORM EDITOR For Quartus II 13.1 2 Background ModelSim is a powerful simulator that can be used to simulate the behavior and performance of logic circuits. This tutorial gives a rudimentary introduction to functional simulation of circuits, using the graphical waveform editing capability of ModelSim. It discusses only a small subset of ModelSim features. The simulator allows the user to apply inputs to the designed circuit, usually referred to as test vectors, and to observe the outputs generated in response. The user can use the Waveform Editor to represent the input signals as waveforms. In this tutorial, the reader will learn about: • Test vectors needed to test the designed circuit • Using the ModelSim Graphical Waveform Editor to draw test vectors • Functional simulation, which is used to verify the functional correctness of a synthesized circuit This tutorial is aimed at the reader who wishes to simulate circuits defined by using the VHDL hardware description language.
    [Show full text]
  • Programmable Logic Design Quick Start Handbook
    00-Beginners Book front.fm Page i Wednesday, October 8, 2003 10:58 AM Programmable Logic Design Quick Start Handbook by Karen Parnell and Nick Mehta August 2003 Xilinx • i 00-Beginners Book front.fm Page ii Wednesday, October 8, 2003 10:58 AM PROGRAMMABLE LOGIC DESIGN: QUICK START HANDBOOK • © 2003, Xilinx, Inc. “Xilinx” is a registered trademark of Xilinx, Inc. Any rights not expressly granted herein are reserved. The Programmable Logic Company is a service mark of Xilinx, Inc. All terms mentioned in this book are known to be trademarks or service marks and are the property of their respective owners. Use of a term in this book should not be regarded as affecting the validity of any trade- mark or service mark. All rights reserved. No part of this book may be reproduced, in any form or by any means, without written permission from the publisher. PN 0402205 Rev. 3, 10/03 Xilinx • ii 00-Beginners Book front.fm Page iii Wednesday, October 8, 2003 10:58 AM ABSTRACT Whether you design with discrete logic, base all of your designs on micro- controllers, or simply want to learn how to use the latest and most advanced programmable logic software, you will find this book an interesting insight into a different way to design. Programmable logic devices were invented in the late 1970s and have since proved to be very popular, now one of the largest growing sectors in the semi- conductor industry. Why are programmable logic devices so widely used? Besides offering designers ultimate flexibility, programmable logic devices also provide a time-to-market advantage and design integration.
    [Show full text]