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EP Activity Report 2014
EUROPRACTICE IC SERVICE THE RIGHT COCKTAIL OF ASIC SERVICES EUROPRACTICE IC SERVICE OFFERS YOU A PROVEN ROUTE TO ASICS THAT FEATURES: • Low-cost ASIC prototyping • Flexible access to silicon capacity for small and medium volume production quantities • Partnerships with leading world-class foundries, assembly and testhouses • Wide choice of IC technologies • Distribution and full support of high-quality cell libraries and design kits for the most popular CAD tools • RTL-to-Layout service for deep-submicron technologies • Front-end ASIC design through Alliance Partners Industry is rapidly discovering the benefits of using the EUROPRACTICE IC service to help bring new product designs to market quickly and cost-effectively. The EUROPRACTICE ASIC route supports especially those companies who don’t need always the full range of services or high production volumes. Those companies will gain from the flexible access to silicon prototype and production capacity at leading foundries, design services, high quality support and manufacturing expertise that includes IC manufacturing, packaging and test. This you can get all from EUROPRACTICE IC service, a service that is already established for 20 years in the market. THE EUROPRACTICE IC SERVICES ARE OFFERED BY THE FOLLOWING CENTERS: • imec, Leuven (Belgium) • Fraunhofer-Institut fuer Integrierte Schaltungen (Fraunhofer IIS), Erlangen (Germany) This project has received funding from the European Union’s Seventh Programme for research, technological development and demonstration under grant agreement N° 610018. This funding is exclusively used to support European universities and research laboratories. By courtesy of imec FOREWORD Dear EUROPRACTICE customers, Time goes on. A year passes very quickly and when we look around us we see a tremendous rapidly changing world. -
Die Virtuelle Plattform: Der Einsatz Von Zynq Fuer Die Verifikation Und Das Debugging Von Konfigurierbaren Systemen
Die virtuelle Plattform: Der Einsatz von Zynq fuer die Verifikation und das Debugging von konfigurierbaren Systemen Dr. Endric Schubert Missing Link Electronics Marlene-Dietrich-Straße 5 89231 Neu-Ulm www.missinglinkelectronics.com Tel: +49 (731) 141-149-0 Courtesy Xilinx 1 Challenges of Debugging Your Own ASSP © Missing Link Electronics 12. Juli 2012 2 Another Challenge When Building Your Own ASSP: Making Hardware and Software Work Together. © Missing Link Electronics 12. Juli 2012 3 ASSP System-on-Chip Design – An Embedded Designers Life © Missing Link Electronics 12. Juli 2012 4 What is a Virtual Platform? © Missing Link Electronics 12. Juli 2012 5 Virtual Platform Methodology © Missing Link Electronics 12. Juli 2012 6 Virtual Platforms Can Run Software Fast (Sometimes Faster Than Real) © Missing Link Electronics 12. Juli 2012 7 What is SystemC? Open Source Library managed by Open SystemC Initiative (OSCI) Extension to ISO C++ www.systemc.org Means to express concurrency Communication mechanisms Reactivity Concept of Time Current members: ARM Ltd. Cadence Design Systems, Inc. CoWare, Inc. Forte Design Systems Intel Event driven simulation kernel Corporation Mentor Graphics Corporation NXP Semiconductors STMicroelectronics Synopsys, Inc. Actis Design, LLC Atrenta, Inc. Bluespec, Inc. Broadcom - A modeling methodology Corporation Calypto Design Systems, Inc. Canon Inc. Carbon Design Systems Celoxica Ltd. ChipVision Design Systems AG Denali Software Inc. Doulos Ltd. ESLX, Inc. Fraunhofer Institute for Integrated Circuits Freescale Semiconductor Inc. GreenSocs Ltd. Industrial Technology Research Institute (ITRI) JEDA Technologies Inc. Infineon Technologies AG NEC Corporation Semiconductor Technology Academic Research Center (STARC) SpringSoft, Inc. Synfora Inc. Tenison EDA VaST Systems Technology Corporation © Missing Link Electronics 12. -
Download the Compiled Program File Onto the Chip
International Journal of Computer Science & Information Technology (IJCSIT) Vol 4, No 2, April 2012 MPP SOCGEN: A FRAMEWORK FOR AUTOMATIC GENERATION OF MPP SOC ARCHITECTURE Emna Kallel, Yassine Aoudni, Mouna Baklouti and Mohamed Abid Electrical department, Computer Embedded System Laboratory, ENIS School, Sfax, Tunisia ABSTRACT Automatic code generation is a standard method in software engineering since it improves the code consistency and reduces the overall development time. In this context, this paper presents a design flow for automatic VHDL code generation of mppSoC (massively parallel processing System-on-Chip) configuration. Indeed, depending on the application requirements, a framework of Netbeans Platform Software Tool named MppSoCGEN was developed in order to accelerate the design process of complex mppSoC. Starting from an architecture parameters design, VHDL code will be automatically generated using parsing method. Configuration rules are proposed to have a correct and valid VHDL syntax configuration. Finally, an automatic generation of Processor Elements and network topologies models of mppSoC architecture will be done for Stratix II device family. Our framework improves its flexibility on Netbeans 5.5 version and centrino duo Core 2GHz with 22 Kbytes and 3 seconds average runtime. Experimental results for reduction algorithm validate our MppSoCGEN design flow and demonstrate the efficiency of generated architectures. KEYWORD MppSoC, Automatic code generation; mppSoC configuration;parsing ; MppSoCGEN; 1. INTRODUCTION Parallel machines are most often used in many modern applications that need regular parallel algorithms and high computing resources, such as image processing and signal processing. Massively parallel architectures, in particular Single Instruction Multiple Data (SIMD) systems, have shown to be powerful executers for data-intensive applications [1]. -
ECD.June.2013.Pdf
-community Post Joining the embedded conversation -community Post Joining the embedded conversation ON THE COVER Embedded Computing Design editors have been on the lookout for this year’s Top Embedded Innovators, and – for the first time this year -– thecommunity Most Influential Women in Post Embedded. Our two contests pulled in many inspirational, www.embedded-computing.com highly qualified candidatesJoining who are theforging embedded new ideas conversation and making a difference in the embedded industry. Read June 2013 | Volume 11 • Number 4 about the winners in this edition’s exclusive Q&As, and check out the nominees for Most Innovative Product, winners to be announced in our August edition. 7 Tracking Trends in Embedded Technology 54 -community Post Top Innovators streamline embedded technology Joining the embedded conversation By Warren Webb By Sharon Hess Silicon Software Strategies Multicore processors Finding an operating system Small form factors 8 24 31 Moving target: EEMBC evolves ▲ Choose the right ▲ VPX helps programmable 28 its benchmark suites to keep pace embedded operating system field of dreams become reality with the multicore revolution By Warren Webb By Kevin Roth, Alpha Data Q&A with Markus Levy, Founder and President of EEMBC Case study: 31 Challenges in incarnating a ARM’s big.LITTLE 11 EXPERT PANEL: 14 credit card sized SBC architecture aims to satisfy the Is EDA as easy as By Pete Lomas, Raspberry Pi hunger for power 1, 2, 3 these days? Q&A with John Goodacre, Director, Roundtable discussion with Wally Rhines, Chairman Technology and Systems, ARM Processor Division and CEO, Mentor Graphics; Brett Cline, Vice President, Forte Design Systems; Marc Serughetti, Business Development Director, Synopsys; Michał Siwinski,´ Director of Product Marketing at Cadence; Bill Neifert, 52 Cofounder and CTO, Carbon Design Systems Editor’s Choice By Sharon Hess Top Embedded Innovators Josh Lee, Cofounder, President, and CEO at Uniquify 34 Darren Humphrey, Sr. -
Inside Chips
InsideChips.VenturesTM Tracking Fabless, IP & Design-House Startups Volume 6, Number 7 July 2005 Business Microscope 3-D Chip Trends … For more than 30 years, the yearly conference explores market and technology chipmakers have been riding the Moore’s Law speed opportunities in the 3-D space. and performance wave. Without fail, they have been Universities, institutes/consortia, IDMs and a able to rely on reductions in transistor size used in ICs handful of startups are conducting 3-D research to achieve predicted increases in speed and around the world. Table 1 (page 2) highlights the performance. Moore’s Law, which states that chip notable players. DARPA funds most of the university performance doubles approximately every two years, programs in the U.S. held true because the RC delay has been negligible in comparison with signal propagation delay. For Initial 3-D efforts involved package stacking or submicron technology, however, RC delay becomes chip stacking in a single package with wire bond a dominant factor. As the industry moves to submicron feature interconnects. Amkor is a good illustration of this approach. sizes, shrinking two-dimensional chips will become problematic. Begun in 1998, the technology was primarily used for memory stacks. One emerging solution is 3-D integration. The technology is not new but it is becoming increasingly important as researchers One of the early pioneers of 3-D, Irvine Sensors, developed look for solutions beyond the perceived limits of today’s two- stacked chips in which the connections are made over the edge of dimensional devices. the die. One limitation, however, is that all die must be the same size. -
Formal Hardware Specification Languages for Protocol Compliance Verification
Formal Hardware Specification Languages for Protocol Compliance Verification ANNETTE BUNKER and GANESH GOPALAKRISHNAN University of Utah and SALLY A. MCKEE Cornell University The advent of the system-on-chip and intellectual property hardware design paradigms makes pro- tocol compliance verification increasingly important to the success of a project. One of the central tools in any verification project is the modeling language, and we survey the field of candidate languages for protocol compliance verification, limiting our discussion to languages originally in- tended for hardware and software design and verification activities. We frame our comparison by first constructing a taxonomy of these languages, and then by discussing the applicability of each approach to the compliance verification problem. Each discussion includes a summary of the devel- opment of the language, an evaluation of the language’s utility for our problem domain, and, where feasible, an example of how the language might be used to specify hardware protocols. Finally, we make some general observations regarding the languages considered. Categories and Subject Descriptors: B.4.3 [Input/Output and Data Communications]: Inter- connections (Subsystems)—Interfaces; B.4.5 [Input/Output and Data Communications]: Reli- ability, Testing, and Fault-Tolerance—Hardware reliability; B.7.2 [Integrated Circuits]: Design aids—Verification; C.2.2 [Computer-Communication Networks]: Network Protocols—Protocol verification; D.3.3 [Programming Languages]: Language Constructs and Features—Data types -
Technical Portion
50 50 YEARS OF INNOVATION DESIGN AUTOMATION CONFERENCE Celebrating 50 Years of Innovation! www.DAC.com JUNE 2-6, 2013 AUSTIN CONVENTION CENTER - AUSTIN, TX SPONSORED BY: IN TECHNICAL COOPERATION WITH: 1 2 TABLE OF CONTENTS General Chair’s Welcome ....................................................................................................................... 4 Sponsors ................................................................................................................................................. 5 Important Information ............................................................................................................................ 6 Networking Receptions .......................................................................................................................... 7 Keynotes ....................................................................................................................................8,9,13-15 Kickin’ it up in Austin Party .................................................................................................................. 10 Global Forum ........................................................................................................................................ 11 Awards .................................................................................................................................................. 12 Technical Sessions ..........................................................................................................................16-36 -
An Introduction to High-Level Synthesis
High-Level Synthesis An Introduction to High-Level Synthesis Philippe Coussy Michael Meredith Universite´ de Bretagne-Sud, Lab-STICC Forte Design Systems Daniel D. Gajski Andres Takach University of California, Irvine Mentor Graphics today would even think of program- Editor’s note: ming a complex software application High-level synthesis raises the design abstraction level and allows rapid gener- solely by using an assembly language. ation of optimized RTL hardware for performance, area, and power require- In the hardware domain, specification ments. This article gives an overview of state-of-the-art HLS techniques and languages and design methodologies tools. 1,2 ÀÀTim Cheng, Editor in Chief have evolved similarly. For this reason, until the late 1960s, ICs were designed, optimized, and laid out by hand. Simula- THE GROWING CAPABILITIES of silicon technology tion at the gate level appeared in the early 1970s, and and the increasing complexity of applications in re- cycle-based simulation became available by 1979. Tech- cent decades have forced design methodologies niques introduced during the 1980s included place-and- and tools to move to higher abstraction levels. Raising route, schematic circuit capture, formal verification, the abstraction levels and accelerating automation of and static timing analysis. Hardware description lan- both the synthesis and the verification processes have guages (HDLs), such as Verilog (1986) and VHDL for this reason always been key factors in the evolu- (1987), have enabled wide adoption of simulation tion of the design process, which in turn has allowed tools. These HDLs have also served as inputs to logic designers to explore the design space efficiently and synthesis tools leading to the definition of their synthe- rapidly. -
Software-Defined Hardware Provides the Key to High-Performance Data
Software-Defined Hardware Provides the Key to High-Performance Data Acceleration (WP019) Software-Defined Hardware Provides the Key to High- Performance Data Acceleration (WP019) November 13, 2019 White Paper Executive Summary Across a wide range of industries, data acceleration is the key to building efficient, smart systems. Traditional general-purpose processors are falling short in their ability to support the performance and latency constraints that users have. A number of accelerator technologies have appeared to fill the gap that are based on custom silicon, graphics processors or dynamically reconfigurable hardware, but the key to their success is their ability to integrate into an environment where high throughput, low latency and ease of development are paramount requirements. A board-level platform developed jointly by Achronix and BittWare has been optimized for these applications, providing developers with a rapid path to deployment for high-throughput data acceleration. A Growing Demand for Distributed Acceleration There is a massive thirst for performance to power a diverse range of applications in both cloud and edge computing. To satisfy this demand, operators of data centers, network hubs and edge-computing sites are turning to the technology of customized accelerators. Accelerators are a practical response to the challenges faced by users with a need for high-performance computing platforms who can no longer count on traditional general-purpose CPUs, such as those in the Intel Xeon family, to support the growth in demand for data throughput. The core of the problem with the general- purpose CPU is that Moore's Law continues to double the number of available transistors per square millimeter approximately every two years but no longer allows for growth in clock speeds. -
EP Activity Report 2015
EUROPRACTICE IC SERVICE THE RIGHT COCKTAIL OF ASIC SERVICES EUROPRACTICE IC SERVICE OFFERS YOU A PROVEN ROUTE TO ASICS THAT FEATURES: · .QYEQUV#5+%RTQVQV[RKPI · (NGZKDNGCEEGUUVQUKNKEQPECRCEKV[HQTUOCNNCPFOGFKWOXQNWOGRTQFWEVKQPSWCPVKVKGU · 2CTVPGTUJKRUYKVJNGCFKPIYQTNFENCUUHQWPFTKGUCUUGODN[CPFVGUVJQWUGU · 9KFGEJQKEGQH+%VGEJPQNQIKGU · &KUVTKDWVKQPCPFHWNNUWRRQTVQHJKIJSWCNKV[EGNNNKDTCTKGUCPFFGUKIPMKVUHQTVJGOQUVRQRWNCT%#&VQQNU · 46.VQ.C[QWVUGTXKEGHQTFGGRUWDOKETQPVGEJPQNQIKGU · (TQPVGPF#5+%FGUKIPVJTQWIJ#NNKCPEG2CTVPGTU +PFWUVT[KUTCRKFN[FKUEQXGTKPIVJGDGPG«VUQHWUKPIVJG'74124#%6+%'+%UGTXKEGVQJGNRDTKPIPGYRTQFWEVFGUKIPUVQOCTMGV SWKEMN[CPFEQUVGHHGEVKXGN[6JG'74124#%6+%'#5+%TQWVGUWRRQTVUGURGEKCNN[VJQUGEQORCPKGUYJQFQP°VPGGFCNYC[UVJG HWNNTCPIGQHUGTXKEGUQTJKIJRTQFWEVKQPXQNWOGU6JQUGEQORCPKGUYKNNICKPHTQOVJG¬GZKDNGCEEGUUVQUKNKEQPRTQVQV[RGCPF RTQFWEVKQPECRCEKV[CVNGCFKPIHQWPFTKGUFGUKIPUGTXKEGUJKIJSWCNKV[UWRRQTVCPFOCPWHCEVWTKPIGZRGTVKUGVJCVKPENWFGU+% OCPWHCEVWTKPIRCEMCIKPICPFVGUV6JKU[QWECPIGVCNNHTQO'74124#%6+%'+%UGTXKEGCUGTXKEGVJCVKUCNTGCF[GUVCDNKUJGF HQT[GCTUKPVJGOCTMGV THE EUROPRACTICE IC SERVICES ARE OFFERED BY THE FOLLOWING CENTERS: · KOGE.GWXGP $GNIKWO · (TCWPJQHGT+PUVKVWVHWGT+PVGITKGTVG5EJCNVWPIGP (TCWPJQHGT++5 'TNCPIGP )GTOCP[ This project has received funding from the European Union’s Seventh Programme for research, technological development and demonstration under grant agreement N° 610018. This funding is exclusively used to support European universities and research laboratories. © imec FOREWORD Dear EUROPRACTICE customers, We are at the start of the -
Introduction to Verilog HDL
Introduction to Verilog HDL Jorge Ramírez Corp Application Engineer Synopsys University Courseware Copyright © 2011 Synopsys, Inc. All rights reserved. Developed by: Jorge Ramirez Outline Lexical elements • HDL Verilog Data type representation Structures and Hierarchy • Synthesis Verilog tutorial Operators • Assignments Synthesis coding guidelines Control statements • Verilog - Test bench Task and functions Generate blocks • Fine State Machines • References Synopsys University Courseware Copyright © 2011 Synopsys, Inc. All rights reserved. Developed by: Jorge Ramirez HDL VERILOG Synopsys University Courseware Copyright © 2011 Synopsys, Inc. All rights reserved. Developed by: Jorge Ramirez What is HDL? • Hard & Difficult Language? – No, means Hardware Description Language • High Level Language – To describe the circuits by syntax and sentences – As oppose to circuit described by schematics • Widely used HDLs – Verilog – Similar to C – SystemVerilog – Similar to C++ – VHDL – Similar to PASCAL Synopsys University Courseware Copyright © 2011 Synopsys, Inc. All rights reserved. Developed by: Jorge Ramirez Verilog • Verilog was developed by Gateway Design Automation as a proprietary language for logic simulation in 1984. • Gateway was acquired by Cadence in 1989 • Verilog was made an open standard in 1990 under the control of Open Verilog International. • The language became an IEEE standard in 1995 (IEEE STD 1364) and was updated in 2001 and 2005. Synopsys University Courseware Copyright © 2011 Synopsys, Inc. All rights reserved. Developed by: Jorge Ramirez SystemVerilog • SystemVerilog is the industry's first unified hardware description and verification language • Started with Superlog language to Accellera in 2002 • Verification functionality (base on OpenVera language) came from Synopsys • In 2005 SystemVerilog was adopted as IEEE Standard (1800-2005). The current version is 1800-2009 Synopsys University Courseware Copyright © 2011 Synopsys, Inc. -
Tarasenko Magistr.Pdf
НАЦІОНАЛЬНИЙ ТЕХНІЧНИЙ УНІВЕРСИТЕТ УКРАЇНИ «КИЇВСЬКИЙ ПОЛІТЕХНІЧНИЙ ІНСТИТУТ імені ІГОРЯ СІКОРСЬКОГО» ФАКУЛЬТЕТ ПРИКЛАДНОЇ МАТЕМАТИКИ КАФЕДРА СИСТЕМНОГО ПРОГРАМУВАННЯ І СПЕЦІАЛІЗОВАНИХ КОМП’ЮТЕРНИХ СИСТЕМ «На правах рукопису» «До захисту допущено» УДК 004.31 Завідувач кафедри СПСКС __________ В.П.Тарасенко_ (підпис) (ініціали, прізвище) “___”_____________2018р. Магістерська дисертація на здобуття ступеня магістра зі спеціальності 123 Комп‘ютерна інженерія (Спеціалізовані комп‘ютерні системи) на тему: «Методи захисту спеціалізованих моніторингових комп’ютерних засобів на ПЛІС» Виконав: студент II курсу, групи КВ-63м (шифр групи) Тарасенко Георгій Олегович (прізвище, ім’я, по батькові) (підпис) Науковий керівник к.т.н., доцент Клятченко Ярослав Михайлович (посада, науковий ступінь, вчене звання, прізвище та ініціали) (підпис) Рецензент д.т.н., професор Симоненко Валерій Павлович (посада, науковий ступінь, вчене звання, науковий ступінь, прізвище та ініціали) (підпис) Засвідчую, що у цій магістерській дисертації немає запозичень з праць інших авторів без відповідних посилань. Студент _____________ (підпис) Київ – 2018 року НАЦІОНАЛЬНИЙ ТЕХНІЧНИЙ УНІВЕРСИТЕТ УКРАЇНИ «КИЇВСЬКИЙ ПОЛІТЕХНІЧНИЙ ІНСТИТУТ імені ІГОРЯ СІКОРСЬКОГО» Факультет прикладної математики Кафедра системного програмування і спеціалізованих комп’ютерних систем Рівень вищої освіти – другий (магістерський) Спеціальність 123 Комп‘ютерна інженерія Спеціалізовані комп‘ютерні системи ЗАТВЕРДЖУЮ Завідувач кафедри СПСКС __________ _В.П.Тарасенко__ (підпис) (ініціали, прізвище) «___»_____________2018р.