Vysok´E Uˇcení Technick´E V Brnˇe

VYSOKEU´ CENˇ Í TECHNICKE´ V BRNEˇ BRNO UNIVERSITY OF TECHNOLOGY FAKULTA INFORMACNˇ ÍCH TECHNOLOGIÍ USTAV´ POCˇ ÍTACOVˇ YCH´ SYSTEM´ U˚ FACULTY OF INFORMATION TECHNOLOGY DEPARTMENT OF COMPUTER SYSTEMS NEW METHODS FOR INCREASING EFFICIENCY AND SPEED OF FUNCTIONAL VERIFICATION DIZERTACNˇ Í PRACE´ PHD THESIS AUTOR PRACE´ Ing. MARCELA SIMKOVˇ A´ AUTHOR BRNO 2015 VYSOKEU´ CENˇ Í TECHNICKE´ V BRNEˇ BRNO UNIVERSITY OF TECHNOLOGY FAKULTA INFORMACNˇ ÍCH TECHNOLOGIÍ USTAV´ POCˇ ÍTACOVˇ YCH´ SYSTEM´ U˚ FACULTY OF INFORMATION TECHNOLOGY DEPARTMENT OF COMPUTER SYSTEMS METODY AKCELERACE VERIFIKACE LOGICKYCH´ OBVODU˚ NEW METHODS FOR INCREASING EFFICIENCY AND SPEED OF FUNCTIONAL VERIFICATION DIZERTACNˇ Í PRACE´ PHD THESIS AUTOR PRACE´ Ing. MARCELA SIMKOVˇ A´ AUTHOR VEDOUCÍ PRACE´ Doc. Ing. ZDENEKˇ KOTASEK,´ CSc. SUPERVISOR BRNO 2015 Abstrakt Priˇ vyvoji´ soucasnˇ ych´ cˇ´ıslicovych´ system´ u,˚ napr.ˇ vestavenˇ ych´ systemu´ a pocˇ´ıtacovˇ eho´ hardware, je nutne´ hledat postupy, jak zvy´sitˇ jejich spolehlivost. Jednou z moznostˇ ´ı je zvysovˇ an´ ´ı efektivity a rychlosti verifikacnˇ ´ıch procesu,˚ ktere´ se provad´ ejˇ ´ı v ranych´ faz´ ´ıch navrhu.´ V teto´ dizertacnˇ ´ı praci´ se pozornost venujeˇ verifikacnˇ ´ımu prˇ´ıstupu s nazvem´ funkcnˇ ´ı verifikace. Je identifikovano´ nekolikˇ vyzev´ a problemu´ tykaj´ ´ıc´ıch se efektivity a rychlosti funkcnˇ ´ı verifikace a ty jsou nasledn´ eˇ reˇ senyˇ v c´ılech dizertacnˇ ´ı prace.´ Prvn´ı c´ıl se zameˇrujeˇ na redukci simulacnˇ ´ıho casuˇ v prub˚ ehuˇ verifikace komplexn´ıch system´ u.˚ Duvodem˚ je, zeˇ simulace inherentneˇ paraleln´ıho hardwaroveho´ systemu´ trva´ velmi dlouho v porovnan´ ´ı s behemˇ v skutecnˇ em´ hardware. Je proto navrhnuta optimalizacnˇ ´ı technika, ktera´ umist’uje verifikovany´ system´ do FPGA akceleratoru,´ zat´ım co cˇast´ verifikacnˇ ´ıho prostredˇ ´ı stale´ beˇzˇ´ı v simulaci. T´ımto premˇ ´ıstenˇ ´ım je moznˇ e´ vyrazn´ eˇ zredukovat simulacnˇ ´ı rezii.ˇ Druhy´ c´ıl se zabyv´ a´ rucnˇ eˇ pripravovanˇ ymi´ verifikacnˇ ´ımi prostredˇ ´ımi, ktera´ predstavujˇ ´ı vyrazn´ e´ omezen´ı ve verifikacnˇ ´ı produktivite.ˇ Tato rezieˇ vsakˇ nen´ı nutna,´ protozeˇ vetˇ sinaˇ verifikacnˇ ´ıch prostredˇ ´ı ma´ velice podobnou strukturu, jelikozˇ vyuzˇ´ıvaj´ı komponenty standardn´ıch verifikacnˇ ´ıch metodik. Tyto komponenty se jen upravuj´ı s ohledem na verifikovany´ system.´ Proto druha´ opti- malizacnˇ ´ı technika analyzuje popis systemu´ na vysˇsˇ´ı urovni´ abstrakce a automatizuje tvorbu veri- fikacnˇ ´ıch prostredˇ ´ı t´ım, zeˇ je automaticky generuje z tohoto vysoko-urov´ novˇ eho´ popisu. Tretˇ ´ı c´ıl zkouma,´ jak je moznˇ e´ doc´ılit uplnost´ verifikace pomoc´ı inteligentn´ı automatizace. Uplnost´ verifikace se typicky meˇrˇ´ı pomoc´ı ruzn˚ ych´ metrik pokryt´ı a verifikace je ukoncena,ˇ kdyzˇ je dosazenaˇ prav´ eˇ vysoka´ urove´ nˇ pokryt´ı. Proto je navrzenaˇ tretˇ ´ı optimalizacnˇ ´ı technika, ktera´ rˇ´ıd´ı generovan´ ´ı vstupu˚ pro verifikovany´ system´ tak, aby tyto vstupy aktivovali soucasnˇ eˇ co nejv´ıc bodu˚ pokryt´ı a aby byla rychlost konvergence k maximaln´ ´ımu pokryt´ı co nejvysˇsˇ´ı. Jako hlavn´ı optimalizacnˇ ´ı prostredekˇ se pouzˇ´ıva´ geneticky´ algoritmus, ktery´ je prizpˇ usoben˚ pro funkcnˇ ´ı verifikaci a jeho parametry jsou vyladenyˇ pro tuto domenu.´ Beˇzˇ´ı na pozad´ı verifikacnˇ ´ıho procesu, analyzuje dosazenˇ e´ pokryt´ı a na zaklad´ eˇ toho dynamicky upravuje omezuj´ıc´ı podm´ınky pro generator´ vstupu.˚ Tyto podm´ınky jsou reprezentovany´ pravdepodobnostmi,ˇ ktere´ urcujˇ ´ı vyb´ erˇ vhodnych´ hodnot ze vstupn´ı domeny.´ Ctvrtˇ y´ c´ıl diskutuje, zda je moznˇ e´ znovu pouzˇ´ıt vstupy z funkcnˇ ´ı verifikace pro ućelyˇ regresn´ıho testovan´ ´ı a optimalizovat je tak, aby byla rychlost testovan´ ´ı co nejvysˇsˇ´ı. Ve funkcnˇ ´ı verifikaci je totizˇ beˇznˇ e,´ zeˇ vstupy jsou znacnˇ eˇ redundantn´ı, jelikozˇ jsou produkovany´ generatorem.´ Pro regresn´ı testy ale tato redundance nen´ı potrebnˇ a´ a proto mu˚zeˇ byt´ eliminovana.´ Zarove´ nˇ je ale nutne´ dbat´ na to, aby urove´ nˇ pokryt´ı dosahnut´ a´ optimalizovanou sadou byla stejna,´ jako u te´ puvodn˚ ´ı. Ctvrtˇ a´ optimalizacnˇ ´ı technika toto reflektuje a opetˇ pouzˇ´ıva´ geneticky´ algoritmus jako optimalizacnˇ ´ı prostredek.ˇ Tentokrat´ ale nen´ı integrovan´ do procesu verifikace, ale je pouzitˇ azˇ po jej´ı ukoncenˇ ´ı. Velmi rychle odstranujeˇ redundanci z puvodn˚ ´ı sady vstupu˚ a vysledn´ a´ doba simulace je tak znacnˇ eˇ optimalizovana.´ Kl´ıcovˇ a´ slova Funcnˇ ´ı verifikace, verifikace zalozenˇ a´ na simulaci, Universal Verification Methodology, System- Verilog, optimalizace, automatizace, geneticky´ algoritmus, verifikace rˇ´ızena´ pokryt´ım, metriky pokryt´ı. Citace Marcela Simkovˇ a:´ New Methods for Increasing Efficiency and Speed of Functional Verification [dizertacnˇ ´ı prace],´ Ustav´ pocˇ´ıtacovˇ ych´ system´ u˚ FIT VUT v Brne,ˇ Brno, CZ, 2015 Abstract In the development of current hardware systems, e.g. embedded systems or computer hardware, new ways how to increase their reliability are highly investigated. One way how to tackle the issue of reliability is to increase the efficiency and the speed of verification processes that are performed in the early phases of the design cycle. In this Ph.D. thesis, the attention is focused on the verification approach called functional verification. Several challenges and problems connected with the efficiency and the speed of functional verification are identified and reflected in the goals of the Ph.D. thesis. The first goal focuses on the reduction of the simulation runtime when verifying com- plex hardware systems. The reason is that the simulation of inherently parallel hardware systems is very slow in comparison to the speed of real hardware. The optimization technique is proposed that moves the verified system into the FPGA acceleration board while the rest of the verification environment runs in simulation. By this single move, the simulation overhead can be significantly reduced. The second goal deals with manually written verification environments which represent a huge bottleneck in the verification productivity. However, it is not reasonable, because almost all verification environments have the same structure as they utilize libraries of basic components from the standard verification methodologies. They are only adjusted to the system that is verified. Therefore, the second optimization technique takes the high-level specification of the system and then automatically generates a comprehensive verification environment for this system. The third goal elaborates how the completeness of the verification process can be achieved using the intelli- gent automation. The completeness is measured by different coverage metrics and the verification is usually ended when a satisfying level of coverage is achieved. Therefore, the third optimization technique drives generation of input stimuli in order to activate multiple coverage points in the verified system and to enhance the overall coverage rate. As the main optimization tool the genetic algorithm is used, which is adopted for the functional verification purposes and its parameters are well-tuned for this domain. It is running in the background of the verification process, it analyses the coverage and it dynamically changes constraints of the stimuli generator. Constraints are repre- sented by the probabilities using which particular values from the input domain are selected. The fourth goal discusses the re-usability of verification stimuli for regression testing and how these stimuli can be further optimized in order to speed-up the testing. It is quite common in verification that until a satisfying level of coverage is achieved, many redundant stimuli are evaluated as they are produced by pseudo-random generators. However, when creating optimal regression suites, redundancy is not needed anymore and can be removed. At the same time, it is important to retain the same level of coverage in order to check all the key properties of the system. The fourth optimization technique is also based on the genetic algorithm, but it is not integrated into the verification process but works offline after the verification is ended. It removes the redundancy from the original suite of stimuli very fast and effectively so the resulting verification runtime of the regression suite is significantly improved. Keywords Functional verification, simulation-based verification, Universal Verification Methodology, Sys- temVerilog, optimization, automation, genetic algorithm, coverage-driven verification, coverage metrics. Bibliographic Citation Marcela Simkovˇ a:´ New Methods for Increasing Efficiency and Speed of Functional Verification, Ph.D. thesis, Department of Computer Systems FIT BUT, Brno, CZ, 2015 Prohla´senˇ ´ı Prohlasuji,ˇ zeˇ jsem tuto dizertacnˇ ´ı praci´ vypracovala samostatneˇ pod veden´ım sveho´ skoliteleˇ Doc. Ing. Zdenkaˇ Kotaska,´ CSc., a zeˇ jsem uvedla vsechnyˇ literarn´ ´ı prameny, ze kterych´ jsem v prub˚ ehuˇ sve´ prace´ cerpala.ˇ ....................... Marcela Simkovˇ a´ 14. za´rˇ´ı 2015 Podekovˇ an´ ´ı Dekujiˇ vsem,ˇ kterˇ´ı mi byli oporou priˇ sepisovan´ ´ı teto´ prace´ a byli mi cennymi´ radci´ v prub˚ ehuˇ celeho´ meho´ studia. Jmenoviteˇ dekujiˇ memu´ skoliteli,ˇ panu Doc. Zdenkoviˇ Kotaskovi´ za veden´ı. Dekujiˇ memu´ budouc´ımu manzeloviˇ Michalovi za lasku,´ podporu a povzbuzen´ı. Take´ dekujiˇ Ondrejoviˇ Lengalovi,´ Michalovi Kajanovi a Liborovi Polcˇakovi´ za vyb´ erˇ tematu´ diplomove´ prace,´ ktery´ mneˇ nasmerovalˇ i k tematu´ dizertacnˇ ´ı prace´ a za vsechnyˇ jejich rady a cas,ˇ ktery´ mi venovali.ˇ Dekujiˇ mym´ kolegum˚ z UPSY a z Codasipu, kterˇ´ı se mnou spolupracovali. © Marcela Simkovˇ a,´ 2015. Tato prace´ vznikla jako skolnˇ ´ı d´ılo na Vysokem´ ucenˇ ´ı technickem´ v Brne,ˇ Fakulteˇ informacnˇ ´ıch technologi´ı. Prace´ je chran´ enaˇ autorskym´ zakonem´ a jej´ı uzitˇ ´ı bez udelenˇ ´ı opravn´ enˇ ´ı autorem je nezakonn´ e,´ s vyjimkou´ zakonem´ definovanych´ prˇ´ıpadu.˚ Contents 1 Introduction 6 1.1 Motivation . .6 1.2 Problem Statement . .8 1.3 Thesis Contribution . .8 1.4 Thesis Organization . 10 2 Verification Approaches 11 2.1 Brief History of Design and Verification Methods . 11 2.2 Current Verification Approaches .

Load more