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Vivado Design Suite User Guide: Logic Simulation (UG900)

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Vivado Design Suite User Guide: Logic Simulation (UG900) Vivado Design Suite User Guide Logic Simulation UG900 (v2015.1) April 1, 2015 Revision History The following table shows the revision history for this document. Date Version Revision 04/01/2015 2015.1 Global Changes Book reorganized to reflect design flow structure. Extensive enhancements to content. Updated figures to match feature changes in the 2015.1 release; some figures enhanced for improved viewing. Chapter 1 Added Aldec Active-HDL and Rivera-PRO to the list of supported simulators. Chapter 2 In section UNIFAST Library, GTXE2_CHANNEL/GTXE2_COMMON, added note to bypass the DRP production reset sequence when using the UNIFAST model. Chapter 3 Added description of new right-click options for items in the Objects Window, page 42. Chapter 5 Added new section on Cross Probing Signals in the Object, Wave, and Text Editor Windows. Chapter 7 Added new xelab Command Syntax Options: -Oenable_pass_through_elimination, -Odisable_pass_through_elimination, -Oenable_always_combine, -Odisable_always_combine Chapter 8 Added Riviera PRO simulator (Aldec) to list of supported third-party simulators. Appendix D Noted newly supported constructs in Table D-1, Synthesizable Set of System Verilog 1800-2009. Added Table D-2, Supported Dynamic Types Constructs: Early Access. Appendix E Updated Table E-2, Data Types Allowed on the C-SystemVerilog Boundary. Logic Simulation www.xilinx.com Send Feedback 2 UG900 (v2015.1) April 1, 2015 Table of Contents Chapter 1: Logic Simulation Overview Introduction . 7 Simulation Flow . 7 Supported Simulators . 10 Language and Encryption Support . 11 OS Support and Release Changes . 11 Chapter 2: Preparing for Simulation Introduction . 12 Using Test Benches and Stimulus Files . 13 Adding or Creating Simulation Source Files . 14 Using Xilinx Simulation Libraries. 16 Using Simulation Settings . 27 Understanding the Simulator Language Option . 30 Recommended Simulation Resolution . 32 Generating a Netlist. 32 Chapter 3: Understanding Vivado Simulator Introduction . 34 Vivado Simulator Features . 34 Running the Vivado Simulator . 35 Running Functional and Timing Simulation . 47 Saving Simulation Results . 50 Distinguishing Between Multiple Simulation Runs . 50 Closing a Simulation. 51 Adding a Simulation Start-up Script File. 51 Viewing Simulation Messages. 53 Using the launch_simulation Command . 54 Chapter 4: Analyzing Simulation Waveforms Introduction . 56 Using Wave Configurations and Windows. 56 Opening a Previously Saved Simulation Run . 57 Logic Simulation www.xilinx.com Send Feedback 3 UG900 (v2015.1) April 1, 2015 Understanding HDL Objects in Waveform Configurations . 59 Customizing the Waveform. 62 Controlling the Waveform Display . 69 Organizing Waveforms . 71 Analyzing Waveforms . 73 Chapter 5: Debugging a Design with Vivado Simulator Introduction . 77 Debugging at the Source Level . 77 Forcing Objects to Specific Values . 81 Power Analysis Using Vivado Simulator. 89 Using the report_drivers Tcl Command . 90 Using the Value Change Dump Feature . 91 Using the log_wave Tcl Command . 92 Cross Probing Signals in the Object, Wave, and Text Editor Windows . 93 Chapter 6: Handling Special Cases Using Global Reset and 3-State. 95 Delta Cycles and Race Conditions . 97 Using the ASYNC_REG Constraint . 98 Simulating Configuration Interfaces. 99 Disabling Block RAM Collision Checks for Simulation . 103 Dumping the Switching Activity Interchange Format File for Power Analysis . 104 Simulating a Design with AXI Bus Functional Models . 104 Skipping Compilation or Simulation . 104 Chapter 7: Using Vivado Simulator in Batch or Scripted Mode Introduction . 106 Vivado Simulator Command Line Steps . 106 Elaborating and Generating a Design Snapshot, -xelab . 108 Simulating the Design Snapshot, xsim . 118 Example of Running Vivado Simulator in Standalone Mode . 120 Project File (.prj) Syntax . 121 Predefined Macros. 122 Library Mapping File (xsim.ini) . 122 Running Simulation Modes . 124 Using Tcl Commands and Scripts . 126 Chapter 8: Using Third-Party Simulators Introduction . 127 Logic Simulation www.xilinx.com Send Feedback 4 UG900 (v2015.1) April 1, 2015 Preparing for Simulation Using Third-Party Tools . 127 Running Simulation with Third-Party Tools . ..
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