System Verilog Introduction & Usage
IBM Verification Seminar Author: Johny Srouji, Intel Corporation IEEE P1800 Chair
SystemVerilog Introduction (1) Presentation Objectives • Provide a brief history and status update of SystemVerilog as a HW Design & Verification Language • Provide a high level overview of the language capabilities and usage aspects
‰ This is not meant to be a tutorial of the language ‰ Parts of this presentation are based on material which was presented in DAC SystemVerilog workshop by technical committees chairs
SystemVerilog Introduction (2) Agenda • Background – HW Design Languages – Problem Statement – IEEE P1800 Activity • SystemVerilog Design Modeling • SystemVerilog for Verification – Extensions for Test-Bench Modeling – Assertions • SystemVerilog DPI • A Quiz • Conclusions
SystemVerilog Introduction (3) HW Design Languages • Hardware Description Language (HDL) is used to describe digital hardware elements • Various levels of design abstractions are used: – Behavioral: flow control, arithmetic operators, complex delays – Register Transfer Level (RTL): Structural description of the registers and the signal changes between registers – Gate level: combinatorial logic gates (and, or, not,…) – Switch level: layout description of the wires, resistors and transistors (CMOS,PMOS, etc) • Two main subsets: – Synthesizable – reflecting HW / Silicon – Non-Synthesizable – reflecting instrumentation code
SystemVerilog Introduction (4) The Problem!
e What’s Next? z
• Quest for Performance is driving up i S
complexity n
– Deeper pipelines, increase in logic g i
functionality and complexity, power issues, s e
explosion in flops D Verilog RTL • Explosion in lines of RTL Code making verification a lot harder Schematics • Low Abstraction level of the RTL is driving 80’s 90’s higher verification effort and lower simulation speed – Trillions of cycles per lead project and s Increasing rate g
more pre-silicon bug escapes u b
n
• Verification effort is reaching 60% of the o c i l i
total design cycle s - e r
– Usage of different languages makes it even P
harder: reference models in C/C++, RTL in # Verilog or VHDL, Test Benches, Assertions, Checkers, Coverage Lead Projects
SystemVerilog Introduction (5) Verilog History
Verilog-1995 SystemVerilog 3.0 Gateway started to First IEEE Verilog Accellera develop Verilog Standard Extensions to V2K
1984 1990 1995 2001 2002 2003
Cadence bought Verilog-2001 (V2K) SystemVerilog 3.1 Gateway, and Enhancement – 2nd Extensions to 3.0 started pushing IEEE Verilog Verilog Standard
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SystemVerilog Introduction (6) SystemVerilog SV3.1 Focus: design SystemVerilog 3.1 - HDVL language cleanup Queues Test Bench Assertions APIs OO Classes Semaphores & Lists
SV3.0 Focus: enhance design System Verilog 3.0 language capabilities Data Types Structures Advanced Control Interfaces Casting & Enums & Unions Operators Flow
Verilog2K Multi-D Arrays Generate Automatic Tasks
Verilog95
Gate Level Modeling & Timing Hardware Concurrency
SystemVerilog Introduction (7) SystemVerilog Components
Transaction-Level Advanced V Full Testbench g e verification capability Veriolog h A r Language with il c s il for semiformal and r n se o Teestbench r g Coverage V tb t formal methods. s io e IEEE n The Assertion T Language Standard Verilog I for Verilog V 2001 P D e A e ri & c e lo I a s P rf ig g e n D t Design In Abstraction: Interface Direct C interface, semantics, abstract Assertion API and data types, Coverage API abstract operators and expressions
SystemVerilog Introduction (8) IEEE P1800 Structure Chair - Johny Srouji Vice chair – Shrenik Mehta IEEE P1800 Secretary - Dennis Brophy SystemVerilog WG Program Mgr: Noelle Humenick
Errata Chair: Karen Pieper LRM – Chair: TBD Stu Sutherland
P1800 Errata 1364 Verilog Sub-WG Champions Sub-WG
SV- SV- SV- SV-CC & BTF Encryption Errata BC EC AC PTF
(transfer/merge)
SystemVerilog Introduction (9) SystemVerilog Design Modeling SystemVerilog enhances Verilog for Design Modeling
• Data Types • Capturing Design Intent – SystemVerilog Data Types – always_* Procedural blocks – Packed & Unpacked Arrays – Unique and Priority Case • Data Organization – Nets and Variables – Structures & Unions • Powerful Syntax – Type Casting – Copy / Buffering – Enumerated Data Types – Port Connections • C-like functionality
SystemVerilog Introduction (10) Basic SV3.1 Data Types
reg r; // 4-value Verilog-2001 single-bit datatype integer i; // 4-value Verilog-2001 >= 32-bit datatype bit b; // single bit 0 or 1 logic w; // 4-value logic, x 0 1 or z as in Verilog byte b; // 2 value, 8 bit signed integer int i; // 2-value, 32-bit signed integer shortint s;// 2-value, 16-bit signed integer longint l; // 2-value, 64-bit signed integer
Make your own types using typedef Use typedef to get C compatibility typedef shortint short; typedef longint longlong; typedef real double; typedef shortreal float;
SystemVerilog Introduction (11) Packed And Unpacked Arrays
unpacked a0 bit a [3:0]; a1 array of u n u s e d a2 bits a3
packed array of bit [3:0] p; p 3 p 2 p 1 p 0 bits
bit [15:0] memory [1023:0]; 1k 16 bit memory[i] = ~memory[i+1]; unpacked memory[i] [15:8] = 0; memory Packed indexes can be sliced
1k 16 bit Can operate on packed bit [15:0] [1023:0] Frame; entire memory always @ (posedge inv) memory Frame = ~Frame;
SystemVerilog Introduction (12) Data Organization
• Signals are Meaningful In Groups – Instructions: Operation, Operands • Verilog Provides Only Informal Grouping reg [47:0] PktSrcAdr; reg [31:0] Instruction; reg [47:0] PktDstAdr; `define opcode 31:16 reg [7:0] InstOpCde; Instruction[`opcode] reg [7:0] InstOpRF [127:0];
By Name By Vector Location
• Better to organize data in explicit, meaningful relationships between data elements • SystemVerilog Structs, Unions & Arrays alone or combined better capture design intent
SystemVerilog Introduction (13) Data Organization - Structures struct { addr_t SrcAdr; • Structs Preserve addr_t DstAdr; Logical Grouping data_t Data; } Pkt; • Reference to Struct facilitates more Pkt.SrcAdr = SrcAdr; meaningful code if (Pkt.DstAdr == Node.Adr) LLikikee i nin C C b buut tw witihthoouut t ththee o opptitoionnaal ls strtruucctuturree tags before the { typedef struct { bit [7:0] opcode; tags before the { bit [23:0] addr; } instruction; // named structure type instruction IR; // define variable
IR.opcode = 1; // set field in IR
SystemVerilog Introduction (14) Data Organization - Packed Structures Consists of bit fields, which are packed together in memory without gaps – They are easily converted to and from bit vectors. struct packed { `define Valid 24 bit Valid; `define Tag 23:16 byte Tag; 15:0 bit [15:0] Addr; `define Addr } Entry; iTag = Entry[`Tag]; iTag = Entry.Tag; iAddr = Entry[`Addr]; iAddr = Entry.Addr; iValid = Entry[`Valid] iValid = Entry.Valid
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SystemVerilog Introduction (15) Data Organization - Type Casting int'(2.0 * 3.0) A data type can be changed shortint' {8’hFA, 8’hCE} by using a cast (‘) operation 17 ' (x – 2)
Any aggregate bit-level object can be reshaped OObbjejecctsts m muusst th haavvee Packed ⇔ Unpacked, Array ⇔ Structure idideenntitcicaal lb biti ts sizizee typedef struct { bit [7:0] f1; f1 A bit [7:0] f2; bit [7:0] f3[0:5]; f2 } Unpacked_s; { typedef struct packed f30 f31 f32 f33 f34 f35 bit [15:0][0:2] f1; bit [15:0] f2; } Packed_s; B Unpacked_s A; Packed_s B; f10 f11 f12 f2 … A = Unpacked_s’(B); B = Packed_s’(A);
SystemVerilog Introduction (16) Data Organization - Unions
typedef union { union typedef union { int n; byte [5:0] bytes; real f; provide storage for real rlevel; } u_type; either int or real integer ilevel; } Data_u_t; u_type u; struct { structs and unions can be assigned as a Data_u_t Data; whole logic isBytes; can contain fixed size packed or unpacked logic isReal; arrays logic isInteger; } DPkt; Unpacked Unions Enable Single Variable DPkt.Data = 3.124; to Contain Data from Multiple Types DPkt.IsReal = 1; Data Read from Unpacked Union Must Be if (DPkt.IsReal) from Last Field Written realvar = DPkt.rlevel; Requires Type Awareness
SystemVerilog Introduction (17) Data Organization – Packed Unions
• Packed Unions Enable • Packed Unions Enable Multiple Namespaces for Many Convenient Name Same-Sized, Integer Data References
typedef logic [7:0] byte_t; inst.fields.opcode = 16’hDEAD; typedef struct packed { inst.bytes[1] = 8’hBE; logic [15:0] opcode; inst[7:0] = 8’hEF; logic [1:0] Mod; … inst == 32’hDEADBEEF; logic [2:0] Base; } Instruction_t; typedef union packed { byte_t [3:0] bytes; Instruction_t fields; • No Need To Test Type } Instruction_u; • Data Maps To All Instruction_u inst; Members
SystemVerilog Introduction (18) Data Organization – Tagged Unions • Provide type-safety and brevity • Improve correctness • Improve ability to reason about programs for FV typedef tagged union { struct { bit [4:0] reg1, reg2, regd; } Add; tagIgInensdsttrur n iiinonsnsttr{r;; ...b..i.t [9:0] JmpU; ccasastsereu(c(itinns{sttrr)) mmaattcchheess ttabagiggtgeed[d1A:Ad0dd]d {c{rcr1,1,,rr22,,rrdd}}:: rrff[[rrdd]] == rrff[[rr11]] ++ rrff[[rr22]];; ttabagiggtgeed[d9J:Jm0mp]p jaj:d: d r; ccaassee ((jj)) mmaattcchheess } JmpC; ttaaggggeedd JJmmppUU aa :: ppcc == ppcc ++ aa;; } Jmp; ttaaggggeedd JJmmppCC {{cc,,aa}}:: } Instr; iiff ((rrff[[cc]])) ppcc == aa;; eennddccaassee eennddccaassee
SystemVerilog Introduction (19) Data Organization – Enum typedef enum {red, green, blue, yellow, white, black} Colors; a=2*3=6 Colors col; col=3 integer a, b; b=3+1=4 a = blue * 3; col = yellow; b = col + green; • Finite State Machines typedef enum logic [2:0] {idle, – Currently a List of Parameters init, decode …} fsmstate; fsmstate pstate, nstate; – Why Not A Real List of Values? case (pstate) idle: if (sync) – Enumerate formally defines nstate = init; symbolic set of values init: if (rdy) • Enumerates are strongly typed nstate = decode; to ensure assignment to value … in set endcase typedef enum {lo,hi} byteloc; • Symbolic Indexes to Make memory[addr][hi] = data[hi]; Array References More Readable
SystemVerilog Introduction (20) Design Intent – always_* • In Verilog, always blocks do not //forgot Else but it’s guarantee capture of intent //only a synthesis warning – If not edge-sensitive then only a always @ (a or b) if (b) c = a; warning if latch inferred
• SystemVerilog introduces always_comb three new logic specific a = b & c; processes – Combinational Coding Style – Latch Coding Style always_latch if (en) q <= d – Sequential Logic
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SystemVerilog Introduction (21) Design Intent – always_* • Compiler Now Knows User Intent and can flag errors
always_comb ERROR: combinational logic requested if (en) q <= d; but latch was inferred
always_ff @ (clk, rst_n) ERROR: incorrect sensitivity list if (!rst_n) q <= 0; flip flop not inferred else q <= d;
• Both always @* and always_comb – Ensures synthesis-compatible sensitivity – Helps reduce “spaghetti code” – But, always_comb infers the sensitivity list from within functions called in the always block
SystemVerilog Introduction (22) Design Intent – Unique/Priority
• Verilog synthesis pragmas are “full_case” & “parallel_case” – Pass different information to synthesis and simulator – May cause pre- & post-synthesis simulations differences • SystemVerilog introduces Unique and Priority – Passing the same information to the simulator and synthesis tool – Enables Simulation, Synthesis and FV to behave consistently bit [2:0] a; priority casez (a)// values 4,5,6,7 unique case (a) // values 3,5,6,7 cause // cause run time // run time warning // warning 0,1: $display(“0” or “1”); 3’b00?: $display(“0” or “1”); 2: $display(“2”); 3’b0??: $display(“2” or “3”); 4: $display(“4”); endcase endcase
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SystemVerilog Introduction (23) Design Intent – nets vs. variables
• In Synthesized Design most nets • Multiply Driven, Variable-Strength have a single driver Nets generally take great care to design. Would like these nets to stand out in the design. • Use Net Types to Distinguish
trireg [1:0] dbus; assign dbus = wen[0] ? cff : ‘z; • Combination of SystemVerilog assign dbus = wen[1] ? variables and processes can enforce {cff[0],cff[1]} : ‘z; single driver/avoid multiple drivers • Variables may be driven by only one logic [1:0] n0,n1,n2,n3,n4; assign n0 = {ina,inb}; of the following always_comb – continuous assignment if (sela) n1 = ina; – always_comb else n1 = inb; always_latch – always_latch if (sela) n2 <= ina; – always_ff always_ff @(posedge ck) n3 <= ina; – module port sbuf buf1 (.di(n1),.do(n4)); • Compilers Can Catch Your Mistakes sbuf buf2 (.di(n2),.do(n4));
SystemVerilog Introduction (24) Powerful Syntax – .* Port Connections
• Creating netlists by hand module top(); is tedious logic rd,wr; • Generated netlists are tri [31:0] dbus,abus; unreadable tb tb1(.*); – Many signals in dut dut1(.*); instantiations endmodule – Instantiations cumbersome to manage • Implicit port connections dramatically improve module top(); readability logic rd,wr; tri [31:0] dbus,abus; • Use same signal names tb tb(.*, .ireset(start), up and down hierarchy .oreset(tbreset)); where possible dut d1(.*,.reset(tbreset[0])); dut d2(.*,.reset(tbreset[1])); • Emphasize where port endmodule differences occur
SystemVerilog Introduction (25) Familiar C Features do continue starts begin next loop iteration works with: if ( (n%3) == 0 ) continue; for while if (foo == 22) ; break forever end break exits repeat while (foo != 0); the loop do while … Blocking Assignments Extra parentheses if ( (a=b) ) … required to distinguish as expressions while ((a = b || c)) from if(a==b)
Auto increment/ x++; decrement operators if (--c > 17) c=0; Assignment Operators a += 3; Semantically equivalent s &= mask; to blocking assignment Wildcard Comparisons f <<= 3; X and Z values act as a =?= b wildcards a !?= b
SystemVerilog Introduction (26) SystemVerilog for Verification • SystemVerilog extends the language to include Verification and Test-Bench modeling constructs
• Extended Data Types • Object Oriented Programming – Dynamic Arrays – Class; Object; Methods – Associative Arrays • Communication Encapsulation • Process Synchronization – Interfaces – Semaphors and Event • Assertion Based Design Variables – Assertions Constructs – Mailbox queues – Usage – Processes and Threads
SystemVerilog Introduction (27) Dynamic Arrays
Declaration syntax bit[3:0] fix[0:3];
SystemVerilog Introduction (28) Dynamic Arrays Declaration syntax
SystemVerilog Introduction (29) Associative Arrays • Excellent for Sparse Storage • Elements Not Allocated Until Used • Index Can Be of Any Packed Type, String or Class Declaration syntax
int imem[*]; struct packed {int a; logic[7:0] b} imem[ 2’b3 ] = 1; mystruct; imem[ 16’hffff ] = 2; int myArr [mystruct]; imem[ 4b’1000 ] = 3; //associative array indexed by mystruct Built-in Methods num(), delete([index]), exists(index); first/last/prev/next(ref index); IIddeeaall ffoorr DDeeaalliinngg wwiitthh SSppaarrssee DDaattaa
SystemVerilog Introduction (30) Object-Oriented Programming
• Organize programs in the • Class – A blueprint for a house same way that objects – Program element “containing” related group of features and are organized in the real functionality. world – Encapsulates functionality • Break program into – Provides a template for building blocks that work together objects to accomplish a task, • Properties – It has light switches each block has a well – Variables specific to the class • Methods – Turn on/off the lights defined interface – Tasks/functions specific to the • Focuses on the data and class what you are trying to do • Object – The actual house with it rather than on – An object is an instance of a procedural algorithms class
SystemVerilog Introduction (31) OOP - Class Definition Definition Syntax class name;
“::” operator links method declaration to task Packet::set_cmd(input bit[3:0] a); Class definition cmd = a; endtask
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SystemVerilog Introduction (32) OOP - Class Instantiation • Objects Allocated Packet myPkt = new; and Initialized Via myPkt
Call to the new class Packet; cmd IDLE Constructor ... status 5 function new(); Method cmd = IDLE; header – All objects have endfunction built-in new method endclass Packet myPkt = new; • No arguments • Allocates storage class Packet; for all data ... properties function new(input int a); cmd = IDLE; – User-defined new status = a; method can endfunction initialize and/or do endclass other things Packet myPkt = new(5); // myPkt.status = 5
SystemVerilog Introduction (33) OOP - Class Inheritance & Extension • Keyword extends class ErrPkt extends Packet; Denotes Hierarchy of bit[3:0] err; Definitions function bit[3:0] show_err(); – Subclass inherits return(err); properties and methods endfunction from parent task set_cmd(input bit[3:0] a); – Subclass can redefine cmd = a+1; endtask // overrides Packet::set_cmd methods explicitly endclass
Packet: ErrPkt: cmd cmd status get_status status get_status show_err header header set_cmd set_cmd cmd = a; err cmd = a+1;
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SystemVerilog Introduction (34) Process Synchronization • SystemVerilog adds a powerful and easy-to-use set of synchronization and communication mechanisms – Which can be created and reclaimed dynamically – Dynamic parallel processes using fork/join_any and fork/join_none
fork fork fork
join join_any join_none
• SystemVerilog adds – a semaphore built-in class - for synchronization and mutual exclusion to shared resources – a mailbox built-in class - communication channel between processes – event data type to satisfy system-level synchronization requirements
SystemVerilog Introduction (35) Process Synchronization – Semaphores & Event Variables • Events – enhanced from V2K – Events are variables – can be copied, passed to tasks, etc. – event.triggered; // persists throughout timeslice, avoids races • Semaphore – Built-in Class – Synchronization for arbitration of shared resources, keys. – Mutual Exclusivity control – Built-in methods: new, get, put, try_get KEYS // main program ….. semaphore shrdBus =new; shared bus // usage, forking parallel ... // threads for cpu access
s event ev1,ev2; task go_cpu(id, event ev…) e r begin ... o ... h
@(ev) shrdBus.get () p fork a go_cpu(cpu1,ev1);
...//access granted m e
...//activity on the cpu bus s go_cpu(cpu2,ev2); shrdBus.put() ...... Cache CPU1 CPU2 Cache join endtask ...
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SystemVerilog Introduction (36) Process Synchronization - Mailbox • Mailbox features – FIFO message queue: passes data between threads – Can suspend thread, used for data checking • Mailbox built-in methods – new(), num(), put(), try_put(), get(), try_get(), peek(), try_peek()
Testbench compares the actual output with expected output [Packets] mailbox pktMbx = new; pktMbx.put(inPkt1); pktMbx.get(outPkt); compare_twoPackets;
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DUT output Input to Design
SystemVerilog Introduction (37) Process Synchronization - Example program • Threads are created via fork fork…join a c b a;b;c; • Threads execute until a join blocking statement fork a;b;c; c – mailbox, semaphore, etc a b join_any • “wait fork”; “disable fork” c fork a;b;c; are introduced a b join_none • $exit terminates the main c fork a;b;c; program thread a b join_any disable fork; // kill all child processes
fork a;b;c; a c b join_any wait fork; // wait for children to complete #10; $exit
SystemVerilog Introduction (38) Interface • An Interface Provides a new hierarchical structure – Encapsulates communication – Captures Interconnect and Communication – Separates Communication from Functionality – Eliminates “Wiring” Errors – Enables abstraction in the RTL
int i; int i; logic [7:0] a; wire [7:0] a;
typedef struct { interface intf; AAt tt hthee s simimpplelesst t int i; int i; level an interface logic [7:0] a; level an interface wire [7:0] a; is to a wire } s_type; is to a wire endinterface : intf wwhhaat ta a s strturucct ti sis toto a a v vaariraiabblele
SystemVerilog Introduction (39) How Interfaces work interface intf; bit A,B; byte C,D; modA intf modB logic E,F; endinterface Instantiate module top ( ); Interface An interface is similar to a module intf w; straddling two other modules
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Allows structuring the information flow between blocks
SystemVerilog Introduction (40) Example without Interface
module top; module memMod(input logic req, logic req,gnt,start,rdy; bit clk, bit clk = 0; logic start, logic [1:0] mode; logic[1:0] mode, logic [7:0] addr,data; logic[7:0] addr, inout logic[7:0] data, memMod mem(req,clk,start,mode, output logic gnt, addr,data,gnt,rdy); logic rdy); cpuMod cpu(clk,gnt,rdy,data, always @(posedge clk) req,start,addr,mode); gnt <= req & avail; endmodule endmodule Top clk module cpuMod(input bit clk,
logic gnt, req logic rdy, start inout logic [7:0] data, gnt rdy output logic req, mode[1:0] logic start, CPU Mem logic[7:0] addr, addr[7:0] logic[1:0] mode); data[7:0] endmodule
SystemVerilog Introduction (41) Example Using Interfaces
Bundle signals interface interface simple_bus; module top; in interface instance logic req,gnt; bit clk = 0; logic [7:0] addr,data; simple_bus sb_intf; Connect logic [1:0] mode; interface start,rdy; logic memMod mem(sb_intf, clk); endinterface: simple_bus cpuMod cpu(.b(sb_intf), Use interface .clk(clk)); keyword in port list endmodule module memMod(interface a, input bit clk); Top clk logic avail; always @(posedge clk) a.gnt <= a.req & avail; sb_intf endmodule Refer to intf CPU Mem signals module cpuMod(interface b, input bit clk); endmodule
SystemVerilog Introduction (42) Interface Verification Benefits
• Interfaces provide • Pre- tbA tbB tbI reusable I I Integration components I • tbA and tbB are A B ‘linked’ Test interface in isolation • Interface is an executable spec tbS • Wiring up is simple and not error S • Post-Integration prone A I B • Interfaces can contain protocol checkers and coverage counters Protocol bugs already flushed out
SystemVerilog Introduction (43) SystemVerilog Assertions • A concise description of desired / undesired behavior • Supports Assertion Based Verification methodology – White-box (inside block) assertions – Black-box (at interface boundaries) assertions • Usability – Easy to code, understand and use by Design and Verification Engineers • Monitoring the design – Concurrent (“standalone”) assertions – Procedural (“embedded”) assertions • Formalism – Formal semantics to ensure correct analysis – Consistent semantics between simulation and formal design validation approaches
SystemVerilog Introduction (44) Assertion Types • Two kinds of Assertions: Immediate and Concurrent • Immediate Assertions: – Appears as a procedural statement – Follows simulations semantics, like an “if” assert ( expression ) action_block; – Action block executes immediately and can contain system tasks to control severity, for example: $error, $warning • Concurrent Assertions: – Appears outside/inside procedural context – Follows cycle semantics using sampled values assert property ( property_instance_or_spec ) action_block; – Action block executes in reactive region and can contain system tasks to control severity, for example: $error, $warning
SystemVerilog Introduction (45) Assertions Example Ï “After request signal is asserted, acknowledge signal must come 1 to 3 cycles later” property req_ack; @(posedge clk) req ##[1:3] $rose(ack); SVA Assertion endproperty as_req_ack: assert property (req_ack);
always @(posedge req) begin repeat (1) @(posedge clk); fork: pos_pos 0 1 2 3 4 5 begin @(posedge ack) req $display("Assertion Success",$time); disable pos_pos; end ack begin Example intended behavior repeat (2) @(posedge clk); $display("Assertion Failure",$time); disable pos_pos; end join V2K Assertion end // always
SystemVerilog Introduction (46) Assertions Usage @Intel • RTL assertions are a powerful validation tool, and have been used in Intel for over a decade • Basic combinational assertions – Most are either FORBIDDEN or MUTEX • Sequential assertions improve the ability to capture design intent. Used to capture: – Assumptions on the interface – Expected output – Local relations • Template Library: consists of dozens of temporal and combinatorial properties for: – Safety Properties: expresses that "something bad will not happen" during a system execution – Liveness Properties: expresses that "something good must happen" during an execution
SystemVerilog Introduction (47) Assertions Usage @Intel
• Easier for designers to write assertions using the template library – No need to ramp-up on a formal specification language – Hides the subtle implementation details • RTL assertions caught >25% of all bugs! • High in bug hunting in CTE – right after designated CTE checkers • Very high in bug hunting at the FC level • RTL assertions were the first to fail • They were more local than checkers and mostly combinatorial • RTL assertions shortened the debug process • Assertions point directly at the bug
SystemVerilog Introduction (48) SystemVerilog DPI – WHY? Direct Programming Interface • Users need a simple way of invoking foreign functions from Verilog and getting results back • VPI and PLI are not easy to use – Even trivial usage requires detailed knowledge – Many users don’t need the sophisticated capabilities – Verilog can invoke C functions but C functions can’t invoke Verilog functions • SystemVerilog includes assertions. These were not addressed by any prior Verilog API • DPI and VPI extensions are based on Direct-C donation from Synopsys
SystemVerilog Introduction (49) SystemVerilog DPI - Overview
• DPI is a natural inter-language function call interface between SystemVerilog and C/C++ – The standard allows for other foreign languages in the future • DPI relies on C function call conventions and semantics • On each side, the calls look and behave the same as native function calls for that language – On SV side, DPI calls look and behave like native SV functions – On C side, DPI calls look and behave like native C functions • Binary or source code compatible – Binary compatible in absence of packed data types (svdpi.h) – Source code compatible otherwise (svdpi_src.h)
SystemVerilog Introduction (50) The QUIZ ÏQuestion: How do you get 20 Elephants into a Volkswagen beetle?
I don’t know! BUT …
SystemVerilog Introduction (51) QUIZ ‰How do you get module m( 20 lines of pipe1_clk ,pipe1_dat,pipe1_ctrl, Verilog into 4 pipe2_clk ,pipe2_dat,pipe2_ctrl); cm? input pipe1_clk,pipe1_dat,pipe1_ctrl; output pipe2_clk,pipe2_dat,pipe2_ctrl; wirepipe1_clk,pipe1_dat,pipe1_ctrl; regpipe2_clk,pipe2_dat,pipe2_ctrl; always @(pipe1_clk, pipe1_dat, pipe1_ctrl) begin typdef struct ( logic clk,dat,ctrl) pipe; pipe2_clk<=pipe1_clk; module m(input pipe pipe1, pipe2_dat<=pipe1_dat; output pipe pipe2); pipe2_ctrl<=pipe1_ctrl; always_comb end pipe2<= pipe1; endmodule endmodule
SystemVerilog Introduction (52) QUIZ ‰How do you get module m( 20 lines of pipe1_clk ,pipe1_dat,pipe1_ctrl, Verilog into 4 pipe2_clk ,pipe2_dat,pipe2_ctrl); cm? input pipe1_clk,pipe1_dat,pipe1_ctrl; output pipe2_clk,pipe2_dat,pipe2_ctrl; wirepipe1_clk,pipe1_dat,pipe1_ctrl; regpipe2_clk,pipe2_dat,pipe2_ctrl; always @(pipe1_clk, pipe1_dat, pipe1_ctrl)begin typdef struct ( logic clk,dat,ctrl) pipe; pipe2_clk<=pipe1_clk; module m(input pipe pipe1, pipe2_dat<=pipe1_dat; output pipe pipe2); pipe2_ctrl<=pipe1_ctrl; always_comb end pipe2<= pipe1; endmodule endmodule
SystemVerilog Introduction (53) Conclusions • SystemVerilog was demonstrated as: – The next generation of HW Design Language – Provides a comprehensive language coverage for Modeling and Verification (HDVL) – Enables design abstraction; more accurate modeling and capture of designer intent – Integrates to external languages – Has wide and increasing support in the EDA – Being used on real life complex design projects – Being standardized under IEEE P1800 with the goal of convergence with Verilog
SystemVerilog Introduction (54) Q&A
SystemVerilog Introduction (55) SystemVerilog & SystemC
ALG
C l eve ystem L m se for S e U n t Desig Architecture s y S g o l i r e V gn m TL Desi Abstract RTL e for R t Use s y S Netlist RTL
SSyysstteemm VVeerriilloogg && SSyysstteemm CC CCoommpplleemmeenntt EEaacchh Other in ARCH ‰ Physical Design Flow Other in ARCH ‰ Physical DesSigysntem FVleorilwog Introduction (56)